ci: bump action-build-driver to v0.4.0
This commit is contained in:
Enrico Weigelt, metux IT consult
commit
f825bb8a38
94 changed files with 69205 additions and 0 deletions
65
.github/ISSUE_TEMPLATE/01-bug-report.yml
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65
.github/ISSUE_TEMPLATE/01-bug-report.yml
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|||
name: 🐞 Bug report
|
||||
description: Create a report to help us improve
|
||||
|
||||
labels: [bug, needs-triage]
|
||||
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Please fill out the sections below to help everyone identify and fix the bug. If you have a general idea or question then please use the [discussions](https://github.com/orgs/X11Libre/discussions).
|
||||
- type: dropdown
|
||||
id: affected-version
|
||||
attributes:
|
||||
label: Select the version
|
||||
options:
|
||||
- 22.0.0.1
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||||
- Git master branch
|
||||
- other or don't know
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||||
default: 1
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: Describe your issue
|
||||
placeholder: When I did X then Y happened.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: steps
|
||||
attributes:
|
||||
label: Steps to reproduce
|
||||
placeholder: |
|
||||
1. Start ...
|
||||
2. Do this
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||||
3. Do that
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: expected
|
||||
attributes:
|
||||
label: What did you expect?
|
||||
placeholder: I expected this to happen.
|
||||
- type: textarea
|
||||
id: environment
|
||||
attributes:
|
||||
label: Additional Information
|
||||
description: |
|
||||
Additional information you want to provide such as logs, system info, environment, screenshots, etc.
|
||||
placeholder: |
|
||||
Add any other context about the bug here.
|
||||
- type: checkboxes
|
||||
id: checks
|
||||
attributes:
|
||||
label: Extra fields
|
||||
options:
|
||||
- label: I have checked the existing [issues](https://github.com/X11Libre/xf86-video-ati/issues)
|
||||
required: true
|
||||
- label: I have read the [Contributing Guidelines](https://github.com/X11Libre/xserver/blob/master/CONTRIBUTING.md)
|
||||
required: true
|
||||
- label: I'd like to work on this issue
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for reporting this issue! We will get back to you as soon as possible.
|
||||
49
.github/ISSUE_TEMPLATE/02-feature-request.yml
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49
.github/ISSUE_TEMPLATE/02-feature-request.yml
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|||
name: ✨ Feature request
|
||||
description: Suggest a feature for this software
|
||||
labels: [enhancement, needs-triage]
|
||||
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Please fill out the sections below to properly describe the new software feature you are suggesting. If you have a general idea or question then please use the [discussions](https://github.com/orgs/X11Libre/discussions).
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: "Describe the feature"
|
||||
placeholder: A thing in X that allows to do Y.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: rationale
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||||
attributes:
|
||||
label: "It should be done because"
|
||||
placeholder: Doing Y is needed for Z.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: alternative
|
||||
attributes:
|
||||
label: "What are the alternatives?"
|
||||
placeholder: We could do A or B instead.
|
||||
- type: textarea
|
||||
id: context
|
||||
attributes:
|
||||
label: Additional context
|
||||
description: Additional information you want to provide such as references to related issues or protocols, the implications on existing use cases, etc.
|
||||
placeholder: |
|
||||
Add any other context about the feature request here.
|
||||
- type: checkboxes
|
||||
id: checks
|
||||
attributes:
|
||||
label: Extra fields
|
||||
options:
|
||||
- label: I have checked the existing [issues](https://github.com/X11Libre/xf86-video-ati/issues)
|
||||
required: true
|
||||
- label: I have read the [Contributing Guidelines](https://github.com/X11Libre/xserver/blob/master/CONTRIBUTING.md)
|
||||
required: true
|
||||
- label: I'd like to work on this issue
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for your suggestion! Let's see together if it can be done.
|
||||
49
.github/ISSUE_TEMPLATE/03-code-cleanup.yml
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49
.github/ISSUE_TEMPLATE/03-code-cleanup.yml
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@ -0,0 +1,49 @@
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|||
name: 🔧 Code cleanup
|
||||
description: Level up the source code
|
||||
labels: [code-cleanup, needs-triage]
|
||||
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Please fill out the sections below to properly describe the code cleanup you are suggesting. If you have a general idea or question then please use the [discussions](https://github.com/orgs/X11Libre/discussions).
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: "Describe the cleanup"
|
||||
placeholder: C in X needs to be changed into D.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: rationale
|
||||
attributes:
|
||||
label: "It should be done because"
|
||||
placeholder: Having D is needed for E.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: alternative
|
||||
attributes:
|
||||
label: "What are the alternatives?"
|
||||
placeholder: We could do A or B instead.
|
||||
- type: textarea
|
||||
id: context
|
||||
attributes:
|
||||
label: Additional context
|
||||
description: Additional information you want to provide such as implications on existing code, how to ensure API/ABI stability, which tests are needed or to be run, related issues, etc.
|
||||
placeholder: |
|
||||
Add any other context about the cleanup here.
|
||||
- type: checkboxes
|
||||
id: checks
|
||||
attributes:
|
||||
label: Extra fields
|
||||
options:
|
||||
- label: I have checked the existing [issues](https://github.com/X11Libre/xf86-video-ati/issues)
|
||||
required: true
|
||||
- label: I have read the [Contributing Guidelines](https://github.com/X11Libre/xserver/blob/master/CONTRIBUTING.md)
|
||||
required: true
|
||||
- label: I'd like to work on this issue
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for looking at the source code! Let's see together how it can be improved.
|
||||
38
.github/ISSUE_TEMPLATE/04-doc-update.yml
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38
.github/ISSUE_TEMPLATE/04-doc-update.yml
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|||
name: 🔖 Documentation update
|
||||
description: Make your mark for better documentation
|
||||
|
||||
labels: [documentation, needs-triage]
|
||||
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Please fill out the sections below to help others understand our software. If you have a general idea or question then please use the [discussions](https://github.com/orgs/X11Libre/discussions).
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: Describe the update
|
||||
placeholder: These things need to be better documented.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: environment
|
||||
attributes:
|
||||
label: Additional Information
|
||||
description: Additional information you want to provide such as tickets related to changes in the software, affected files, screenshots, etc.
|
||||
placeholder: |
|
||||
Add any other context about the update here.
|
||||
- type: checkboxes
|
||||
id: checks
|
||||
attributes:
|
||||
label: Extra fields
|
||||
options:
|
||||
- label: I have checked the existing [issues](https://github.com/X11Libre/xf86-video-ati/issues)
|
||||
required: true
|
||||
- label: I have read the [Contributing Guidelines](https://github.com/X11Libre/xserver/blob/master/CONTRIBUTING.md)
|
||||
required: true
|
||||
- label: I'd like to work on this issue
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for requesting this update! We will get back to you as soon as possible.
|
||||
43
.github/ISSUE_TEMPLATE/05-org-task.yml
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43
.github/ISSUE_TEMPLATE/05-org-task.yml
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@ -0,0 +1,43 @@
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|||
name: ✅ Organizational task
|
||||
description: Create a task for project organization
|
||||
|
||||
labels: [needs-triage, organization]
|
||||
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Please fill out the sections below to get organizational things done. If you have a general idea or question then please use the [discussions](https://github.com/orgs/X11Libre/discussions).
|
||||
- type: textarea
|
||||
id: description
|
||||
attributes:
|
||||
label: Describe the task
|
||||
placeholder: These things need to be done.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: rationale
|
||||
attributes:
|
||||
label: "It should be done because"
|
||||
placeholder: Doing Y is needed for Z.
|
||||
- type: textarea
|
||||
id: environment
|
||||
attributes:
|
||||
label: Additional Information
|
||||
description: Additional information you want to provide such as the context for bigger tasks, the implicatons on existing workflows, related issues, etc.
|
||||
placeholder: |
|
||||
Add any other context about the task here.
|
||||
- type: checkboxes
|
||||
id: checks
|
||||
attributes:
|
||||
label: Extra fields
|
||||
options:
|
||||
- label: I have checked the existing [issues](https://github.com/X11Libre/xf86-video-ati/issues)
|
||||
required: true
|
||||
- label: I have read the [Contributing Guidelines](https://github.com/X11Libre/xserver/blob/master/CONTRIBUTING.md)
|
||||
required: true
|
||||
- label: I'd like to work on this issue
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: |
|
||||
Thanks for adding this task! We will get back to you as soon as possible.
|
||||
8
.github/ISSUE_TEMPLATE/config.yml
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8
.github/ISSUE_TEMPLATE/config.yml
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@ -0,0 +1,8 @@
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|||
blank_issues_enabled: false
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||||
contact_links:
|
||||
- name: XLibre Community Support
|
||||
url: https://github.com/orgs/X11Libre/discussions
|
||||
about: Please ask and answer questions here.
|
||||
- name: Mailing List
|
||||
url: https://www.freelists.org/list/xlibre
|
||||
about: You can join the discussions on our mailing list.
|
||||
58
.github/workflows/build.yml
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58
.github/workflows/build.yml
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|||
permissions:
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||||
contents: write
|
||||
|
||||
on:
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||||
push:
|
||||
pull_request:
|
||||
|
||||
jobs:
|
||||
ubuntu:
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||||
strategy:
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||||
matrix:
|
||||
xserver-version: [ master, xlibre-xserver-25.1.0, xlibre-xserver-25.0.0.18 ]
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: X11Libre/action-build-driver/target/ubuntu@v0.4.0
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||||
with:
|
||||
xserver-version: ${{ matrix.xserver-version }}
|
||||
|
||||
freebsd:
|
||||
strategy:
|
||||
matrix:
|
||||
xserver-version: [ master, xlibre-xserver-25.1.0, xlibre-xserver-25.0.0.18 ]
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: X11Libre/action-build-driver/target/freebsd@v0.4.0
|
||||
with:
|
||||
xserver-version: ${{ matrix.xserver-version }}
|
||||
|
||||
dragonfly:
|
||||
strategy:
|
||||
matrix:
|
||||
# xlibre-xserver-25.0.x not compiling on dragonfly yet
|
||||
xserver-version: [ master, xlibre-xserver-25.1.0 ]
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: X11Libre/action-build-driver/target/dragonfly@v0.4.0
|
||||
with:
|
||||
xserver-version: ${{ matrix.xserver-version }}
|
||||
|
||||
netbsd:
|
||||
strategy:
|
||||
matrix:
|
||||
xserver-version: [ master, xlibre-xserver-25.1.0 ]
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: X11Libre/action-build-driver/target/netbsd@v0.4.0
|
||||
with:
|
||||
xserver-version: ${{ matrix.xserver-version }}
|
||||
|
||||
release-notes:
|
||||
name: Release pushed tag
|
||||
runs-on: ubuntu-latest
|
||||
if: ${{ startsWith(github.ref, 'refs/tags/xlibre-') }}
|
||||
needs: [ ubuntu, freebsd, dragonfly, netbsd ]
|
||||
env:
|
||||
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
|
||||
steps:
|
||||
- uses: X11Libre/action-build-driver/release@v0.4.0
|
||||
73
.gitignore
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.gitignore
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|||
#
|
||||
# X.Org module default exclusion patterns
|
||||
# The next section if for module specific patterns
|
||||
#
|
||||
# Do not edit the following section
|
||||
# GNU Build System (Autotools)
|
||||
aclocal.m4
|
||||
autom4te.cache/
|
||||
autoscan.log
|
||||
ChangeLog
|
||||
compile
|
||||
config.guess
|
||||
config.h
|
||||
config.h.in
|
||||
config.log
|
||||
config-ml.in
|
||||
config.py
|
||||
config.status
|
||||
config.status.lineno
|
||||
config.sub
|
||||
configure
|
||||
configure.scan
|
||||
depcomp
|
||||
.deps/
|
||||
INSTALL
|
||||
install-sh
|
||||
.libs/
|
||||
libtool
|
||||
ltmain.sh
|
||||
Makefile
|
||||
Makefile.in
|
||||
mdate-sh
|
||||
missing
|
||||
mkinstalldirs
|
||||
*.pc
|
||||
py-compile
|
||||
stamp-h?
|
||||
symlink-tree
|
||||
texinfo.tex
|
||||
ylwrap
|
||||
|
||||
# Do not edit the following section
|
||||
# Edit Compile Debug Document Distribute
|
||||
*~
|
||||
*.[0-9]
|
||||
*.[0-9]x
|
||||
*.bak
|
||||
*.bin
|
||||
core
|
||||
*.dll
|
||||
*.exe
|
||||
*-ISO*.bdf
|
||||
*-JIS*.bdf
|
||||
*-KOI8*.bdf
|
||||
*.kld
|
||||
*.ko
|
||||
*.ko.cmd
|
||||
*.lai
|
||||
*.l[oa]
|
||||
*.[oa]
|
||||
*.obj
|
||||
*.patch
|
||||
*.so
|
||||
*.pcf.gz
|
||||
*.pdb
|
||||
*.tar.bz2
|
||||
*.tar.gz
|
||||
#
|
||||
# Add & Override patterns for xf86-video-ati
|
||||
#
|
||||
# Edit the following section as needed
|
||||
# For example, !report.pc overrides *.pc. See 'man gitignore'
|
||||
#
|
||||
129
COPYING
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129
COPYING
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
|
||||
Permission to use, copy, modify, distribute, and sell this software and its
|
||||
documentation for any purpose is hereby granted without fee, provided that
|
||||
the above copyright notice appear in all copies and that both that copyright
|
||||
notice and this permission notice appear in supporting documentation, and
|
||||
that the name of Marc Aurele La France not be used in advertising or
|
||||
publicity pertaining to distribution of the software without specific,
|
||||
written prior permission. Marc Aurele La France makes no representations
|
||||
about the suitability of this software for any purpose. It is provided
|
||||
"as-is" without express or implied warranty.
|
||||
|
||||
MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
PERFORMANCE OF THIS SOFTWARE.
|
||||
|
||||
Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net
|
||||
Copyright (c) 1995-2003 by The XFree86 Project, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of the copyright holder(s)
|
||||
and author(s) shall not be used in advertising or otherwise to promote
|
||||
the sale, use or other dealings in this Software without prior written
|
||||
authorization from the copyright holder(s) and author(s).
|
||||
|
||||
Copyright 2006-2007 Advanced Micro Devices, Inc.
|
||||
Copyright 2007 Egbert Eich <eich@novell.com>
|
||||
Copyright 2007 Matthias Hopf <mhopf@novell.com>
|
||||
Copyright (C) 1999-2001 Brian Paul All Rights Reserved.
|
||||
Copyright 2007 Luc Verhaegen <lverhaegen@novell.com>
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Copyright 2007 Advanced Micro Devices, Inc.
|
||||
Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
Copyright 2004 Eric Anholt
|
||||
Copyright 2005 Eric Anholt
|
||||
Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
|
||||
Copyright 2004 ATI Technologies Inc., Markham, Ontario
|
||||
Copyright (C) 2008-2009 Alexander Deucher
|
||||
Copyright 2008 Jérôme Glisse
|
||||
Copyright 2005 Benjamin Herrenschmidt
|
||||
Copyright 2008 Kristian Høgsberg
|
||||
Copyright (C) 2008-2009 Matthias Hopf
|
||||
Copyright (c) 2006 Itronix Inc.
|
||||
Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
|
||||
Copyright © 2007 Red Hat, Inc.
|
||||
Copyright © 2009 Red Hat, Inc.
|
||||
Copyright 2007 George Sapountzis
|
||||
Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
|
||||
Copyright 2006 Tungsten Graphics, Inc.
|
||||
Copyright 2000 VA Linux Systems, Inc., Fremont, California.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the next
|
||||
paragraph) shall be included in all copies or substantial portions of the
|
||||
Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
|
||||
Copyright © 2006 Keith Packard
|
||||
|
||||
Permission to use, copy, modify, distribute, and sell this software and its
|
||||
documentation for any purpose is hereby granted without fee, provided that
|
||||
the above copyright notice appear in all copies and that both that copyright
|
||||
notice and this permission notice appear in supporting documentation, and
|
||||
that the name of the copyright holders not be used in advertising or
|
||||
publicity pertaining to distribution of the software without specific,
|
||||
written prior permission. The copyright holders make no representations
|
||||
about the suitability of this software for any purpose. It is provided "as
|
||||
is" without express or implied warranty.
|
||||
|
||||
THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
|
||||
OF THIS SOFTWARE.
|
||||
|
||||
38
Makefile.am
Normal file
38
Makefile.am
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
# Copyright 2005 Adam Jackson.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
# During distcheck, system locations (as provided by pkg-config) may
|
||||
# not be writable; provide instead relative locations.
|
||||
DISTCHECK_CONFIGURE_FLAGS = --with-xorg-module-dir='$${libdir}/xorg/modules'
|
||||
|
||||
SUBDIRS = src man conf
|
||||
MAINTAINERCLEANFILES = ChangeLog INSTALL
|
||||
|
||||
ACLOCAL_AMFLAGS = -I m4
|
||||
|
||||
.PHONY: ChangeLog INSTALL
|
||||
|
||||
INSTALL:
|
||||
$(INSTALL_CMD)
|
||||
|
||||
ChangeLog:
|
||||
$(CHANGELOG_CMD)
|
||||
|
||||
EXTRA_DIST = ChangeLog INSTALL README.md
|
||||
9
README.md
Normal file
9
README.md
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
xf86-video-ati - Xorg driver for ATI/AMD Radeon GPUs using the radeon kernel driver
|
||||
===================================================================================
|
||||
|
||||
Questions regarding this software should be directed at the
|
||||
[amd-gfx mailing list](https://lists.freedesktop.org/mailman/listinfo/amd-gfx).
|
||||
|
||||
[main development code repository](https://github.com/X11Libre/xf86-video-ati)
|
||||
|
||||
Please submit bug reports there and use merge requests for patch submission.
|
||||
17
autogen.sh
Executable file
17
autogen.sh
Executable file
|
|
@ -0,0 +1,17 @@
|
|||
#! /bin/sh
|
||||
|
||||
srcdir=`dirname "$0"`
|
||||
test -z "$srcdir" && srcdir=.
|
||||
|
||||
ORIGDIR=`pwd`
|
||||
cd "$srcdir"
|
||||
|
||||
autoreconf -f -v --install || exit 1
|
||||
cd "$ORIGDIR" || exit $?
|
||||
|
||||
git config --local --get format.subjectPrefix >/dev/null 2>&1 ||
|
||||
git config --local format.subjectPrefix "PATCH xf86-video-ati"
|
||||
|
||||
if test -z "$NOCONFIGURE"; then
|
||||
exec "$srcdir"/configure "$@"
|
||||
fi
|
||||
5
conf/10-radeon.conf
Normal file
5
conf/10-radeon.conf
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
Section "OutputClass"
|
||||
Identifier "Radeon"
|
||||
MatchDriver "radeon"
|
||||
Driver "radeon"
|
||||
EndSection
|
||||
22
conf/Makefile.am
Normal file
22
conf/Makefile.am
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# Copyright 2017 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
dist_config_DATA = 10-radeon.conf
|
||||
239
configure.ac
Normal file
239
configure.ac
Normal file
|
|
@ -0,0 +1,239 @@
|
|||
# Copyright 2005 Adam Jackson.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
#
|
||||
# Process this file with autoconf to produce a configure script
|
||||
|
||||
# Initialize Autoconf
|
||||
AC_PREREQ([2.60])
|
||||
AC_INIT([xlibre-xf86-video-ati],
|
||||
[25.0.1],
|
||||
[https://github.com/X11Libre/xf86-video-ati/issues],
|
||||
[xlibre-xf86-video-ati])
|
||||
|
||||
AC_CONFIG_SRCDIR([Makefile.am])
|
||||
AC_CONFIG_HEADERS([config.h])
|
||||
AC_CONFIG_MACRO_DIR([m4])
|
||||
|
||||
AC_CONFIG_AUX_DIR(.)
|
||||
|
||||
# Initialize Automake
|
||||
AM_INIT_AUTOMAKE([foreign dist-xz])
|
||||
|
||||
# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
|
||||
m4_ifndef([XORG_MACROS_VERSION],
|
||||
[m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])])
|
||||
XORG_MACROS_VERSION(1.8)
|
||||
XORG_DEFAULT_OPTIONS
|
||||
|
||||
# Initialize libtool
|
||||
AC_DISABLE_STATIC
|
||||
LT_INIT
|
||||
|
||||
# Checks for programs.
|
||||
AM_PROG_CC_C_O
|
||||
|
||||
if test "x$GCC" = "xyes"; then
|
||||
CPPFLAGS="$CPPFLAGS -Wall"
|
||||
fi
|
||||
|
||||
AH_TOP([#include "xorg-server.h"])
|
||||
|
||||
# Define a configure option for an alternate module directory
|
||||
PKG_PROG_PKG_CONFIG([0.25])
|
||||
AC_ARG_WITH(xorg-module-dir,
|
||||
AS_HELP_STRING([--with-xorg-module-dir=DIR],
|
||||
[Default xorg module directory]),
|
||||
[moduledir="$withval"],
|
||||
[moduledir=`$PKG_CONFIG --variable=moduledir xorg-server`])
|
||||
|
||||
# Store the list of server defined optional extensions in REQUIRED_MODULES
|
||||
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
|
||||
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
|
||||
XORG_DRIVER_CHECK_EXT(XV, videoproto)
|
||||
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
|
||||
|
||||
# Checks for libraries.
|
||||
PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.89])
|
||||
PKG_CHECK_MODULES(LIBDRM_RADEON, [libdrm_radeon])
|
||||
|
||||
# Obtain compiler/linker options for the driver dependencies
|
||||
PKG_CHECK_MODULES(XORG, [xorg-server >= 25.0.0 xproto fontsproto xf86driproto $REQUIRED_MODULES])
|
||||
PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1])
|
||||
|
||||
# Define a configure option for an alternate X Server configuration directory
|
||||
AC_ARG_WITH(xorg-conf-dir,
|
||||
AS_HELP_STRING([--with-xorg-conf-dir=DIR],
|
||||
[Default xorg.conf.d directory [[default=${prefix}/share/X11/xorg.conf.d]]]),
|
||||
[configdir="$withval"],
|
||||
[configdir='${prefix}/share/X11/xorg.conf.d'])
|
||||
AC_SUBST(configdir)
|
||||
|
||||
AC_ARG_ENABLE([udev],
|
||||
AS_HELP_STRING([--disable-udev], [Disable libudev support [default=auto]]),
|
||||
[enable_udev="$enableval"],
|
||||
[enable_udev=auto])
|
||||
if test "x$enable_udev" != "xno"; then
|
||||
PKG_CHECK_MODULES(LIBUDEV, [libudev], [LIBUDEV=yes], [LIBUDEV=no])
|
||||
if test "x$LIBUDEV" = xyes; then
|
||||
AC_DEFINE(HAVE_LIBUDEV, 1,[libudev support])
|
||||
elif test "x$enable_udev" != "xauto"; then
|
||||
AC_MSG_ERROR([Building with udev requested but libudev not found])
|
||||
fi
|
||||
fi
|
||||
AM_CONDITIONAL(LIBUDEV, test x$LIBUDEV = xyes)
|
||||
|
||||
SAVE_CPPFLAGS="$CPPFLAGS"
|
||||
CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
|
||||
|
||||
AC_MSG_CHECKING([whether to include GLAMOR support])
|
||||
AC_ARG_ENABLE(glamor,
|
||||
AS_HELP_STRING([--disable-glamor],
|
||||
[Disable glamor, a new GL-based acceleration [default=enabled]]),
|
||||
[GLAMOR="$enableval"],
|
||||
[GLAMOR=yes])
|
||||
|
||||
if test "x$GLAMOR" != "xno"; then
|
||||
AC_CHECK_HEADERS([glamor.h], [GLAMOR_H="yes"], [GLAMOR_H="no"], [#include "xorg-server.h"])
|
||||
|
||||
if test "x$GLAMOR_H" = xyes; then
|
||||
AC_CHECK_DECL(GLAMOR_NO_DRI3,
|
||||
[GLAMOR_XSERVER="yes"], [GLAMOR_XSERVER="no"],
|
||||
[#include "xorg-server.h"
|
||||
#include "glamor.h"])
|
||||
|
||||
AC_CHECK_DECL(glamor_glyphs_init,
|
||||
[AC_DEFINE(HAVE_GLAMOR_GLYPHS_INIT, 1,
|
||||
[Have glamor_glyphs_init API])], [],
|
||||
[#include "xorg-server.h"
|
||||
#include "glamor.h"])
|
||||
|
||||
AC_CHECK_DECL(glamor_finish,
|
||||
[AC_DEFINE(HAVE_GLAMOR_FINISH, 1,
|
||||
[Have glamor_finish API])],
|
||||
[PKG_CHECK_MODULES(LIBGL, [gl])],
|
||||
[#include "xorg-server.h"
|
||||
#include "glamor.h"])
|
||||
fi
|
||||
|
||||
if test "x$GLAMOR_XSERVER" != xyes; then
|
||||
PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0])
|
||||
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
|
||||
fi
|
||||
|
||||
PKG_CHECK_MODULES(GBM, [gbm >= 10.6])
|
||||
|
||||
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
|
||||
else
|
||||
AC_MSG_RESULT([$GLAMOR])
|
||||
fi
|
||||
AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno)
|
||||
|
||||
AC_CHECK_DECL(xf86CursorResetCursor,
|
||||
[AC_DEFINE(HAVE_XF86_CURSOR_RESET_CURSOR, 1,
|
||||
[Have xf86CursorResetCursor API])], [],
|
||||
[#include <xorg-server.h>
|
||||
#include <xf86Cursor.h>])
|
||||
|
||||
CPPFLAGS="$SAVE_CPPFLAGS"
|
||||
|
||||
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
|
||||
XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
|
||||
|
||||
# Checks for headers/macros for byte swapping
|
||||
# Known variants:
|
||||
# <byteswap.h> bswap_16, bswap_32 (glibc)
|
||||
# <sys/endian.h> __swap16, __swap32, __swap64 (OpenBSD)
|
||||
# <sys/endian.h> bswap16, bswap32 (other BSD's)
|
||||
# and a fallback to local macros if none of the above are found
|
||||
|
||||
# if <byteswap.h> is found, assume it's the correct version
|
||||
AC_CHECK_HEADERS([byteswap.h])
|
||||
|
||||
# if <sys/endian.h> is found, have to check which version
|
||||
AC_CHECK_HEADER([sys/endian.h], [HAVE_SYS_ENDIAN_H="yes"], [HAVE_SYS_ENDIAN_H="no"])
|
||||
|
||||
if test "x$HAVE_SYS_ENDIAN_H" = "xyes" ; then
|
||||
AC_MSG_CHECKING([for __swap16 variant of <sys/endian.h> byteswapping macros])
|
||||
AC_LINK_IFELSE([AC_LANG_PROGRAM([
|
||||
#include <sys/types.h>
|
||||
#include <sys/endian.h>
|
||||
], [
|
||||
int a = 1, b;
|
||||
b = __swap16(a);
|
||||
])
|
||||
], [SYS_ENDIAN__SWAP='yes'], [SYS_ENDIAN__SWAP='no'])
|
||||
AC_MSG_RESULT([$SYS_ENDIAN__SWAP])
|
||||
|
||||
AC_MSG_CHECKING([for bswap16 variant of <sys/endian.h> byteswapping macros])
|
||||
AC_LINK_IFELSE([AC_LANG_PROGRAM([
|
||||
#include <sys/types.h>
|
||||
#include <sys/endian.h>
|
||||
], [
|
||||
int a = 1, b;
|
||||
b = bswap16(a);
|
||||
])
|
||||
], [SYS_ENDIAN_BSWAP='yes'], [SYS_ENDIAN_BSWAP='no'])
|
||||
AC_MSG_RESULT([$SYS_ENDIAN_BSWAP])
|
||||
|
||||
if test "$SYS_ENDIAN_BSWAP" = "yes" ; then
|
||||
USE_SYS_ENDIAN_H=yes
|
||||
BSWAP=bswap
|
||||
else
|
||||
if test "$SYS_ENDIAN__SWAP" = "yes" ; then
|
||||
USE_SYS_ENDIAN_H=yes
|
||||
BSWAP=__swap
|
||||
else
|
||||
USE_SYS_ENDIAN_H=no
|
||||
fi
|
||||
fi
|
||||
|
||||
if test "$USE_SYS_ENDIAN_H" = "yes" ; then
|
||||
AC_DEFINE([USE_SYS_ENDIAN_H], 1,
|
||||
[Define to use byteswap macros from <sys/endian.h>])
|
||||
AC_DEFINE_UNQUOTED([radeon_bswap_16], ${BSWAP}16,
|
||||
[Define to 16-bit byteswap macro])
|
||||
AC_DEFINE_UNQUOTED([radeon_bswap_32], ${BSWAP}32,
|
||||
[Define to 32-bit byteswap macro])
|
||||
fi
|
||||
fi
|
||||
|
||||
AC_SUBST([moduledir])
|
||||
|
||||
AC_CONFIG_FILES([Makefile src/Makefile man/Makefile conf/Makefile])
|
||||
AC_OUTPUT
|
||||
|
||||
dnl
|
||||
dnl Output some configuration info for the user
|
||||
dnl
|
||||
echo ""
|
||||
echo " prefix: $prefix"
|
||||
echo " exec_prefix: $exec_prefix"
|
||||
echo " libdir: $libdir"
|
||||
echo " includedir: $includedir"
|
||||
echo " configdir: $configdir"
|
||||
|
||||
echo ""
|
||||
echo " CFLAGS: $CFLAGS"
|
||||
echo " CXXFLAGS: $CXXFLAGS"
|
||||
echo " Macros: $DEFINES"
|
||||
|
||||
echo ""
|
||||
echo " Run '${MAKE-make}' to build xf86-video-ati"
|
||||
echo ""
|
||||
5
m4/.gitignore
vendored
Normal file
5
m4/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
libtool.m4
|
||||
lt~obsolete.m4
|
||||
ltoptions.m4
|
||||
ltsugar.m4
|
||||
ltversion.m4
|
||||
41
man/Makefile.am
Normal file
41
man/Makefile.am
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
#
|
||||
# Copyright 2005 Sun Microsystems, Inc. All rights reserved.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
# and/or sell copies of the Software, and to permit persons to whom the
|
||||
# Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
# DEALINGS IN THE SOFTWARE.
|
||||
#
|
||||
|
||||
drivermandir = $(DRIVER_MAN_DIR)
|
||||
|
||||
driverman_PRE = ati.man radeon.man
|
||||
|
||||
driverman_DATA = $(driverman_PRE:man=@DRIVER_MAN_SUFFIX@)
|
||||
|
||||
EXTRA_DIST = ati.man radeon.man
|
||||
|
||||
CLEANFILES = $(driverman_DATA)
|
||||
|
||||
|
||||
# String replacements in MAN_SUBSTS now come from xorg-macros.m4 via configure
|
||||
|
||||
|
||||
SUFFIXES = .$(DRIVER_MAN_SUFFIX) .man
|
||||
|
||||
.man.$(DRIVER_MAN_SUFFIX):
|
||||
$(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@
|
||||
43
man/ati.man
Normal file
43
man/ati.man
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
.\" shorthand for double quote that works everywhere.
|
||||
.ds q \N'34'
|
||||
.TH ATI __drivermansuffix__ 2010-12-02 __vendorversion__
|
||||
.SH NAME
|
||||
ati \- ATI video wrapper driver for XLibre
|
||||
.SH SYNOPSIS
|
||||
.nf
|
||||
.B "Section \*qDevice\*q"
|
||||
.BI " Identifier \*q" devname \*q
|
||||
.B " Driver \*qati\*q"
|
||||
\ \ ...
|
||||
.B EndSection
|
||||
.fi
|
||||
.SH DESCRIPTION
|
||||
.B ati
|
||||
is an XLibre wrapper driver for ATI video cards.
|
||||
It autodetects whether your hardware has a
|
||||
Radeon, Rage 128, or Mach64 or earlier class of chipset, and loads the
|
||||
.BR radeon (__drivermansuffix__),
|
||||
.BR r128 (__drivermansuffix__),
|
||||
or
|
||||
.B mach64
|
||||
driver as appropriate.
|
||||
.SH SUPPORTED HARDWARE
|
||||
The
|
||||
.B ati
|
||||
driver supports Radeon, Rage 128, and Mach64 and earlier chipsets by loading
|
||||
those drivers.
|
||||
See those manpages for specific cards supported.
|
||||
.SH CONFIGURATION DETAILS
|
||||
Please refer to
|
||||
.BR xorg.conf(__filemansuffix__)
|
||||
for general configuration details,
|
||||
and the specific card driver for driver configuration details.
|
||||
.SH "SEE ALSO"
|
||||
.BR XLibre (__appmansuffix__),
|
||||
.BR xorg.conf (__filemansuffix__),
|
||||
.BR Xserver (__appmansuffix__),
|
||||
.BR X (__miscmansuffix__),
|
||||
.BR r128 (__drivermansuffix__),
|
||||
.BR radeon (__drivermansuffix__)
|
||||
.SH AUTHORS
|
||||
See the individual driver pages for authors.
|
||||
443
man/radeon.man
Normal file
443
man/radeon.man
Normal file
|
|
@ -0,0 +1,443 @@
|
|||
.ds q \N'34'
|
||||
.TH RADEON __drivermansuffix__ 2024-09-29 __vendorversion__
|
||||
.SH NAME
|
||||
radeon \- ATI/AMD RADEON video driver for XLibre
|
||||
.SH SYNOPSIS
|
||||
.nf
|
||||
.B "Section \*qDevice\*q"
|
||||
.BI " Identifier \*q" devname \*q
|
||||
.B " Driver \*qradeon\*q"
|
||||
\ \ ...
|
||||
.B EndSection
|
||||
.fi
|
||||
.SH DESCRIPTION
|
||||
.B radeon
|
||||
is an XLibre driver for ATI/AMD RADEON-based video cards with the
|
||||
following features:
|
||||
.PP
|
||||
.PD 0
|
||||
.TP 2
|
||||
\(bu
|
||||
Full support for 8-, 15-, 16- and 24-bit pixel depths,
|
||||
and for 30-bit depth on Linux 3.16 and later;
|
||||
.TP
|
||||
\(bu
|
||||
RandR 1.2 and RandR 1.3 support;
|
||||
.TP
|
||||
\(bu
|
||||
Full EXA 2D acceleration;
|
||||
.TP
|
||||
\(bu
|
||||
Textured XVideo acceleration including anti-tearing support (Bicubic filtering
|
||||
only available on R/RV3xx, R/RV/RS4xx, R/RV5xx, and RS6xx/RS740);
|
||||
.TP
|
||||
\(bu
|
||||
3D acceleration;
|
||||
.PD
|
||||
.SH SUPPORTED HARDWARE
|
||||
The
|
||||
.B radeon
|
||||
driver supports PCI, AGP, and PCIe video cards based on
|
||||
the following ATI/AMD chips
|
||||
(note: list is non-exhaustive):
|
||||
.PP
|
||||
.PD 0
|
||||
.TP 12
|
||||
.B R100
|
||||
Radeon 7200
|
||||
.TP 12
|
||||
.B RV100
|
||||
Radeon 7000(VE), M6, RN50/ES1000
|
||||
.TP 12
|
||||
.B RS100
|
||||
Radeon IGP320(M)
|
||||
.TP 12
|
||||
.B RV200
|
||||
Radeon 7500, M7, FireGL 7800
|
||||
.TP 12
|
||||
.B RS200
|
||||
Radeon IGP330(M)/IGP340(M)
|
||||
.TP 12
|
||||
.B RS250
|
||||
Radeon Mobility 7000 IGP
|
||||
.TP 12
|
||||
.B R200
|
||||
Radeon 8500, 9100, FireGL 8800/8700
|
||||
.TP 12
|
||||
.B RV250
|
||||
Radeon 9000PRO/9000, M9
|
||||
.TP 12
|
||||
.B RV280
|
||||
Radeon 9200PRO/9200/9200SE/9250, M9+
|
||||
.TP 12
|
||||
.B RS300
|
||||
Radeon 9100 IGP
|
||||
.TP 12
|
||||
.B RS350
|
||||
Radeon 9200 IGP
|
||||
.TP 12
|
||||
.B RS400/RS480
|
||||
Radeon XPRESS 200(M)/1100 IGP
|
||||
.TP 12
|
||||
.B R300
|
||||
Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1
|
||||
.TP 12
|
||||
.B R350
|
||||
Radeon 9800PRO/9800SE/9800, FireGL X2
|
||||
.TP 12
|
||||
.B R360
|
||||
Radeon 9800XT
|
||||
.TP 12
|
||||
.B RV350
|
||||
Radeon 9600PRO/9600SE/9600/9550, M10/M11, FireGL T2
|
||||
.TP 12
|
||||
.B RV360
|
||||
Radeon 9600XT
|
||||
.TP 12
|
||||
.B RV370
|
||||
Radeon X300, M22
|
||||
.TP 12
|
||||
.B RV380
|
||||
Radeon X600, M24
|
||||
.TP 12
|
||||
.B RV410
|
||||
Radeon X700, M26 PCIe
|
||||
.TP 12
|
||||
.B R420
|
||||
Radeon X800 AGP
|
||||
.TP 12
|
||||
.B R423/R430
|
||||
Radeon X800, M28 PCIe
|
||||
.TP 12
|
||||
.B R480/R481
|
||||
Radeon X850 PCIe/AGP
|
||||
.TP 12
|
||||
.B RV505/RV515/RV516/RV550
|
||||
Radeon X1300/X1400/X1500/X1550/X2300
|
||||
.TP 12
|
||||
.B R520
|
||||
Radeon X1800
|
||||
.TP 12
|
||||
.B RV530/RV560
|
||||
Radeon X1600/X1650/X1700
|
||||
.TP 12
|
||||
.B RV570/R580
|
||||
Radeon X1900/X1950
|
||||
.TP 12
|
||||
.B RS600/RS690/RS740
|
||||
Radeon X1200/X1250/X2100
|
||||
.TP 12
|
||||
.B R600
|
||||
Radeon HD 2900
|
||||
.TP 12
|
||||
.B RV610/RV630
|
||||
Radeon HD 2400/2600/2700/4200/4225/4250
|
||||
.TP 12
|
||||
.B RV620/RV635
|
||||
Radeon HD 3410/3430/3450/3470/3650/3670
|
||||
.TP 12
|
||||
.B RV670
|
||||
Radeon HD 3690/3850/3870
|
||||
.TP 12
|
||||
.B RS780/RS880
|
||||
Radeon HD 3100/3200/3300/4100/4200/4250/4290
|
||||
.TP 12
|
||||
.B RV710/RV730
|
||||
Radeon HD 4330/4350/4550/4650/4670/5145/5165/530v/545v/560v/565v
|
||||
.TP 12
|
||||
.B RV740/RV770/RV790
|
||||
Radeon HD 4770/4730/4830/4850/4860/4870/4890
|
||||
.TP 12
|
||||
.B CEDAR
|
||||
Radeon HD 5430/5450/6330/6350/6370
|
||||
.TP 12
|
||||
.B REDWOOD
|
||||
Radeon HD 5550/5570/5650/5670/5730/5750/5770/6530/6550/6570
|
||||
.TP 12
|
||||
.B JUNIPER
|
||||
Radeon HD 5750/5770/5830/5850/5870/6750/6770/6830/6850/6870
|
||||
.TP 12
|
||||
.B CYPRESS
|
||||
Radeon HD 5830/5850/5870
|
||||
.TP 12
|
||||
.B HEMLOCK
|
||||
Radeon HD 5970
|
||||
.TP 12
|
||||
.B PALM
|
||||
Radeon HD 6310/6250
|
||||
.TP 12
|
||||
.B SUMO/SUMO2
|
||||
Radeon HD 6370/6380/6410/6480/6520/6530/6550/6620
|
||||
.TP 12
|
||||
.B BARTS
|
||||
Radeon HD 6790/6850/6870/6950/6970/6990
|
||||
.TP 12
|
||||
.B TURKS
|
||||
Radeon HD 6570/6630/6650/6670/6730/6750/6770
|
||||
.TP 12
|
||||
.B CAICOS
|
||||
Radeon HD 6430/6450/6470/6490
|
||||
.TP 12
|
||||
.B CAYMAN
|
||||
Radeon HD 6950/6970/6990
|
||||
.TP 12
|
||||
.B ARUBA
|
||||
Radeon HD 7000 series
|
||||
.TP 12
|
||||
.B TAHITI
|
||||
Radeon HD 7900 series
|
||||
.TP 12
|
||||
.B PITCAIRN
|
||||
Radeon HD 7800 series
|
||||
.TP 12
|
||||
.B VERDE
|
||||
Radeon HD 7700 series
|
||||
.TP 12
|
||||
.B OLAND
|
||||
Radeon HD 8000 series
|
||||
.TP 12
|
||||
.B HAINAN
|
||||
Radeon HD 8000 series
|
||||
.TP 12
|
||||
.B BONAIRE
|
||||
Radeon HD 7790 series
|
||||
.TP 12
|
||||
.B KAVERI
|
||||
KAVERI APUs
|
||||
.TP 12
|
||||
.B KABINI
|
||||
KABINI APUs
|
||||
.TP 12
|
||||
.B HAWAII
|
||||
Radeon R9 series
|
||||
.TP 12
|
||||
.B MULLINS
|
||||
MULLINS APUs
|
||||
.PD
|
||||
.SH CONFIGURATION DETAILS
|
||||
Please refer to
|
||||
.BR xorg.conf (__filemansuffix__)
|
||||
for general configuration details.
|
||||
This section only covers configuration details specific to this driver.
|
||||
.PP
|
||||
The following driver
|
||||
.B Options
|
||||
are supported:
|
||||
.TP
|
||||
.BI "Option \*qSWcursor\*q \*q" boolean \*q
|
||||
Selects software cursor.
|
||||
The default is
|
||||
.B off.
|
||||
.TP
|
||||
.BI "Option \*qAccel\*q \*q" boolean \*q
|
||||
Enables or disables all hardware acceleration.
|
||||
.br
|
||||
The default is
|
||||
.B on.
|
||||
.TP
|
||||
.BI "Option \*qZaphodHeads\*q \*q" string \*q
|
||||
Specify the RandR output(s) to use with zaphod mode for a particular driver
|
||||
instance.
|
||||
If you use this option you must use this option for all instances of the driver.
|
||||
.br
|
||||
For example:
|
||||
.B
|
||||
Option \*qZaphodHeads\*q \*qLVDS,VGA-0\*q
|
||||
will assign xrandr outputs LVDS and VGA-0 to this instance of the driver.
|
||||
.TP
|
||||
.BI "Option \*qColorTiling\*q \*q" "boolean" \*q
|
||||
The framebuffer can be addressed either in linear or tiled mode.
|
||||
Tiled mode can provide significant performance benefits with 3D applications.
|
||||
Tiling will be disabled if the drm module is too old or
|
||||
if the current display configuration does not support it.
|
||||
On R600+ this enables 1D tiling mode.
|
||||
.br
|
||||
The default value is
|
||||
.B on
|
||||
for R/RV3XX, R/RV4XX, R/RV5XX, RS6XX, RS740, R/RV6XX, R/RV7XX, RS780, RS880,
|
||||
EVERGREEN, CAYMAN, ARUBA, Southern Islands, and Sea Islands and
|
||||
.B off
|
||||
for R/RV/RS1XX, R/RV/RS2XX, RS3XX, and RS690/RS780/RS880
|
||||
when fast fb feature is enabled.
|
||||
.TP
|
||||
.BI "Option \*qColorTiling2D\*q \*q" "boolean" \*q
|
||||
The framebuffer can be addressed either in linear, 1D, or 2D tiled modes.
|
||||
2D tiled mode can provide significant performance benefits over
|
||||
1D tiling with 3D applications.
|
||||
Tiling will be disabled if the drm module is too old or
|
||||
if the current display configuration does not support it.
|
||||
KMS ColorTiling2D is only supported on R600 and newer chips and requires
|
||||
Mesa 9.0 or newer for R6xx-ARUBA, Mesa 9.2 or newer for Southern Islands,
|
||||
and Mesa 10.1 or newer for Sea Islands.
|
||||
.br
|
||||
The default value is
|
||||
.B on
|
||||
for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, ARUBA, Southern Islands,
|
||||
and Sea Islands.
|
||||
.TP
|
||||
.BI "Option \*qDRI\*q \*q" integer \*q
|
||||
Define the maximum level of DRI to enable.
|
||||
Valid values are 2 for DRI2 or 3 for DRI3.
|
||||
The default is
|
||||
.B 3 for DRI3
|
||||
if the Xorg version is >= 1.18.3 and glamor is enabled, otherwise
|
||||
.B 2 for DRI2.
|
||||
Note:
|
||||
DRI3 may not work correctly in all cases with EXA, enable at your own risk.
|
||||
.TP
|
||||
.BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
|
||||
Enable DRI2 page flipping.
|
||||
The default is
|
||||
.B on.
|
||||
Pageflipping is supported on all radeon hardware.
|
||||
.TP
|
||||
.BI "Option \*qTearFree\*q \*q" boolean \*q
|
||||
Set the default value of the per-output 'TearFree' property, which controls
|
||||
tearing prevention using the hardware page flipping mechanism.
|
||||
TearFree is on for any CRTC associated with one or more outputs with TearFree on.
|
||||
Two separate scanout buffers need to be allocated for each CRTC with TearFree on.
|
||||
If this option is set, the default value of the property is 'on' or 'off'
|
||||
accordingly.
|
||||
If this option isn't set, the default value of the property is
|
||||
.BR auto ,
|
||||
which means that TearFree is on for rotated outputs, outputs with RandR
|
||||
transforms applied and for RandR 1.4 secondary outputs, otherwise off.
|
||||
.TP
|
||||
.BI "Option \*qAccelMethod\*q \*q" "string" \*q
|
||||
Chooses between available acceleration architectures.
|
||||
Valid values are
|
||||
.B EXA
|
||||
(for pre-TAHITI GPUs) and
|
||||
.B glamor
|
||||
(for R300 or higher).
|
||||
The default is
|
||||
.B glamor
|
||||
with R600 or newer (with Xorg >= 1.18.3, otherwise with TAHITI or newer),
|
||||
otherwise
|
||||
.B EXA.
|
||||
.sp
|
||||
.PP
|
||||
The following driver
|
||||
.B Options
|
||||
are supported for
|
||||
.BR glamor :
|
||||
.TP
|
||||
.BI "Option \*qShadowPrimary\*q \*q" boolean \*q
|
||||
This option enables a so-called "shadow primary" buffer for fast CPU access to
|
||||
pixel data, and separate scanout buffers for each display controller (CRTC).
|
||||
This may improve performance for some 2D workloads, potentially at the expense
|
||||
of other (e.g. 3D, video) workloads.
|
||||
Note in particular that enabling this option currently disables page flipping.
|
||||
The default is
|
||||
.B off.
|
||||
.PP
|
||||
The following driver
|
||||
.B Options
|
||||
are supported for
|
||||
.BR EXA :
|
||||
.TP
|
||||
.BI "Option \*qEXAVSync\*q \*q" boolean \*q
|
||||
This option attempts to avoid tearing by stalling the engine until the display
|
||||
controller has passed the destination region.
|
||||
It reduces tearing at the cost of performance and
|
||||
has been known to cause instability on some chips.
|
||||
The default is
|
||||
.B off.
|
||||
.TP
|
||||
.BI "Option \*qEXAPixmaps\*q \*q" boolean \*q
|
||||
Under KMS, to avoid thrashing pixmaps in/out of VRAM on low memory cards,
|
||||
we use a heuristic based on VRAM amount to determine whether to allow EXA
|
||||
to use VRAM for non-essential pixmaps.
|
||||
This option allows us to override the heuristic.
|
||||
The default is
|
||||
.B on
|
||||
with > 32MB VRAM,
|
||||
.B off
|
||||
with < 32MB or when fast fb feature is enabled for RS690/RS780/RS880.
|
||||
.TP
|
||||
.BI "Option \*qSwapbuffersWait\*q \*q" boolean \*q
|
||||
This option controls the behavior of glXSwapBuffers and glXCopySubBufferMESA
|
||||
calls by GL applications.
|
||||
If enabled, the calls will avoid tearing by making sure the display scanline
|
||||
is outside of the area to be copied before the copy occurs.
|
||||
If disabled, no scanline synchronization is performed,
|
||||
meaning tearing will likely occur.
|
||||
Note that when enabled, this option can adversely affect
|
||||
the framerate of applications that render frames at less than refresh rate.
|
||||
.IP
|
||||
The default value is
|
||||
.B on.
|
||||
.SH TEXTURED VIDEO ATTRIBUTES
|
||||
The driver supports the following X11 Xv attributes for Textured Video.
|
||||
You can use the "xvattr" tool to query/set those attributes at runtime.
|
||||
.TP
|
||||
.B "XV_VSYNC"
|
||||
XV_VSYNC is used to control whether textured adapter synchronizes
|
||||
the screen update to the monitor vertical refresh to eliminate tearing.
|
||||
It has two values: 'off'(0) and 'on'(1). The default is
|
||||
.B 'on'(1).
|
||||
.TP
|
||||
.B "XV_CRTC"
|
||||
XV_CRTC is used to control which display controller (crtc) the textured
|
||||
adapter synchronizes the screen update with when XV_VSYNC is enabled.
|
||||
The default, 'auto'(-1), will sync to the display controller that more
|
||||
of the video is on; when this is ambiguous, the display controller associated
|
||||
with the RandR primary output is preferred.
|
||||
This attribute is useful for things like clone mode where the user
|
||||
can best decide which display should be synced.
|
||||
The default is
|
||||
.B 'auto'(-1).
|
||||
.TP
|
||||
.B "XV_BICUBIC"
|
||||
XV_BICUBIC is used to control whether textured adapter should apply
|
||||
a bicubic filter to smooth the output. It has three values: 'off'(0), 'on'(1)
|
||||
and 'auto'(2).
|
||||
\&'off' means never apply the filter, 'on' means always apply
|
||||
the filter and 'auto' means apply the filter only if the X and Y
|
||||
sizes are scaled to more than double to avoid blurred output.
|
||||
Bicubic filtering is not currently compatible with other Xv attributes like hue,
|
||||
contrast, and brightness, and must be disabled to use those attributes.
|
||||
The default is
|
||||
.B 'off'(0).
|
||||
.SH SEE ALSO
|
||||
.BR XLibre (__appmansuffix__),
|
||||
.BR xorg.conf (__filemansuffix__),
|
||||
.BR Xserver (__appmansuffix__),
|
||||
.BR X (__miscmansuffix__)
|
||||
.IP " 1." 4
|
||||
Wiki page:
|
||||
.RS 4
|
||||
https://www.x.org/wiki/radeon
|
||||
.RE
|
||||
.IP " 2." 4
|
||||
Overview about radeon development code:
|
||||
.RS 4
|
||||
https://github.com/X11Libre/xf86-video-ati
|
||||
.RE
|
||||
.IP " 3." 4
|
||||
Mailing list:
|
||||
.RS 4
|
||||
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
|
||||
.RE
|
||||
.IP " 4." 4
|
||||
IRC channel:
|
||||
.RS 4
|
||||
#radeon on irc.oftc.net
|
||||
.RE
|
||||
.IP " 5." 4
|
||||
Query the bugtracker for radeon bugs:
|
||||
.RS 4
|
||||
https://github.com/X11Libre/xf86-video-ati/issues
|
||||
.RE
|
||||
.SH AUTHORS
|
||||
.nf
|
||||
Authors include:
|
||||
Rickard E. (Rik) Faith \fIfaith@precisioninsight.com\fP
|
||||
Kevin E. Martin \fIkem@freedesktop.org\fP
|
||||
Alan Hourihane \fIalanh@fairlite.demon.co.uk\fP
|
||||
Marc Aurele La France \fItsi@xfree86.org\fP
|
||||
Benjamin Herrenschmidt \fIbenh@kernel.crashing.org\fP
|
||||
Michel D\(:anzer \fImichel@daenzer.net\fP
|
||||
Alex Deucher \fIalexdeucher@gmail.com\fP
|
||||
Bogdan D. \fIbogdand@users.sourceforge.net\fP
|
||||
Eric Anholt \fIeric@anholt.net\fP
|
||||
3
src/.gitignore
vendored
Normal file
3
src/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# Add & Override for this directory and it's subdirectories
|
||||
modes
|
||||
parser
|
||||
114
src/Makefile.am
Normal file
114
src/Makefile.am
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
# Copyright 2005 Adam Jackson.
|
||||
# Copyright 2005 Red Hat, Inc.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
# this is obnoxious:
|
||||
# -module lets us name the module exactly how we want
|
||||
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
|
||||
# _ladir passes a dummy rpath to libtool so the thing will actually link
|
||||
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
|
||||
|
||||
ati_drv_la_LIBADD = $(PCIACCESS_LIBS)
|
||||
radeon_drv_la_LIBADD = $(LIBDRM_RADEON_LIBS)
|
||||
|
||||
RADEON_KMS_SRCS=radeon_dri2.c radeon_dri3.c radeon_drm_queue.c radeon_kms.c \
|
||||
radeon_present.c radeon_sync.c radeon_vbo.c radeon_bo_helper.c \
|
||||
drmmode_display.c
|
||||
|
||||
RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c \
|
||||
evergreen_exa.c evergreen_accel.c evergreen_shader.c evergreen_textured_videofuncs.c cayman_accel.c cayman_shader.c
|
||||
|
||||
AM_CFLAGS = \
|
||||
@LIBDRM_RADEON_CFLAGS@ \
|
||||
@XORG_CFLAGS@ \
|
||||
@LIBUDEV_CFLAGS@
|
||||
|
||||
if LIBUDEV
|
||||
radeon_drv_la_LIBADD += $(LIBUDEV_LIBS)
|
||||
endif
|
||||
|
||||
ati_drv_la_LTLIBRARIES = ati_drv.la
|
||||
ati_drv_la_LDFLAGS = -module -avoid-version
|
||||
ati_drv_ladir = @moduledir@/drivers
|
||||
ati_drv_la_SOURCES = \
|
||||
ati.c atimodule.c
|
||||
|
||||
radeon_drv_la_LTLIBRARIES = radeon_drv.la
|
||||
radeon_drv_la_LDFLAGS = -module -avoid-version
|
||||
radeon_drv_ladir = @moduledir@/drivers
|
||||
radeon_drv_la_SOURCES = \
|
||||
radeon_accel.c radeon_video.c \
|
||||
radeon_misc.c radeon_probe.c \
|
||||
radeon_textured_video.c radeon_xvmc.c \
|
||||
$(RADEON_EXA_SOURCES) \
|
||||
$(RADEON_KMS_SRCS)
|
||||
|
||||
if GLAMOR
|
||||
AM_CFLAGS += @LIBGLAMOR_CFLAGS@ @GBM_CFLAGS@
|
||||
radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ @GBM_LIBS@
|
||||
radeon_drv_la_SOURCES += \
|
||||
radeon_glamor_wrappers.c \
|
||||
radeon_glamor.c
|
||||
endif
|
||||
|
||||
EXTRA_DIST = \
|
||||
radeon_textured_videofuncs.c \
|
||||
r600_reg.h \
|
||||
r600_reg_auto_r6xx.h \
|
||||
r600_reg_r6xx.h \
|
||||
r600_reg_r7xx.h \
|
||||
r600_shader.h \
|
||||
r600_state.h \
|
||||
evergreen_reg.h \
|
||||
evergreen_reg_auto.h \
|
||||
evergreen_shader.h \
|
||||
evergreen_state.h \
|
||||
cayman_reg.h \
|
||||
cayman_reg_auto.h \
|
||||
cayman_shader.h \
|
||||
ati.h \
|
||||
ativersion.h \
|
||||
bicubic_table.h \
|
||||
bicubic_table.py \
|
||||
radeon_bo_helper.h \
|
||||
radeon_drm_queue.h \
|
||||
radeon_exa_render.c \
|
||||
radeon_exa_funcs.c \
|
||||
radeon_exa_shared.h \
|
||||
radeon_glamor.h \
|
||||
radeon.h \
|
||||
radeon_probe.h \
|
||||
radeon_reg.h \
|
||||
radeon_version.h \
|
||||
radeon_vbo.h \
|
||||
radeon_video.h \
|
||||
simple_list.h \
|
||||
atipciids.h \
|
||||
atipcirename.h \
|
||||
ati_pciids_gen.h \
|
||||
radeon_chipinfo_gen.h \
|
||||
radeon_chipset_gen.h \
|
||||
radeon_pci_chipset_gen.h \
|
||||
radeon_pci_device_match_gen.h \
|
||||
pcidb/ati_pciids.csv \
|
||||
pcidb/parse_pci_ids.pl \
|
||||
radeon_dri2.h \
|
||||
drmmode_display.h
|
||||
358
src/ati.c
Normal file
358
src/ati.c
Normal file
|
|
@ -0,0 +1,358 @@
|
|||
/*
|
||||
* Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*************************************************************************/
|
||||
|
||||
/*
|
||||
* Author: Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* This is the ATI driver for XFree86.
|
||||
*
|
||||
* John Donne once said "No man is an island", and I am most certainly not an
|
||||
* exception. Contributions, intentional or not, to this and previous versions
|
||||
* of this driver by the following are hereby acknowledged:
|
||||
*
|
||||
* Thomas Roell, Per Lindqvist, Doug Evans, Rik Faith, Arthur Tateishi,
|
||||
* Alain Hebert, Ton van Rosmalen, David Chambers, William Shubert,
|
||||
* ATI Technologies Incorporated, Robert Wolff, David Dawes, Mark Weaver,
|
||||
* Hans Nasten, Kevin Martin, Frederic Rienthaler, Marc Bolduc, Reuben Sumner,
|
||||
* Benjamin T. Yang, James Fast Kane, Randall Hopper, W. Marcus Miller,
|
||||
* Henrik Harmsen, Christian Lupien, Precision Insight Incorporated,
|
||||
* Mark Vojkovich, Huw D M Davies, Andrew C Aitchison, Ani Joshi,
|
||||
* Kostas Gewrgiou, Jakub Jelinek, David S. Miller, A E Lawrence,
|
||||
* Linus Torvalds, William Blew, Ignacio Garcia Etxebarria, Patrick Chase,
|
||||
* Vladimir Dergachev, Egbert Eich, Mike A. Harris
|
||||
*
|
||||
* ... and, many, many others from around the world.
|
||||
*
|
||||
* In addition, this work would not have been possible without the active
|
||||
* support, both moral and otherwise, of the staff and management of Computing
|
||||
* and Network Services at the University of Alberta, in Edmonton, Alberta,
|
||||
* Canada.
|
||||
*
|
||||
* The driver is intended to support all ATI adapters since their VGA Wonder
|
||||
* V3, including OEM counterparts.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <pciaccess.h>
|
||||
#include <xf86drm.h>
|
||||
#include "atipcirename.h"
|
||||
|
||||
#include "ati.h"
|
||||
#include "atipciids.h"
|
||||
#include "ativersion.h"
|
||||
|
||||
/* names duplicated from version headers */
|
||||
#define MACH64_DRIVER_NAME "mach64"
|
||||
#define R128_DRIVER_NAME "r128"
|
||||
#define RADEON_DRIVER_NAME "radeon"
|
||||
#define AMDGPU_DRIVER_NAME "amdgpu"
|
||||
|
||||
enum
|
||||
{
|
||||
ATI_CHIP_FAMILY_NONE = 0,
|
||||
ATI_CHIP_FAMILY_Mach64,
|
||||
ATI_CHIP_FAMILY_Rage128,
|
||||
ATI_CHIP_FAMILY_Radeon
|
||||
};
|
||||
|
||||
static int ATIChipID(const uint16_t);
|
||||
|
||||
/* domain defines (stolen from xserver) */
|
||||
#if (defined(__alpha__) || defined(__ia64__)) && defined (linux)
|
||||
# define PCI_DOM_MASK 0x01fful
|
||||
#else
|
||||
# define PCI_DOM_MASK 0x0ffu
|
||||
#endif
|
||||
|
||||
#define PCI_DOM_FROM_BUS(bus) (((bus) >> 8) & (PCI_DOM_MASK))
|
||||
#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu)
|
||||
|
||||
static struct pci_device*
|
||||
ati_device_get_from_busid(int bus, int dev, int func)
|
||||
{
|
||||
return pci_device_find_by_slot(PCI_DOM_FROM_BUS(bus),
|
||||
PCI_BUS_NO_DOMAIN(bus),
|
||||
dev,
|
||||
func);
|
||||
}
|
||||
|
||||
#ifndef XSERVER_PLATFORM_BUS
|
||||
static struct pci_device*
|
||||
ati_device_get_primary(void)
|
||||
{
|
||||
struct pci_device *device = NULL;
|
||||
struct pci_device_iterator *device_iter;
|
||||
|
||||
device_iter = pci_slot_match_iterator_create(NULL);
|
||||
|
||||
while ((device = pci_device_next(device_iter))) {
|
||||
if (xf86IsPrimaryPci(device))
|
||||
break;
|
||||
}
|
||||
|
||||
pci_iterator_destroy(device_iter);
|
||||
|
||||
return device;
|
||||
}
|
||||
#else
|
||||
static struct pci_device *
|
||||
ati_device_get_indexed(int index)
|
||||
{
|
||||
struct pci_device *device = NULL;
|
||||
struct pci_device_iterator *device_iter;
|
||||
int count = 0;
|
||||
|
||||
device_iter = pci_slot_match_iterator_create(NULL);
|
||||
|
||||
while ((device = pci_device_next(device_iter))) {
|
||||
if (device->vendor_id == PCI_VENDOR_ATI) {
|
||||
if (count == index)
|
||||
return device;
|
||||
count++;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
ati_gdev_subdriver(void *options)
|
||||
{
|
||||
int nATIGDev, nMach64GDev, nR128GDev, nRadeonGDev, nAmdgpuGDev;
|
||||
GDevPtr *ATIGDevs;
|
||||
Bool load_mach64 = FALSE, load_r128 = FALSE, load_radeon = FALSE, load_amdgpu = FALSE;
|
||||
int i;
|
||||
|
||||
/* let the subdrivers configure for themselves */
|
||||
if (xf86ServerIsOnlyDetecting())
|
||||
return;
|
||||
|
||||
/* get Device sections with Driver "ati" */
|
||||
nATIGDev = xf86MatchDevice(ATI_DRIVER_NAME, &ATIGDevs);
|
||||
nMach64GDev = xf86MatchDevice(MACH64_DRIVER_NAME, NULL);
|
||||
nR128GDev = xf86MatchDevice(R128_DRIVER_NAME, NULL);
|
||||
nRadeonGDev = xf86MatchDevice(RADEON_DRIVER_NAME, NULL);
|
||||
nAmdgpuGDev = xf86MatchDevice(AMDGPU_DRIVER_NAME, NULL);
|
||||
|
||||
for (i = 0; i < nATIGDev; i++) {
|
||||
GDevPtr ati_gdev = ATIGDevs[i];
|
||||
pciVideoPtr device = NULL;
|
||||
int chip_family;
|
||||
|
||||
/* get pci device for the Device section */
|
||||
if (ati_gdev->busID) {
|
||||
int bus, dev, func;
|
||||
|
||||
if (!xf86ParsePciBusString(ati_gdev->busID, &bus, &dev, &func))
|
||||
continue;
|
||||
|
||||
device = ati_device_get_from_busid(bus, dev, func);
|
||||
}
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
else
|
||||
device = ati_device_get_indexed(i);
|
||||
#else
|
||||
else {
|
||||
device = ati_device_get_primary();
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!device)
|
||||
continue;
|
||||
|
||||
/* check for non-ati devices and prehistoric mach32 */
|
||||
if ((PCI_DEV_VENDOR_ID(device) != PCI_VENDOR_ATI) ||
|
||||
(PCI_DEV_DEVICE_ID(device) == PCI_CHIP_MACH32))
|
||||
continue;
|
||||
|
||||
/* replace Driver line in the Device section */
|
||||
chip_family = ATIChipID(PCI_DEV_DEVICE_ID(device));
|
||||
|
||||
if (chip_family == ATI_CHIP_FAMILY_Mach64) {
|
||||
ati_gdev->driver = MACH64_DRIVER_NAME;
|
||||
load_mach64 = TRUE;
|
||||
}
|
||||
|
||||
if (chip_family == ATI_CHIP_FAMILY_Rage128) {
|
||||
ati_gdev->driver = R128_DRIVER_NAME;
|
||||
load_r128 = TRUE;
|
||||
}
|
||||
|
||||
if (chip_family == ATI_CHIP_FAMILY_Radeon) {
|
||||
char *busid = NULL;
|
||||
|
||||
if (asprintf(&busid, "pci:%04x:%02x:%02x.%d",
|
||||
device->domain, device->bus, device->dev,
|
||||
device->func) == -1) {
|
||||
ErrorF("ati: malloc() failed\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
if (busid) {
|
||||
int fd = drmOpen(NULL, busid);
|
||||
|
||||
if (fd >= 0) {
|
||||
drmVersionPtr version = drmGetVersion(fd);
|
||||
|
||||
if (version->version_major == 3) {
|
||||
ati_gdev->driver = AMDGPU_DRIVER_NAME;
|
||||
load_amdgpu = TRUE;
|
||||
}
|
||||
|
||||
free(version);
|
||||
drmClose(fd);
|
||||
}
|
||||
|
||||
free(busid);
|
||||
}
|
||||
|
||||
if (strcmp(ati_gdev->driver, AMDGPU_DRIVER_NAME) != 0) {
|
||||
ati_gdev->driver = RADEON_DRIVER_NAME;
|
||||
load_radeon = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
free(ATIGDevs);
|
||||
|
||||
/* load subdrivers as primary modules and only if they do not get loaded
|
||||
* from other device sections
|
||||
*/
|
||||
|
||||
if (load_mach64 && (nMach64GDev == 0))
|
||||
xf86LoadOneModule(MACH64_DRIVER_NAME, options);
|
||||
|
||||
if (load_r128 && (nR128GDev == 0))
|
||||
xf86LoadOneModule(R128_DRIVER_NAME, options);
|
||||
|
||||
if (load_radeon && (nRadeonGDev == 0))
|
||||
xf86LoadOneModule(RADEON_DRIVER_NAME, options);
|
||||
|
||||
if (load_amdgpu && (nAmdgpuGDev == 0))
|
||||
xf86LoadOneModule(AMDGPU_DRIVER_NAME, options);
|
||||
}
|
||||
|
||||
/*
|
||||
* ATIChipID --
|
||||
*
|
||||
* This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID.
|
||||
*/
|
||||
static int
|
||||
ATIChipID(const uint16_t ChipID)
|
||||
{
|
||||
switch (ChipID)
|
||||
{
|
||||
case PCI_CHIP_MACH64GX:
|
||||
case PCI_CHIP_MACH64CX:
|
||||
case PCI_CHIP_MACH64CT:
|
||||
case PCI_CHIP_MACH64ET:
|
||||
case PCI_CHIP_MACH64VT:
|
||||
case PCI_CHIP_MACH64GT:
|
||||
case PCI_CHIP_MACH64VU:
|
||||
case PCI_CHIP_MACH64GU:
|
||||
case PCI_CHIP_MACH64LG:
|
||||
case PCI_CHIP_MACH64VV:
|
||||
case PCI_CHIP_MACH64GV:
|
||||
case PCI_CHIP_MACH64GW:
|
||||
case PCI_CHIP_MACH64GY:
|
||||
case PCI_CHIP_MACH64GZ:
|
||||
case PCI_CHIP_MACH64GB:
|
||||
case PCI_CHIP_MACH64GD:
|
||||
case PCI_CHIP_MACH64GI:
|
||||
case PCI_CHIP_MACH64GP:
|
||||
case PCI_CHIP_MACH64GQ:
|
||||
case PCI_CHIP_MACH64LB:
|
||||
case PCI_CHIP_MACH64LD:
|
||||
case PCI_CHIP_MACH64LI:
|
||||
case PCI_CHIP_MACH64LP:
|
||||
case PCI_CHIP_MACH64LQ:
|
||||
case PCI_CHIP_MACH64GL:
|
||||
case PCI_CHIP_MACH64GM:
|
||||
case PCI_CHIP_MACH64GN:
|
||||
case PCI_CHIP_MACH64GO:
|
||||
case PCI_CHIP_MACH64GR:
|
||||
case PCI_CHIP_MACH64GS:
|
||||
case PCI_CHIP_MACH64LM:
|
||||
case PCI_CHIP_MACH64LN:
|
||||
case PCI_CHIP_MACH64LR:
|
||||
case PCI_CHIP_MACH64LS:
|
||||
return ATI_CHIP_FAMILY_Mach64;
|
||||
|
||||
case PCI_CHIP_RAGE128RE:
|
||||
case PCI_CHIP_RAGE128RF:
|
||||
case PCI_CHIP_RAGE128RG:
|
||||
case PCI_CHIP_RAGE128SK:
|
||||
case PCI_CHIP_RAGE128SL:
|
||||
case PCI_CHIP_RAGE128SM:
|
||||
case PCI_CHIP_RAGE128SN:
|
||||
case PCI_CHIP_RAGE128RK:
|
||||
case PCI_CHIP_RAGE128RL:
|
||||
case PCI_CHIP_RAGE128SE:
|
||||
case PCI_CHIP_RAGE128SF:
|
||||
case PCI_CHIP_RAGE128SG:
|
||||
case PCI_CHIP_RAGE128SH:
|
||||
case PCI_CHIP_RAGE128PA:
|
||||
case PCI_CHIP_RAGE128PB:
|
||||
case PCI_CHIP_RAGE128PC:
|
||||
case PCI_CHIP_RAGE128PD:
|
||||
case PCI_CHIP_RAGE128PE:
|
||||
case PCI_CHIP_RAGE128PF:
|
||||
case PCI_CHIP_RAGE128PG:
|
||||
case PCI_CHIP_RAGE128PH:
|
||||
case PCI_CHIP_RAGE128PI:
|
||||
case PCI_CHIP_RAGE128PJ:
|
||||
case PCI_CHIP_RAGE128PK:
|
||||
case PCI_CHIP_RAGE128PL:
|
||||
case PCI_CHIP_RAGE128PM:
|
||||
case PCI_CHIP_RAGE128PN:
|
||||
case PCI_CHIP_RAGE128PO:
|
||||
case PCI_CHIP_RAGE128PP:
|
||||
case PCI_CHIP_RAGE128PQ:
|
||||
case PCI_CHIP_RAGE128PR:
|
||||
case PCI_CHIP_RAGE128PS:
|
||||
case PCI_CHIP_RAGE128PT:
|
||||
case PCI_CHIP_RAGE128PU:
|
||||
case PCI_CHIP_RAGE128PV:
|
||||
case PCI_CHIP_RAGE128PW:
|
||||
case PCI_CHIP_RAGE128PX:
|
||||
case PCI_CHIP_RAGE128TF:
|
||||
case PCI_CHIP_RAGE128TL:
|
||||
case PCI_CHIP_RAGE128TR:
|
||||
case PCI_CHIP_RAGE128TS:
|
||||
case PCI_CHIP_RAGE128TT:
|
||||
case PCI_CHIP_RAGE128TU:
|
||||
case PCI_CHIP_RAGE128LE:
|
||||
case PCI_CHIP_RAGE128LF:
|
||||
#if 0
|
||||
case PCI_CHIP_RAGE128LK:
|
||||
case PCI_CHIP_RAGE128LL:
|
||||
#endif
|
||||
case PCI_CHIP_RAGE128MF:
|
||||
case PCI_CHIP_RAGE128ML:
|
||||
return ATI_CHIP_FAMILY_Rage128;
|
||||
|
||||
default:
|
||||
return ATI_CHIP_FAMILY_Radeon;
|
||||
}
|
||||
}
|
||||
36
src/ati.h
Normal file
36
src/ati.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef ___ATI_H___
|
||||
#define ___ATI_H___ 1
|
||||
|
||||
#include <unistd.h>
|
||||
#include <stdint.h>
|
||||
#include "xf86Pci.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
#include "xf86_OSproc.h"
|
||||
|
||||
extern void ati_gdev_subdriver(void *options);
|
||||
|
||||
#endif /* ___ATI_H___ */
|
||||
782
src/ati_pciids_gen.h
Normal file
782
src/ati_pciids_gen.h
Normal file
|
|
@ -0,0 +1,782 @@
|
|||
#define PCI_CHIP_RV380_3150 0x3150
|
||||
#define PCI_CHIP_RV380_3151 0x3151
|
||||
#define PCI_CHIP_RV380_3152 0x3152
|
||||
#define PCI_CHIP_RV380_3154 0x3154
|
||||
#define PCI_CHIP_RV380_3155 0x3155
|
||||
#define PCI_CHIP_RV380_3E50 0x3E50
|
||||
#define PCI_CHIP_RV380_3E54 0x3E54
|
||||
#define PCI_CHIP_RS100_4136 0x4136
|
||||
#define PCI_CHIP_RS200_4137 0x4137
|
||||
#define PCI_CHIP_R300_AD 0x4144
|
||||
#define PCI_CHIP_R300_AE 0x4145
|
||||
#define PCI_CHIP_R300_AF 0x4146
|
||||
#define PCI_CHIP_R300_AG 0x4147
|
||||
#define PCI_CHIP_R350_AH 0x4148
|
||||
#define PCI_CHIP_R350_AI 0x4149
|
||||
#define PCI_CHIP_R350_AJ 0x414A
|
||||
#define PCI_CHIP_R350_AK 0x414B
|
||||
#define PCI_CHIP_RV350_AP 0x4150
|
||||
#define PCI_CHIP_RV350_AQ 0x4151
|
||||
#define PCI_CHIP_RV360_AR 0x4152
|
||||
#define PCI_CHIP_RV350_AS 0x4153
|
||||
#define PCI_CHIP_RV350_AT 0x4154
|
||||
#define PCI_CHIP_RV350_4155 0x4155
|
||||
#define PCI_CHIP_RV350_AV 0x4156
|
||||
#define PCI_CHIP_MACH32 0x4158
|
||||
#define PCI_CHIP_RS250_4237 0x4237
|
||||
#define PCI_CHIP_R200_BB 0x4242
|
||||
#define PCI_CHIP_RS100_4336 0x4336
|
||||
#define PCI_CHIP_RS200_4337 0x4337
|
||||
#define PCI_CHIP_MACH64CT 0x4354
|
||||
#define PCI_CHIP_MACH64CX 0x4358
|
||||
#define PCI_CHIP_RS250_4437 0x4437
|
||||
#define PCI_CHIP_MACH64ET 0x4554
|
||||
#define PCI_CHIP_MACH64GB 0x4742
|
||||
#define PCI_CHIP_MACH64GD 0x4744
|
||||
#define PCI_CHIP_MACH64GI 0x4749
|
||||
#define PCI_CHIP_MACH64GL 0x474C
|
||||
#define PCI_CHIP_MACH64GM 0x474D
|
||||
#define PCI_CHIP_MACH64GN 0x474E
|
||||
#define PCI_CHIP_MACH64GO 0x474F
|
||||
#define PCI_CHIP_MACH64GP 0x4750
|
||||
#define PCI_CHIP_MACH64GQ 0x4751
|
||||
#define PCI_CHIP_MACH64GR 0x4752
|
||||
#define PCI_CHIP_MACH64GS 0x4753
|
||||
#define PCI_CHIP_MACH64GT 0x4754
|
||||
#define PCI_CHIP_MACH64GU 0x4755
|
||||
#define PCI_CHIP_MACH64GV 0x4756
|
||||
#define PCI_CHIP_MACH64GW 0x4757
|
||||
#define PCI_CHIP_MACH64GX 0x4758
|
||||
#define PCI_CHIP_MACH64GY 0x4759
|
||||
#define PCI_CHIP_MACH64GZ 0x475A
|
||||
#define PCI_CHIP_RV250_If 0x4966
|
||||
#define PCI_CHIP_RV250_Ig 0x4967
|
||||
#define PCI_CHIP_R420_JH 0x4A48
|
||||
#define PCI_CHIP_R420_JI 0x4A49
|
||||
#define PCI_CHIP_R420_JJ 0x4A4A
|
||||
#define PCI_CHIP_R420_JK 0x4A4B
|
||||
#define PCI_CHIP_R420_JL 0x4A4C
|
||||
#define PCI_CHIP_R420_JM 0x4A4D
|
||||
#define PCI_CHIP_R420_JN 0x4A4E
|
||||
#define PCI_CHIP_R420_4A4F 0x4A4F
|
||||
#define PCI_CHIP_R420_JP 0x4A50
|
||||
#define PCI_CHIP_R420_JT 0x4A54
|
||||
#define PCI_CHIP_R481_4B48 0x4B48
|
||||
#define PCI_CHIP_R481_4B49 0x4B49
|
||||
#define PCI_CHIP_R481_4B4A 0x4B4A
|
||||
#define PCI_CHIP_R481_4B4B 0x4B4B
|
||||
#define PCI_CHIP_R481_4B4C 0x4B4C
|
||||
#define PCI_CHIP_MACH64LB 0x4C42
|
||||
#define PCI_CHIP_MACH64LD 0x4C44
|
||||
#define PCI_CHIP_RAGE128LE 0x4C45
|
||||
#define PCI_CHIP_RAGE128LF 0x4C46
|
||||
#define PCI_CHIP_MACH64LG 0x4C47
|
||||
#define PCI_CHIP_MACH64LI 0x4C49
|
||||
#define PCI_CHIP_MACH64LM 0x4C4D
|
||||
#define PCI_CHIP_MACH64LN 0x4C4E
|
||||
#define PCI_CHIP_MACH64LP 0x4C50
|
||||
#define PCI_CHIP_MACH64LQ 0x4C51
|
||||
#define PCI_CHIP_MACH64LR 0x4C52
|
||||
#define PCI_CHIP_MACH64LS 0x4C53
|
||||
#define PCI_CHIP_RADEON_LW 0x4C57
|
||||
#define PCI_CHIP_RADEON_LX 0x4C58
|
||||
#define PCI_CHIP_RADEON_LY 0x4C59
|
||||
#define PCI_CHIP_RADEON_LZ 0x4C5A
|
||||
#define PCI_CHIP_RV250_Ld 0x4C64
|
||||
#define PCI_CHIP_RV250_Lf 0x4C66
|
||||
#define PCI_CHIP_RV250_Lg 0x4C67
|
||||
#define PCI_CHIP_RV280_4C6E 0x4C6E
|
||||
#define PCI_CHIP_RAGE128MF 0x4D46
|
||||
#define PCI_CHIP_RAGE128ML 0x4D4C
|
||||
#define PCI_CHIP_R300_ND 0x4E44
|
||||
#define PCI_CHIP_R300_NE 0x4E45
|
||||
#define PCI_CHIP_R300_NF 0x4E46
|
||||
#define PCI_CHIP_R300_NG 0x4E47
|
||||
#define PCI_CHIP_R350_NH 0x4E48
|
||||
#define PCI_CHIP_R350_NI 0x4E49
|
||||
#define PCI_CHIP_R360_NJ 0x4E4A
|
||||
#define PCI_CHIP_R350_NK 0x4E4B
|
||||
#define PCI_CHIP_RV350_NP 0x4E50
|
||||
#define PCI_CHIP_RV350_NQ 0x4E51
|
||||
#define PCI_CHIP_RV350_NR 0x4E52
|
||||
#define PCI_CHIP_RV350_NS 0x4E53
|
||||
#define PCI_CHIP_RV350_NT 0x4E54
|
||||
#define PCI_CHIP_RV350_NV 0x4E56
|
||||
#define PCI_CHIP_RAGE128PA 0x5041
|
||||
#define PCI_CHIP_RAGE128PB 0x5042
|
||||
#define PCI_CHIP_RAGE128PC 0x5043
|
||||
#define PCI_CHIP_RAGE128PD 0x5044
|
||||
#define PCI_CHIP_RAGE128PE 0x5045
|
||||
#define PCI_CHIP_RAGE128PF 0x5046
|
||||
#define PCI_CHIP_RAGE128PG 0x5047
|
||||
#define PCI_CHIP_RAGE128PH 0x5048
|
||||
#define PCI_CHIP_RAGE128PI 0x5049
|
||||
#define PCI_CHIP_RAGE128PJ 0x504A
|
||||
#define PCI_CHIP_RAGE128PK 0x504B
|
||||
#define PCI_CHIP_RAGE128PL 0x504C
|
||||
#define PCI_CHIP_RAGE128PM 0x504D
|
||||
#define PCI_CHIP_RAGE128PN 0x504E
|
||||
#define PCI_CHIP_RAGE128PO 0x504F
|
||||
#define PCI_CHIP_RAGE128PP 0x5050
|
||||
#define PCI_CHIP_RAGE128PQ 0x5051
|
||||
#define PCI_CHIP_RAGE128PR 0x5052
|
||||
#define PCI_CHIP_RAGE128PS 0x5053
|
||||
#define PCI_CHIP_RAGE128PT 0x5054
|
||||
#define PCI_CHIP_RAGE128PU 0x5055
|
||||
#define PCI_CHIP_RAGE128PV 0x5056
|
||||
#define PCI_CHIP_RAGE128PW 0x5057
|
||||
#define PCI_CHIP_RAGE128PX 0x5058
|
||||
#define PCI_CHIP_RADEON_QD 0x5144
|
||||
#define PCI_CHIP_RADEON_QE 0x5145
|
||||
#define PCI_CHIP_RADEON_QF 0x5146
|
||||
#define PCI_CHIP_RADEON_QG 0x5147
|
||||
#define PCI_CHIP_R200_QH 0x5148
|
||||
#define PCI_CHIP_R200_QL 0x514C
|
||||
#define PCI_CHIP_R200_QM 0x514D
|
||||
#define PCI_CHIP_RV200_QW 0x5157
|
||||
#define PCI_CHIP_RV200_QX 0x5158
|
||||
#define PCI_CHIP_RV100_QY 0x5159
|
||||
#define PCI_CHIP_RV100_QZ 0x515A
|
||||
#define PCI_CHIP_RN50_515E 0x515E
|
||||
#define PCI_CHIP_RAGE128RE 0x5245
|
||||
#define PCI_CHIP_RAGE128RF 0x5246
|
||||
#define PCI_CHIP_RAGE128RG 0x5247
|
||||
#define PCI_CHIP_RAGE128RK 0x524B
|
||||
#define PCI_CHIP_RAGE128RL 0x524C
|
||||
#define PCI_CHIP_RAGE128SE 0x5345
|
||||
#define PCI_CHIP_RAGE128SF 0x5346
|
||||
#define PCI_CHIP_RAGE128SG 0x5347
|
||||
#define PCI_CHIP_RAGE128SH 0x5348
|
||||
#define PCI_CHIP_RAGE128SK 0x534B
|
||||
#define PCI_CHIP_RAGE128SL 0x534C
|
||||
#define PCI_CHIP_RAGE128SM 0x534D
|
||||
#define PCI_CHIP_RAGE128SN 0x534E
|
||||
#define PCI_CHIP_RAGE128TF 0x5446
|
||||
#define PCI_CHIP_RAGE128TL 0x544C
|
||||
#define PCI_CHIP_RAGE128TR 0x5452
|
||||
#define PCI_CHIP_RAGE128TS 0x5453
|
||||
#define PCI_CHIP_RAGE128TT 0x5454
|
||||
#define PCI_CHIP_RAGE128TU 0x5455
|
||||
#define PCI_CHIP_RV370_5460 0x5460
|
||||
#define PCI_CHIP_RV370_5462 0x5462
|
||||
#define PCI_CHIP_RV370_5464 0x5464
|
||||
#define PCI_CHIP_R423_UH 0x5548
|
||||
#define PCI_CHIP_R423_UI 0x5549
|
||||
#define PCI_CHIP_R423_UJ 0x554A
|
||||
#define PCI_CHIP_R423_UK 0x554B
|
||||
#define PCI_CHIP_R430_554C 0x554C
|
||||
#define PCI_CHIP_R430_554D 0x554D
|
||||
#define PCI_CHIP_R430_554E 0x554E
|
||||
#define PCI_CHIP_R430_554F 0x554F
|
||||
#define PCI_CHIP_R423_5550 0x5550
|
||||
#define PCI_CHIP_R423_UQ 0x5551
|
||||
#define PCI_CHIP_R423_UR 0x5552
|
||||
#define PCI_CHIP_R423_UT 0x5554
|
||||
#define PCI_CHIP_RV410_564A 0x564A
|
||||
#define PCI_CHIP_RV410_564B 0x564B
|
||||
#define PCI_CHIP_RV410_564F 0x564F
|
||||
#define PCI_CHIP_RV410_5652 0x5652
|
||||
#define PCI_CHIP_RV410_5653 0x5653
|
||||
#define PCI_CHIP_RV410_5657 0x5657
|
||||
#define PCI_CHIP_MACH64VT 0x5654
|
||||
#define PCI_CHIP_MACH64VU 0x5655
|
||||
#define PCI_CHIP_MACH64VV 0x5656
|
||||
#define PCI_CHIP_RS300_5834 0x5834
|
||||
#define PCI_CHIP_RS300_5835 0x5835
|
||||
#define PCI_CHIP_RS480_5954 0x5954
|
||||
#define PCI_CHIP_RS480_5955 0x5955
|
||||
#define PCI_CHIP_RV280_5960 0x5960
|
||||
#define PCI_CHIP_RV280_5961 0x5961
|
||||
#define PCI_CHIP_RV280_5962 0x5962
|
||||
#define PCI_CHIP_RV280_5964 0x5964
|
||||
#define PCI_CHIP_RV280_5965 0x5965
|
||||
#define PCI_CHIP_RN50_5969 0x5969
|
||||
#define PCI_CHIP_RS482_5974 0x5974
|
||||
#define PCI_CHIP_RS485_5975 0x5975
|
||||
#define PCI_CHIP_RS400_5A41 0x5A41
|
||||
#define PCI_CHIP_RS400_5A42 0x5A42
|
||||
#define PCI_CHIP_RC410_5A61 0x5A61
|
||||
#define PCI_CHIP_RC410_5A62 0x5A62
|
||||
#define PCI_CHIP_RV370_5B60 0x5B60
|
||||
#define PCI_CHIP_RV370_5B62 0x5B62
|
||||
#define PCI_CHIP_RV370_5B63 0x5B63
|
||||
#define PCI_CHIP_RV370_5B64 0x5B64
|
||||
#define PCI_CHIP_RV370_5B65 0x5B65
|
||||
#define PCI_CHIP_RV280_5C61 0x5C61
|
||||
#define PCI_CHIP_RV280_5C63 0x5C63
|
||||
#define PCI_CHIP_R430_5D48 0x5D48
|
||||
#define PCI_CHIP_R430_5D49 0x5D49
|
||||
#define PCI_CHIP_R430_5D4A 0x5D4A
|
||||
#define PCI_CHIP_R480_5D4C 0x5D4C
|
||||
#define PCI_CHIP_R480_5D4D 0x5D4D
|
||||
#define PCI_CHIP_R480_5D4E 0x5D4E
|
||||
#define PCI_CHIP_R480_5D4F 0x5D4F
|
||||
#define PCI_CHIP_R480_5D50 0x5D50
|
||||
#define PCI_CHIP_R480_5D52 0x5D52
|
||||
#define PCI_CHIP_R423_5D57 0x5D57
|
||||
#define PCI_CHIP_RV410_5E48 0x5E48
|
||||
#define PCI_CHIP_RV410_5E4A 0x5E4A
|
||||
#define PCI_CHIP_RV410_5E4B 0x5E4B
|
||||
#define PCI_CHIP_RV410_5E4C 0x5E4C
|
||||
#define PCI_CHIP_RV410_5E4D 0x5E4D
|
||||
#define PCI_CHIP_RV410_5E4F 0x5E4F
|
||||
#define PCI_CHIP_R520_7100 0x7100
|
||||
#define PCI_CHIP_R520_7101 0x7101
|
||||
#define PCI_CHIP_R520_7102 0x7102
|
||||
#define PCI_CHIP_R520_7103 0x7103
|
||||
#define PCI_CHIP_R520_7104 0x7104
|
||||
#define PCI_CHIP_R520_7105 0x7105
|
||||
#define PCI_CHIP_R520_7106 0x7106
|
||||
#define PCI_CHIP_R520_7108 0x7108
|
||||
#define PCI_CHIP_R520_7109 0x7109
|
||||
#define PCI_CHIP_R520_710A 0x710A
|
||||
#define PCI_CHIP_R520_710B 0x710B
|
||||
#define PCI_CHIP_R520_710C 0x710C
|
||||
#define PCI_CHIP_R520_710E 0x710E
|
||||
#define PCI_CHIP_R520_710F 0x710F
|
||||
#define PCI_CHIP_RV515_7140 0x7140
|
||||
#define PCI_CHIP_RV515_7141 0x7141
|
||||
#define PCI_CHIP_RV515_7142 0x7142
|
||||
#define PCI_CHIP_RV515_7143 0x7143
|
||||
#define PCI_CHIP_RV515_7144 0x7144
|
||||
#define PCI_CHIP_RV515_7145 0x7145
|
||||
#define PCI_CHIP_RV515_7146 0x7146
|
||||
#define PCI_CHIP_RV515_7147 0x7147
|
||||
#define PCI_CHIP_RV515_7149 0x7149
|
||||
#define PCI_CHIP_RV515_714A 0x714A
|
||||
#define PCI_CHIP_RV515_714B 0x714B
|
||||
#define PCI_CHIP_RV515_714C 0x714C
|
||||
#define PCI_CHIP_RV515_714D 0x714D
|
||||
#define PCI_CHIP_RV515_714E 0x714E
|
||||
#define PCI_CHIP_RV515_714F 0x714F
|
||||
#define PCI_CHIP_RV515_7151 0x7151
|
||||
#define PCI_CHIP_RV515_7152 0x7152
|
||||
#define PCI_CHIP_RV515_7153 0x7153
|
||||
#define PCI_CHIP_RV515_715E 0x715E
|
||||
#define PCI_CHIP_RV515_715F 0x715F
|
||||
#define PCI_CHIP_RV515_7180 0x7180
|
||||
#define PCI_CHIP_RV515_7181 0x7181
|
||||
#define PCI_CHIP_RV515_7183 0x7183
|
||||
#define PCI_CHIP_RV515_7186 0x7186
|
||||
#define PCI_CHIP_RV515_7187 0x7187
|
||||
#define PCI_CHIP_RV515_7188 0x7188
|
||||
#define PCI_CHIP_RV515_718A 0x718A
|
||||
#define PCI_CHIP_RV515_718B 0x718B
|
||||
#define PCI_CHIP_RV515_718C 0x718C
|
||||
#define PCI_CHIP_RV515_718D 0x718D
|
||||
#define PCI_CHIP_RV515_718F 0x718F
|
||||
#define PCI_CHIP_RV515_7193 0x7193
|
||||
#define PCI_CHIP_RV515_7196 0x7196
|
||||
#define PCI_CHIP_RV515_719B 0x719B
|
||||
#define PCI_CHIP_RV515_719F 0x719F
|
||||
#define PCI_CHIP_RV530_71C0 0x71C0
|
||||
#define PCI_CHIP_RV530_71C1 0x71C1
|
||||
#define PCI_CHIP_RV530_71C2 0x71C2
|
||||
#define PCI_CHIP_RV530_71C3 0x71C3
|
||||
#define PCI_CHIP_RV530_71C4 0x71C4
|
||||
#define PCI_CHIP_RV530_71C5 0x71C5
|
||||
#define PCI_CHIP_RV530_71C6 0x71C6
|
||||
#define PCI_CHIP_RV530_71C7 0x71C7
|
||||
#define PCI_CHIP_RV530_71CD 0x71CD
|
||||
#define PCI_CHIP_RV530_71CE 0x71CE
|
||||
#define PCI_CHIP_RV530_71D2 0x71D2
|
||||
#define PCI_CHIP_RV530_71D4 0x71D4
|
||||
#define PCI_CHIP_RV530_71D5 0x71D5
|
||||
#define PCI_CHIP_RV530_71D6 0x71D6
|
||||
#define PCI_CHIP_RV530_71DA 0x71DA
|
||||
#define PCI_CHIP_RV530_71DE 0x71DE
|
||||
#define PCI_CHIP_RV515_7200 0x7200
|
||||
#define PCI_CHIP_RV515_7210 0x7210
|
||||
#define PCI_CHIP_RV515_7211 0x7211
|
||||
#define PCI_CHIP_R580_7240 0x7240
|
||||
#define PCI_CHIP_R580_7243 0x7243
|
||||
#define PCI_CHIP_R580_7244 0x7244
|
||||
#define PCI_CHIP_R580_7245 0x7245
|
||||
#define PCI_CHIP_R580_7246 0x7246
|
||||
#define PCI_CHIP_R580_7247 0x7247
|
||||
#define PCI_CHIP_R580_7248 0x7248
|
||||
#define PCI_CHIP_R580_7249 0x7249
|
||||
#define PCI_CHIP_R580_724A 0x724A
|
||||
#define PCI_CHIP_R580_724B 0x724B
|
||||
#define PCI_CHIP_R580_724C 0x724C
|
||||
#define PCI_CHIP_R580_724D 0x724D
|
||||
#define PCI_CHIP_R580_724E 0x724E
|
||||
#define PCI_CHIP_R580_724F 0x724F
|
||||
#define PCI_CHIP_RV570_7280 0x7280
|
||||
#define PCI_CHIP_RV560_7281 0x7281
|
||||
#define PCI_CHIP_RV560_7283 0x7283
|
||||
#define PCI_CHIP_R580_7284 0x7284
|
||||
#define PCI_CHIP_RV560_7287 0x7287
|
||||
#define PCI_CHIP_RV570_7288 0x7288
|
||||
#define PCI_CHIP_RV570_7289 0x7289
|
||||
#define PCI_CHIP_RV570_728B 0x728B
|
||||
#define PCI_CHIP_RV570_728C 0x728C
|
||||
#define PCI_CHIP_RV560_7290 0x7290
|
||||
#define PCI_CHIP_RV560_7291 0x7291
|
||||
#define PCI_CHIP_RV560_7293 0x7293
|
||||
#define PCI_CHIP_RV560_7297 0x7297
|
||||
#define PCI_CHIP_RS350_7834 0x7834
|
||||
#define PCI_CHIP_RS350_7835 0x7835
|
||||
#define PCI_CHIP_RS690_791E 0x791E
|
||||
#define PCI_CHIP_RS690_791F 0x791F
|
||||
#define PCI_CHIP_RS600_793F 0x793F
|
||||
#define PCI_CHIP_RS600_7941 0x7941
|
||||
#define PCI_CHIP_RS600_7942 0x7942
|
||||
#define PCI_CHIP_RS740_796C 0x796C
|
||||
#define PCI_CHIP_RS740_796D 0x796D
|
||||
#define PCI_CHIP_RS740_796E 0x796E
|
||||
#define PCI_CHIP_RS740_796F 0x796F
|
||||
#define PCI_CHIP_R600_9400 0x9400
|
||||
#define PCI_CHIP_R600_9401 0x9401
|
||||
#define PCI_CHIP_R600_9402 0x9402
|
||||
#define PCI_CHIP_R600_9403 0x9403
|
||||
#define PCI_CHIP_R600_9405 0x9405
|
||||
#define PCI_CHIP_R600_940A 0x940A
|
||||
#define PCI_CHIP_R600_940B 0x940B
|
||||
#define PCI_CHIP_R600_940F 0x940F
|
||||
#define PCI_CHIP_RV770_9440 0x9440
|
||||
#define PCI_CHIP_RV770_9441 0x9441
|
||||
#define PCI_CHIP_RV770_9442 0x9442
|
||||
#define PCI_CHIP_RV770_9443 0x9443
|
||||
#define PCI_CHIP_RV770_9444 0x9444
|
||||
#define PCI_CHIP_RV770_9446 0x9446
|
||||
#define PCI_CHIP_RV770_944A 0x944A
|
||||
#define PCI_CHIP_RV770_944B 0x944B
|
||||
#define PCI_CHIP_RV770_944C 0x944C
|
||||
#define PCI_CHIP_RV770_944E 0x944E
|
||||
#define PCI_CHIP_RV770_9450 0x9450
|
||||
#define PCI_CHIP_RV770_9452 0x9452
|
||||
#define PCI_CHIP_RV770_9456 0x9456
|
||||
#define PCI_CHIP_RV770_945A 0x945A
|
||||
#define PCI_CHIP_RV770_945B 0x945B
|
||||
#define PCI_CHIP_RV770_945E 0x945E
|
||||
#define PCI_CHIP_RV790_9460 0x9460
|
||||
#define PCI_CHIP_RV790_9462 0x9462
|
||||
#define PCI_CHIP_RV770_946A 0x946A
|
||||
#define PCI_CHIP_RV770_946B 0x946B
|
||||
#define PCI_CHIP_RV770_947A 0x947A
|
||||
#define PCI_CHIP_RV770_947B 0x947B
|
||||
#define PCI_CHIP_RV730_9480 0x9480
|
||||
#define PCI_CHIP_RV730_9487 0x9487
|
||||
#define PCI_CHIP_RV730_9488 0x9488
|
||||
#define PCI_CHIP_RV730_9489 0x9489
|
||||
#define PCI_CHIP_RV730_948A 0x948A
|
||||
#define PCI_CHIP_RV730_948F 0x948F
|
||||
#define PCI_CHIP_RV730_9490 0x9490
|
||||
#define PCI_CHIP_RV730_9491 0x9491
|
||||
#define PCI_CHIP_RV730_9495 0x9495
|
||||
#define PCI_CHIP_RV730_9498 0x9498
|
||||
#define PCI_CHIP_RV730_949C 0x949C
|
||||
#define PCI_CHIP_RV730_949E 0x949E
|
||||
#define PCI_CHIP_RV730_949F 0x949F
|
||||
#define PCI_CHIP_RV740_94A0 0x94A0
|
||||
#define PCI_CHIP_RV740_94A1 0x94A1
|
||||
#define PCI_CHIP_RV740_94A3 0x94A3
|
||||
#define PCI_CHIP_RV740_94B1 0x94B1
|
||||
#define PCI_CHIP_RV740_94B3 0x94B3
|
||||
#define PCI_CHIP_RV740_94B4 0x94B4
|
||||
#define PCI_CHIP_RV740_94B5 0x94B5
|
||||
#define PCI_CHIP_RV740_94B9 0x94B9
|
||||
#define PCI_CHIP_RV610_94C0 0x94C0
|
||||
#define PCI_CHIP_RV610_94C1 0x94C1
|
||||
#define PCI_CHIP_RV610_94C3 0x94C3
|
||||
#define PCI_CHIP_RV610_94C4 0x94C4
|
||||
#define PCI_CHIP_RV610_94C5 0x94C5
|
||||
#define PCI_CHIP_RV610_94C6 0x94C6
|
||||
#define PCI_CHIP_RV610_94C7 0x94C7
|
||||
#define PCI_CHIP_RV610_94C8 0x94C8
|
||||
#define PCI_CHIP_RV610_94C9 0x94C9
|
||||
#define PCI_CHIP_RV610_94CB 0x94CB
|
||||
#define PCI_CHIP_RV610_94CC 0x94CC
|
||||
#define PCI_CHIP_RV610_94CD 0x94CD
|
||||
#define PCI_CHIP_RV670_9500 0x9500
|
||||
#define PCI_CHIP_RV670_9501 0x9501
|
||||
#define PCI_CHIP_RV670_9504 0x9504
|
||||
#define PCI_CHIP_RV670_9505 0x9505
|
||||
#define PCI_CHIP_RV670_9506 0x9506
|
||||
#define PCI_CHIP_RV670_9507 0x9507
|
||||
#define PCI_CHIP_RV670_9508 0x9508
|
||||
#define PCI_CHIP_RV670_9509 0x9509
|
||||
#define PCI_CHIP_RV670_950F 0x950F
|
||||
#define PCI_CHIP_RV670_9511 0x9511
|
||||
#define PCI_CHIP_RV670_9515 0x9515
|
||||
#define PCI_CHIP_RV670_9517 0x9517
|
||||
#define PCI_CHIP_RV670_9519 0x9519
|
||||
#define PCI_CHIP_RV710_9540 0x9540
|
||||
#define PCI_CHIP_RV710_9541 0x9541
|
||||
#define PCI_CHIP_RV710_9542 0x9542
|
||||
#define PCI_CHIP_RV710_954E 0x954E
|
||||
#define PCI_CHIP_RV710_954F 0x954F
|
||||
#define PCI_CHIP_RV710_9552 0x9552
|
||||
#define PCI_CHIP_RV710_9553 0x9553
|
||||
#define PCI_CHIP_RV710_9555 0x9555
|
||||
#define PCI_CHIP_RV710_9557 0x9557
|
||||
#define PCI_CHIP_RV710_955F 0x955F
|
||||
#define PCI_CHIP_RV630_9580 0x9580
|
||||
#define PCI_CHIP_RV630_9581 0x9581
|
||||
#define PCI_CHIP_RV630_9583 0x9583
|
||||
#define PCI_CHIP_RV630_9586 0x9586
|
||||
#define PCI_CHIP_RV630_9587 0x9587
|
||||
#define PCI_CHIP_RV630_9588 0x9588
|
||||
#define PCI_CHIP_RV630_9589 0x9589
|
||||
#define PCI_CHIP_RV630_958A 0x958A
|
||||
#define PCI_CHIP_RV630_958B 0x958B
|
||||
#define PCI_CHIP_RV630_958C 0x958C
|
||||
#define PCI_CHIP_RV630_958D 0x958D
|
||||
#define PCI_CHIP_RV630_958E 0x958E
|
||||
#define PCI_CHIP_RV630_958F 0x958F
|
||||
#define PCI_CHIP_RV620_95C0 0x95C0
|
||||
#define PCI_CHIP_RV620_95C2 0x95C2
|
||||
#define PCI_CHIP_RV620_95C4 0x95C4
|
||||
#define PCI_CHIP_RV620_95C5 0x95C5
|
||||
#define PCI_CHIP_RV620_95C6 0x95C6
|
||||
#define PCI_CHIP_RV620_95C7 0x95C7
|
||||
#define PCI_CHIP_RV620_95C9 0x95C9
|
||||
#define PCI_CHIP_RV620_95CC 0x95CC
|
||||
#define PCI_CHIP_RV620_95CD 0x95CD
|
||||
#define PCI_CHIP_RV620_95CE 0x95CE
|
||||
#define PCI_CHIP_RV620_95CF 0x95CF
|
||||
#define PCI_CHIP_RV635_9590 0x9590
|
||||
#define PCI_CHIP_RV635_9596 0x9596
|
||||
#define PCI_CHIP_RV635_9597 0x9597
|
||||
#define PCI_CHIP_RV635_9598 0x9598
|
||||
#define PCI_CHIP_RV635_9599 0x9599
|
||||
#define PCI_CHIP_RV635_9591 0x9591
|
||||
#define PCI_CHIP_RV635_9593 0x9593
|
||||
#define PCI_CHIP_RV635_9595 0x9595
|
||||
#define PCI_CHIP_RV635_959B 0x959B
|
||||
#define PCI_CHIP_RS780_9610 0x9610
|
||||
#define PCI_CHIP_RS780_9611 0x9611
|
||||
#define PCI_CHIP_RS780_9612 0x9612
|
||||
#define PCI_CHIP_RS780_9613 0x9613
|
||||
#define PCI_CHIP_RS780_9614 0x9614
|
||||
#define PCI_CHIP_RS780_9615 0x9615
|
||||
#define PCI_CHIP_RS780_9616 0x9616
|
||||
#define PCI_CHIP_SUMO_9640 0x9640
|
||||
#define PCI_CHIP_SUMO_9641 0x9641
|
||||
#define PCI_CHIP_SUMO2_9642 0x9642
|
||||
#define PCI_CHIP_SUMO2_9643 0x9643
|
||||
#define PCI_CHIP_SUMO2_9644 0x9644
|
||||
#define PCI_CHIP_SUMO2_9645 0x9645
|
||||
#define PCI_CHIP_SUMO_9647 0x9647
|
||||
#define PCI_CHIP_SUMO_9648 0x9648
|
||||
#define PCI_CHIP_SUMO2_9649 0x9649
|
||||
#define PCI_CHIP_SUMO_964A 0x964A
|
||||
#define PCI_CHIP_SUMO_964B 0x964B
|
||||
#define PCI_CHIP_SUMO_964C 0x964C
|
||||
#define PCI_CHIP_SUMO_964E 0x964E
|
||||
#define PCI_CHIP_SUMO_964F 0x964F
|
||||
#define PCI_CHIP_RS880_9710 0x9710
|
||||
#define PCI_CHIP_RS880_9711 0x9711
|
||||
#define PCI_CHIP_RS880_9712 0x9712
|
||||
#define PCI_CHIP_RS880_9713 0x9713
|
||||
#define PCI_CHIP_RS880_9714 0x9714
|
||||
#define PCI_CHIP_RS880_9715 0x9715
|
||||
#define PCI_CHIP_PALM_9802 0x9802
|
||||
#define PCI_CHIP_PALM_9803 0x9803
|
||||
#define PCI_CHIP_PALM_9804 0x9804
|
||||
#define PCI_CHIP_PALM_9805 0x9805
|
||||
#define PCI_CHIP_PALM_9806 0x9806
|
||||
#define PCI_CHIP_PALM_9807 0x9807
|
||||
#define PCI_CHIP_PALM_9808 0x9808
|
||||
#define PCI_CHIP_PALM_9809 0x9809
|
||||
#define PCI_CHIP_PALM_980A 0x980A
|
||||
#define PCI_CHIP_CYPRESS_6880 0x6880
|
||||
#define PCI_CHIP_CYPRESS_6888 0x6888
|
||||
#define PCI_CHIP_CYPRESS_6889 0x6889
|
||||
#define PCI_CHIP_CYPRESS_688A 0x688A
|
||||
#define PCI_CHIP_CYPRESS_688C 0x688C
|
||||
#define PCI_CHIP_CYPRESS_688D 0x688D
|
||||
#define PCI_CHIP_CYPRESS_6898 0x6898
|
||||
#define PCI_CHIP_CYPRESS_6899 0x6899
|
||||
#define PCI_CHIP_CYPRESS_689B 0x689B
|
||||
#define PCI_CHIP_CYPRESS_689E 0x689E
|
||||
#define PCI_CHIP_HEMLOCK_689C 0x689C
|
||||
#define PCI_CHIP_HEMLOCK_689D 0x689D
|
||||
#define PCI_CHIP_JUNIPER_68A0 0x68A0
|
||||
#define PCI_CHIP_JUNIPER_68A1 0x68A1
|
||||
#define PCI_CHIP_JUNIPER_68A8 0x68A8
|
||||
#define PCI_CHIP_JUNIPER_68A9 0x68A9
|
||||
#define PCI_CHIP_JUNIPER_68B0 0x68B0
|
||||
#define PCI_CHIP_JUNIPER_68B8 0x68B8
|
||||
#define PCI_CHIP_JUNIPER_68B9 0x68B9
|
||||
#define PCI_CHIP_JUNIPER_68BA 0x68BA
|
||||
#define PCI_CHIP_JUNIPER_68BE 0x68BE
|
||||
#define PCI_CHIP_JUNIPER_68BF 0x68BF
|
||||
#define PCI_CHIP_REDWOOD_68C0 0x68C0
|
||||
#define PCI_CHIP_REDWOOD_68C1 0x68C1
|
||||
#define PCI_CHIP_REDWOOD_68C7 0x68C7
|
||||
#define PCI_CHIP_REDWOOD_68C8 0x68C8
|
||||
#define PCI_CHIP_REDWOOD_68C9 0x68C9
|
||||
#define PCI_CHIP_REDWOOD_68D8 0x68D8
|
||||
#define PCI_CHIP_REDWOOD_68D9 0x68D9
|
||||
#define PCI_CHIP_REDWOOD_68DA 0x68DA
|
||||
#define PCI_CHIP_REDWOOD_68DE 0x68DE
|
||||
#define PCI_CHIP_CEDAR_68E0 0x68E0
|
||||
#define PCI_CHIP_CEDAR_68E1 0x68E1
|
||||
#define PCI_CHIP_CEDAR_68E4 0x68E4
|
||||
#define PCI_CHIP_CEDAR_68E5 0x68E5
|
||||
#define PCI_CHIP_CEDAR_68E8 0x68E8
|
||||
#define PCI_CHIP_CEDAR_68E9 0x68E9
|
||||
#define PCI_CHIP_CEDAR_68F1 0x68F1
|
||||
#define PCI_CHIP_CEDAR_68F2 0x68F2
|
||||
#define PCI_CHIP_CEDAR_68F8 0x68F8
|
||||
#define PCI_CHIP_CEDAR_68F9 0x68F9
|
||||
#define PCI_CHIP_CEDAR_68FA 0x68FA
|
||||
#define PCI_CHIP_CEDAR_68FE 0x68FE
|
||||
#define PCI_CHIP_CAYMAN_6700 0x6700
|
||||
#define PCI_CHIP_CAYMAN_6701 0x6701
|
||||
#define PCI_CHIP_CAYMAN_6702 0x6702
|
||||
#define PCI_CHIP_CAYMAN_6703 0x6703
|
||||
#define PCI_CHIP_CAYMAN_6704 0x6704
|
||||
#define PCI_CHIP_CAYMAN_6705 0x6705
|
||||
#define PCI_CHIP_CAYMAN_6706 0x6706
|
||||
#define PCI_CHIP_CAYMAN_6707 0x6707
|
||||
#define PCI_CHIP_CAYMAN_6708 0x6708
|
||||
#define PCI_CHIP_CAYMAN_6709 0x6709
|
||||
#define PCI_CHIP_CAYMAN_6718 0x6718
|
||||
#define PCI_CHIP_CAYMAN_6719 0x6719
|
||||
#define PCI_CHIP_CAYMAN_671C 0x671C
|
||||
#define PCI_CHIP_CAYMAN_671D 0x671D
|
||||
#define PCI_CHIP_CAYMAN_671F 0x671F
|
||||
#define PCI_CHIP_BARTS_6720 0x6720
|
||||
#define PCI_CHIP_BARTS_6721 0x6721
|
||||
#define PCI_CHIP_BARTS_6722 0x6722
|
||||
#define PCI_CHIP_BARTS_6723 0x6723
|
||||
#define PCI_CHIP_BARTS_6724 0x6724
|
||||
#define PCI_CHIP_BARTS_6725 0x6725
|
||||
#define PCI_CHIP_BARTS_6726 0x6726
|
||||
#define PCI_CHIP_BARTS_6727 0x6727
|
||||
#define PCI_CHIP_BARTS_6728 0x6728
|
||||
#define PCI_CHIP_BARTS_6729 0x6729
|
||||
#define PCI_CHIP_BARTS_6738 0x6738
|
||||
#define PCI_CHIP_BARTS_6739 0x6739
|
||||
#define PCI_CHIP_BARTS_673E 0x673E
|
||||
#define PCI_CHIP_TURKS_6740 0x6740
|
||||
#define PCI_CHIP_TURKS_6741 0x6741
|
||||
#define PCI_CHIP_TURKS_6742 0x6742
|
||||
#define PCI_CHIP_TURKS_6743 0x6743
|
||||
#define PCI_CHIP_TURKS_6744 0x6744
|
||||
#define PCI_CHIP_TURKS_6745 0x6745
|
||||
#define PCI_CHIP_TURKS_6746 0x6746
|
||||
#define PCI_CHIP_TURKS_6747 0x6747
|
||||
#define PCI_CHIP_TURKS_6748 0x6748
|
||||
#define PCI_CHIP_TURKS_6749 0x6749
|
||||
#define PCI_CHIP_TURKS_674A 0x674A
|
||||
#define PCI_CHIP_TURKS_6750 0x6750
|
||||
#define PCI_CHIP_TURKS_6751 0x6751
|
||||
#define PCI_CHIP_TURKS_6758 0x6758
|
||||
#define PCI_CHIP_TURKS_6759 0x6759
|
||||
#define PCI_CHIP_TURKS_675B 0x675B
|
||||
#define PCI_CHIP_TURKS_675D 0x675D
|
||||
#define PCI_CHIP_TURKS_675F 0x675F
|
||||
#define PCI_CHIP_TURKS_6840 0x6840
|
||||
#define PCI_CHIP_TURKS_6841 0x6841
|
||||
#define PCI_CHIP_TURKS_6842 0x6842
|
||||
#define PCI_CHIP_TURKS_6843 0x6843
|
||||
#define PCI_CHIP_TURKS_6849 0x6849
|
||||
#define PCI_CHIP_TURKS_6850 0x6850
|
||||
#define PCI_CHIP_TURKS_6858 0x6858
|
||||
#define PCI_CHIP_TURKS_6859 0x6859
|
||||
#define PCI_CHIP_CAICOS_6760 0x6760
|
||||
#define PCI_CHIP_CAICOS_6761 0x6761
|
||||
#define PCI_CHIP_CAICOS_6762 0x6762
|
||||
#define PCI_CHIP_CAICOS_6763 0x6763
|
||||
#define PCI_CHIP_CAICOS_6764 0x6764
|
||||
#define PCI_CHIP_CAICOS_6765 0x6765
|
||||
#define PCI_CHIP_CAICOS_6766 0x6766
|
||||
#define PCI_CHIP_CAICOS_6767 0x6767
|
||||
#define PCI_CHIP_CAICOS_6768 0x6768
|
||||
#define PCI_CHIP_CAICOS_6770 0x6770
|
||||
#define PCI_CHIP_CAICOS_6771 0x6771
|
||||
#define PCI_CHIP_CAICOS_6772 0x6772
|
||||
#define PCI_CHIP_CAICOS_6778 0x6778
|
||||
#define PCI_CHIP_CAICOS_6779 0x6779
|
||||
#define PCI_CHIP_CAICOS_677B 0x677B
|
||||
#define PCI_CHIP_ARUBA_9900 0x9900
|
||||
#define PCI_CHIP_ARUBA_9901 0x9901
|
||||
#define PCI_CHIP_ARUBA_9903 0x9903
|
||||
#define PCI_CHIP_ARUBA_9904 0x9904
|
||||
#define PCI_CHIP_ARUBA_9905 0x9905
|
||||
#define PCI_CHIP_ARUBA_9906 0x9906
|
||||
#define PCI_CHIP_ARUBA_9907 0x9907
|
||||
#define PCI_CHIP_ARUBA_9908 0x9908
|
||||
#define PCI_CHIP_ARUBA_9909 0x9909
|
||||
#define PCI_CHIP_ARUBA_990A 0x990A
|
||||
#define PCI_CHIP_ARUBA_990B 0x990B
|
||||
#define PCI_CHIP_ARUBA_990C 0x990C
|
||||
#define PCI_CHIP_ARUBA_990D 0x990D
|
||||
#define PCI_CHIP_ARUBA_990E 0x990E
|
||||
#define PCI_CHIP_ARUBA_990F 0x990F
|
||||
#define PCI_CHIP_ARUBA_9910 0x9910
|
||||
#define PCI_CHIP_ARUBA_9913 0x9913
|
||||
#define PCI_CHIP_ARUBA_9917 0x9917
|
||||
#define PCI_CHIP_ARUBA_9918 0x9918
|
||||
#define PCI_CHIP_ARUBA_9919 0x9919
|
||||
#define PCI_CHIP_ARUBA_9990 0x9990
|
||||
#define PCI_CHIP_ARUBA_9991 0x9991
|
||||
#define PCI_CHIP_ARUBA_9992 0x9992
|
||||
#define PCI_CHIP_ARUBA_9993 0x9993
|
||||
#define PCI_CHIP_ARUBA_9994 0x9994
|
||||
#define PCI_CHIP_ARUBA_9995 0x9995
|
||||
#define PCI_CHIP_ARUBA_9996 0x9996
|
||||
#define PCI_CHIP_ARUBA_9997 0x9997
|
||||
#define PCI_CHIP_ARUBA_9998 0x9998
|
||||
#define PCI_CHIP_ARUBA_9999 0x9999
|
||||
#define PCI_CHIP_ARUBA_999A 0x999A
|
||||
#define PCI_CHIP_ARUBA_999B 0x999B
|
||||
#define PCI_CHIP_ARUBA_999C 0x999C
|
||||
#define PCI_CHIP_ARUBA_999D 0x999D
|
||||
#define PCI_CHIP_ARUBA_99A0 0x99A0
|
||||
#define PCI_CHIP_ARUBA_99A2 0x99A2
|
||||
#define PCI_CHIP_ARUBA_99A4 0x99A4
|
||||
#define PCI_CHIP_TAHITI_6780 0x6780
|
||||
#define PCI_CHIP_TAHITI_6784 0x6784
|
||||
#define PCI_CHIP_TAHITI_6788 0x6788
|
||||
#define PCI_CHIP_TAHITI_678A 0x678A
|
||||
#define PCI_CHIP_TAHITI_6790 0x6790
|
||||
#define PCI_CHIP_TAHITI_6791 0x6791
|
||||
#define PCI_CHIP_TAHITI_6792 0x6792
|
||||
#define PCI_CHIP_TAHITI_6798 0x6798
|
||||
#define PCI_CHIP_TAHITI_6799 0x6799
|
||||
#define PCI_CHIP_TAHITI_679A 0x679A
|
||||
#define PCI_CHIP_TAHITI_679B 0x679B
|
||||
#define PCI_CHIP_TAHITI_679E 0x679E
|
||||
#define PCI_CHIP_TAHITI_679F 0x679F
|
||||
#define PCI_CHIP_PITCAIRN_6800 0x6800
|
||||
#define PCI_CHIP_PITCAIRN_6801 0x6801
|
||||
#define PCI_CHIP_PITCAIRN_6802 0x6802
|
||||
#define PCI_CHIP_PITCAIRN_6806 0x6806
|
||||
#define PCI_CHIP_PITCAIRN_6808 0x6808
|
||||
#define PCI_CHIP_PITCAIRN_6809 0x6809
|
||||
#define PCI_CHIP_PITCAIRN_6810 0x6810
|
||||
#define PCI_CHIP_PITCAIRN_6811 0x6811
|
||||
#define PCI_CHIP_PITCAIRN_6816 0x6816
|
||||
#define PCI_CHIP_PITCAIRN_6817 0x6817
|
||||
#define PCI_CHIP_PITCAIRN_6818 0x6818
|
||||
#define PCI_CHIP_PITCAIRN_6819 0x6819
|
||||
#define PCI_CHIP_PITCAIRN_684C 0x684C
|
||||
#define PCI_CHIP_VERDE_6820 0x6820
|
||||
#define PCI_CHIP_VERDE_6821 0x6821
|
||||
#define PCI_CHIP_VERDE_6822 0x6822
|
||||
#define PCI_CHIP_VERDE_6823 0x6823
|
||||
#define PCI_CHIP_VERDE_6824 0x6824
|
||||
#define PCI_CHIP_VERDE_6825 0x6825
|
||||
#define PCI_CHIP_VERDE_6826 0x6826
|
||||
#define PCI_CHIP_VERDE_6827 0x6827
|
||||
#define PCI_CHIP_VERDE_6828 0x6828
|
||||
#define PCI_CHIP_VERDE_6829 0x6829
|
||||
#define PCI_CHIP_VERDE_682A 0x682A
|
||||
#define PCI_CHIP_VERDE_682B 0x682B
|
||||
#define PCI_CHIP_VERDE_682C 0x682C
|
||||
#define PCI_CHIP_VERDE_682D 0x682D
|
||||
#define PCI_CHIP_VERDE_682F 0x682F
|
||||
#define PCI_CHIP_VERDE_6830 0x6830
|
||||
#define PCI_CHIP_VERDE_6831 0x6831
|
||||
#define PCI_CHIP_VERDE_6835 0x6835
|
||||
#define PCI_CHIP_VERDE_6837 0x6837
|
||||
#define PCI_CHIP_VERDE_6838 0x6838
|
||||
#define PCI_CHIP_VERDE_6839 0x6839
|
||||
#define PCI_CHIP_VERDE_683B 0x683B
|
||||
#define PCI_CHIP_VERDE_683D 0x683D
|
||||
#define PCI_CHIP_VERDE_683F 0x683F
|
||||
#define PCI_CHIP_OLAND_6600 0x6600
|
||||
#define PCI_CHIP_OLAND_6601 0x6601
|
||||
#define PCI_CHIP_OLAND_6602 0x6602
|
||||
#define PCI_CHIP_OLAND_6603 0x6603
|
||||
#define PCI_CHIP_OLAND_6604 0x6604
|
||||
#define PCI_CHIP_OLAND_6605 0x6605
|
||||
#define PCI_CHIP_OLAND_6606 0x6606
|
||||
#define PCI_CHIP_OLAND_6607 0x6607
|
||||
#define PCI_CHIP_OLAND_6608 0x6608
|
||||
#define PCI_CHIP_OLAND_6610 0x6610
|
||||
#define PCI_CHIP_OLAND_6611 0x6611
|
||||
#define PCI_CHIP_OLAND_6613 0x6613
|
||||
#define PCI_CHIP_OLAND_6617 0x6617
|
||||
#define PCI_CHIP_OLAND_6620 0x6620
|
||||
#define PCI_CHIP_OLAND_6621 0x6621
|
||||
#define PCI_CHIP_OLAND_6623 0x6623
|
||||
#define PCI_CHIP_OLAND_6631 0x6631
|
||||
#define PCI_CHIP_HAINAN_6660 0x6660
|
||||
#define PCI_CHIP_HAINAN_6663 0x6663
|
||||
#define PCI_CHIP_HAINAN_6664 0x6664
|
||||
#define PCI_CHIP_HAINAN_6665 0x6665
|
||||
#define PCI_CHIP_HAINAN_6667 0x6667
|
||||
#define PCI_CHIP_HAINAN_666F 0x666F
|
||||
#define PCI_CHIP_BONAIRE_6640 0x6640
|
||||
#define PCI_CHIP_BONAIRE_6641 0x6641
|
||||
#define PCI_CHIP_BONAIRE_6646 0x6646
|
||||
#define PCI_CHIP_BONAIRE_6647 0x6647
|
||||
#define PCI_CHIP_BONAIRE_6649 0x6649
|
||||
#define PCI_CHIP_BONAIRE_6650 0x6650
|
||||
#define PCI_CHIP_BONAIRE_6651 0x6651
|
||||
#define PCI_CHIP_BONAIRE_6658 0x6658
|
||||
#define PCI_CHIP_BONAIRE_665C 0x665C
|
||||
#define PCI_CHIP_BONAIRE_665D 0x665D
|
||||
#define PCI_CHIP_BONAIRE_665F 0x665F
|
||||
#define PCI_CHIP_KABINI_9830 0x9830
|
||||
#define PCI_CHIP_KABINI_9831 0x9831
|
||||
#define PCI_CHIP_KABINI_9832 0x9832
|
||||
#define PCI_CHIP_KABINI_9833 0x9833
|
||||
#define PCI_CHIP_KABINI_9834 0x9834
|
||||
#define PCI_CHIP_KABINI_9835 0x9835
|
||||
#define PCI_CHIP_KABINI_9836 0x9836
|
||||
#define PCI_CHIP_KABINI_9837 0x9837
|
||||
#define PCI_CHIP_KABINI_9838 0x9838
|
||||
#define PCI_CHIP_KABINI_9839 0x9839
|
||||
#define PCI_CHIP_KABINI_983A 0x983A
|
||||
#define PCI_CHIP_KABINI_983B 0x983B
|
||||
#define PCI_CHIP_KABINI_983C 0x983C
|
||||
#define PCI_CHIP_KABINI_983D 0x983D
|
||||
#define PCI_CHIP_KABINI_983E 0x983E
|
||||
#define PCI_CHIP_KABINI_983F 0x983F
|
||||
#define PCI_CHIP_MULLINS_9850 0x9850
|
||||
#define PCI_CHIP_MULLINS_9851 0x9851
|
||||
#define PCI_CHIP_MULLINS_9852 0x9852
|
||||
#define PCI_CHIP_MULLINS_9853 0x9853
|
||||
#define PCI_CHIP_MULLINS_9854 0x9854
|
||||
#define PCI_CHIP_MULLINS_9855 0x9855
|
||||
#define PCI_CHIP_MULLINS_9856 0x9856
|
||||
#define PCI_CHIP_MULLINS_9857 0x9857
|
||||
#define PCI_CHIP_MULLINS_9858 0x9858
|
||||
#define PCI_CHIP_MULLINS_9859 0x9859
|
||||
#define PCI_CHIP_MULLINS_985A 0x985A
|
||||
#define PCI_CHIP_MULLINS_985B 0x985B
|
||||
#define PCI_CHIP_MULLINS_985C 0x985C
|
||||
#define PCI_CHIP_MULLINS_985D 0x985D
|
||||
#define PCI_CHIP_MULLINS_985E 0x985E
|
||||
#define PCI_CHIP_MULLINS_985F 0x985F
|
||||
#define PCI_CHIP_KAVERI_1304 0x1304
|
||||
#define PCI_CHIP_KAVERI_1305 0x1305
|
||||
#define PCI_CHIP_KAVERI_1306 0x1306
|
||||
#define PCI_CHIP_KAVERI_1307 0x1307
|
||||
#define PCI_CHIP_KAVERI_1309 0x1309
|
||||
#define PCI_CHIP_KAVERI_130A 0x130A
|
||||
#define PCI_CHIP_KAVERI_130B 0x130B
|
||||
#define PCI_CHIP_KAVERI_130C 0x130C
|
||||
#define PCI_CHIP_KAVERI_130D 0x130D
|
||||
#define PCI_CHIP_KAVERI_130E 0x130E
|
||||
#define PCI_CHIP_KAVERI_130F 0x130F
|
||||
#define PCI_CHIP_KAVERI_1310 0x1310
|
||||
#define PCI_CHIP_KAVERI_1311 0x1311
|
||||
#define PCI_CHIP_KAVERI_1312 0x1312
|
||||
#define PCI_CHIP_KAVERI_1313 0x1313
|
||||
#define PCI_CHIP_KAVERI_1315 0x1315
|
||||
#define PCI_CHIP_KAVERI_1316 0x1316
|
||||
#define PCI_CHIP_KAVERI_1317 0x1317
|
||||
#define PCI_CHIP_KAVERI_1318 0x1318
|
||||
#define PCI_CHIP_KAVERI_131B 0x131B
|
||||
#define PCI_CHIP_KAVERI_131C 0x131C
|
||||
#define PCI_CHIP_KAVERI_131D 0x131D
|
||||
#define PCI_CHIP_HAWAII_67A0 0x67A0
|
||||
#define PCI_CHIP_HAWAII_67A1 0x67A1
|
||||
#define PCI_CHIP_HAWAII_67A2 0x67A2
|
||||
#define PCI_CHIP_HAWAII_67A8 0x67A8
|
||||
#define PCI_CHIP_HAWAII_67A9 0x67A9
|
||||
#define PCI_CHIP_HAWAII_67AA 0x67AA
|
||||
#define PCI_CHIP_HAWAII_67B0 0x67B0
|
||||
#define PCI_CHIP_HAWAII_67B1 0x67B1
|
||||
#define PCI_CHIP_HAWAII_67B8 0x67B8
|
||||
#define PCI_CHIP_HAWAII_67B9 0x67B9
|
||||
#define PCI_CHIP_HAWAII_67BA 0x67BA
|
||||
#define PCI_CHIP_HAWAII_67BE 0x67BE
|
||||
74
src/atimodule.c
Normal file
74
src/atimodule.c
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "ati.h"
|
||||
#include "ativersion.h"
|
||||
|
||||
/* Module loader interface */
|
||||
|
||||
static XF86ModuleVersionInfo ATIVersionRec =
|
||||
{
|
||||
ATI_DRIVER_NAME,
|
||||
MODULEVENDORSTRING,
|
||||
MODINFOSTRING1,
|
||||
MODINFOSTRING2,
|
||||
XORG_VERSION_CURRENT,
|
||||
ATI_VERSION_MAJOR, ATI_VERSION_MINOR, ATI_VERSION_PATCH,
|
||||
ABI_CLASS_VIDEODRV,
|
||||
ABI_VIDEODRV_VERSION,
|
||||
MOD_CLASS_VIDEODRV,
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
/*
|
||||
* ATISetup --
|
||||
*
|
||||
* This function is called every time the module is loaded.
|
||||
*/
|
||||
static void*
|
||||
ATISetup
|
||||
(
|
||||
void *Module,
|
||||
void *Options,
|
||||
int *ErrorMajor,
|
||||
int *ErrorMinor
|
||||
)
|
||||
{
|
||||
static Bool Inited = FALSE;
|
||||
|
||||
if (!Inited)
|
||||
{
|
||||
Inited = TRUE;
|
||||
ati_gdev_subdriver(Options);
|
||||
}
|
||||
|
||||
return (void*)1;
|
||||
}
|
||||
|
||||
/* The following record must be called atiModuleData */
|
||||
_X_EXPORT XF86ModuleData atiModuleData =
|
||||
{
|
||||
&ATIVersionRec,
|
||||
ATISetup,
|
||||
NULL
|
||||
};
|
||||
54
src/atipciids.h
Normal file
54
src/atipciids.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (c) 1995-2003 by The XFree86 Project, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the copyright holder(s)
|
||||
* and author(s) shall not be used in advertising or otherwise to promote
|
||||
* the sale, use or other dealings in this Software without prior written
|
||||
* authorization from the copyright holder(s) and author(s).
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is a replacement for xf86PciInfo.h moving ATI related PCI IDs
|
||||
* locally to the driver module
|
||||
*/
|
||||
|
||||
#ifndef _ATIPCIIDS_H
|
||||
#define _ATIPCIIDS_H
|
||||
|
||||
/* PCI Vendor */
|
||||
#define PCI_VENDOR_ASUS 0x1043
|
||||
#define PCI_VENDOR_ATI 0x1002
|
||||
#define PCI_VENDOR_IBM 0x1014
|
||||
#define PCI_VENDOR_AMD 0x1022
|
||||
#define PCI_VENDOR_DELL 0x1028
|
||||
#define PCI_VENDOR_VIA 0x1106
|
||||
#define PCI_VENDOR_INTEL 0x8086
|
||||
#ifndef PCI_VENDOR_HP
|
||||
#define PCI_VENDOR_HP 0x103c
|
||||
#endif
|
||||
#define PCI_VENDOR_SONY 0x104D
|
||||
|
||||
#include "ati_pciids_gen.h"
|
||||
|
||||
/* Misc */
|
||||
#define PCI_CHIP_AMD761 0x700E
|
||||
|
||||
#endif /* _ATIPCIIDS_H */
|
||||
78
src/atipcirename.h
Normal file
78
src/atipcirename.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright 2007 George Sapountzis
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Macros for porting drivers from legacy xfree86 PCI code to the pciaccess
|
||||
* library. The main purpose being to facilitate source code compatibility.
|
||||
*/
|
||||
|
||||
#ifndef ATIPCIRENAME_H
|
||||
#define ATIPCIRENAME_H
|
||||
|
||||
enum region_type {
|
||||
REGION_MEM,
|
||||
REGION_IO
|
||||
};
|
||||
|
||||
typedef struct pci_device *pciVideoPtr;
|
||||
|
||||
#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id)
|
||||
#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id)
|
||||
#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->revision)
|
||||
|
||||
#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id)
|
||||
#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id)
|
||||
|
||||
/* pci-rework functions take a 'pci_device' parameter instead of a tag */
|
||||
#define PCI_DEV_TAG(_pcidev) (_pcidev)
|
||||
|
||||
/* PCI_DEV macros, typically used in printf's, add domain ? XXX */
|
||||
#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
|
||||
#define PCI_DEV_DEV(_pcidev) ((_pcidev)->dev)
|
||||
#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
|
||||
|
||||
/* pci-rework functions take a 'pci_device' parameter instead of a tag */
|
||||
#define PCI_CFG_TAG(_pcidev) (_pcidev)
|
||||
|
||||
/* PCI_CFG macros, typically used in DRI init, contain the domain */
|
||||
#define PCI_CFG_BUS(_pcidev) (((_pcidev)->domain << 8) | \
|
||||
(_pcidev)->bus)
|
||||
#define PCI_CFG_DEV(_pcidev) ((_pcidev)->dev)
|
||||
#define PCI_CFG_FUNC(_pcidev) ((_pcidev)->func)
|
||||
|
||||
#define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr)
|
||||
#define PCI_REGION_SIZE(_pcidev, _b) ((_pcidev)->regions[(_b)].size)
|
||||
|
||||
#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
|
||||
pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset))
|
||||
|
||||
#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
|
||||
pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset))
|
||||
|
||||
#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
|
||||
pci_device_cfg_write_u32((_pcidev), (_value), (_offset))
|
||||
|
||||
#define ATI_DEVICE_MATCH(d, i) \
|
||||
{ PCI_VENDOR_ATI, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
|
||||
|
||||
#endif /* ATIPCIRENAME_H */
|
||||
54
src/ativersion.h
Normal file
54
src/ativersion.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef ___ATIVERSION_H___
|
||||
#define ___ATIVERSION_H___ 1
|
||||
|
||||
#undef ATI_NAME
|
||||
#undef ATI_DRIVER_NAME
|
||||
#undef ATI_VERSION_CURRENT
|
||||
#undef ATI_VERSION_EVALUATE
|
||||
#undef ATI_VERSION_STRINGIFY
|
||||
#undef ATI_VERSION_NAME
|
||||
|
||||
#define ATI_NAME "ATI"
|
||||
#define ATI_DRIVER_NAME "ati"
|
||||
|
||||
#ifndef ATI_VERSION_EXTRA
|
||||
#define ATI_VERSION_EXTRA ""
|
||||
#endif
|
||||
|
||||
#define ATI_VERSION_MAJOR PACKAGE_VERSION_MAJOR
|
||||
#define ATI_VERSION_MINOR PACKAGE_VERSION_MINOR
|
||||
#define ATI_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
|
||||
|
||||
#define ATI_VERSION_CURRENT \
|
||||
((ATI_VERSION_MAJOR << 20) | (ATI_VERSION_MINOR << 10) | ATI_VERSION_PATCH)
|
||||
|
||||
#define ATI_VERSION_EVALUATE(__x) #__x
|
||||
#define ATI_VERSION_STRINGIFY(_x) ATI_VERSION_EVALUATE(_x)
|
||||
#define ATI_VERSION_NAME \
|
||||
ATI_VERSION_STRINGIFY(ATI_VERSION_MAJOR) "." \
|
||||
ATI_VERSION_STRINGIFY(ATI_VERSION_MINOR) "." \
|
||||
ATI_VERSION_STRINGIFY(ATI_VERSION_PATCH) ATI_VERSION_EXTRA
|
||||
|
||||
#endif /* ___ATIVERSION_H___ */
|
||||
646
src/bicubic_table.h
Normal file
646
src/bicubic_table.h
Normal file
|
|
@ -0,0 +1,646 @@
|
|||
static const uint16_t bicubic_tex_512[] = {
|
||||
0xb266, 0x3c00, 0x3aaa, 0x3155,
|
||||
0xb287, 0x3bf0, 0x3aa2, 0x3175,
|
||||
0xb2a9, 0x3be0, 0x3a9a, 0x3196,
|
||||
0xb2cc, 0x3bd0, 0x3a92, 0x31b7,
|
||||
0xb2ee, 0x3bc0, 0x3a89, 0x31d9,
|
||||
0xb312, 0x3bb0, 0x3a81, 0x31fb,
|
||||
0xb335, 0x3ba0, 0x3a78, 0x321e,
|
||||
0xb359, 0x3b90, 0x3a6f, 0x3241,
|
||||
0xb37d, 0x3b80, 0x3a66, 0x3264,
|
||||
0xb3a2, 0x3b70, 0x3a5d, 0x3288,
|
||||
0xb3c7, 0x3b60, 0x3a54, 0x32ad,
|
||||
0xb3ed, 0x3b51, 0x3a4b, 0x32d1,
|
||||
0xb409, 0x3b41, 0x3a42, 0x32f7,
|
||||
0xb41c, 0x3b31, 0x3a38, 0x331c,
|
||||
0xb42f, 0x3b21, 0x3a2f, 0x3342,
|
||||
0xb443, 0x3b12, 0x3a25, 0x3369,
|
||||
0xb456, 0x3b02, 0x3a1c, 0x3390,
|
||||
0xb46a, 0x3af3, 0x3a12, 0x33b7,
|
||||
0xb47e, 0x3ae3, 0x3a08, 0x33de,
|
||||
0xb492, 0x3ad4, 0x39fe, 0x3403,
|
||||
0xb4a6, 0x3ac5, 0x39f4, 0x3417,
|
||||
0xb4bb, 0x3ab5, 0x39ea, 0x342b,
|
||||
0xb4cf, 0x3aa6, 0x39df, 0x3440,
|
||||
0xb4e4, 0x3a97, 0x39d5, 0x3454,
|
||||
0xb4f9, 0x3a88, 0x39cb, 0x3469,
|
||||
0xb50e, 0x3a79, 0x39c0, 0x347e,
|
||||
0xb523, 0x3a6a, 0x39b6, 0x3493,
|
||||
0xb539, 0x3a5a, 0x39ab, 0x34a8,
|
||||
0xb54e, 0x3a4c, 0x39a0, 0x34be,
|
||||
0xb564, 0x3a3d, 0x3996, 0x34d3,
|
||||
0xb57a, 0x3a2e, 0x398b, 0x34e9,
|
||||
0xb590, 0x3a1f, 0x3980, 0x34ff,
|
||||
0xb5a6, 0x3a10, 0x3975, 0x3515,
|
||||
0xb5bc, 0x3a02, 0x396a, 0x352b,
|
||||
0xb5d2, 0x39f3, 0x395f, 0x3541,
|
||||
0xb5e9, 0x39e4, 0x3954, 0x3557,
|
||||
0xb5ff, 0x39d6, 0x3948, 0x356e,
|
||||
0xb616, 0x39c7, 0x393d, 0x3584,
|
||||
0xb62d, 0x39b9, 0x3932, 0x359b,
|
||||
0xb644, 0x39ab, 0x3926, 0x35b2,
|
||||
0xb65b, 0x399c, 0x391b, 0x35c9,
|
||||
0xb672, 0x398e, 0x3910, 0x35df,
|
||||
0xb68a, 0x3980, 0x3904, 0x35f6,
|
||||
0xb6a1, 0x3972, 0x38f8, 0x360e,
|
||||
0xb6b9, 0x3964, 0x38ed, 0x3625,
|
||||
0xb6d1, 0x3956, 0x38e1, 0x363c,
|
||||
0xb6e8, 0x3948, 0x38d6, 0x3653,
|
||||
0xb700, 0x393a, 0x38ca, 0x366b,
|
||||
0xb719, 0x392c, 0x38be, 0x3682,
|
||||
0xb731, 0x391e, 0x38b2, 0x369a,
|
||||
0xb749, 0x3910, 0x38a7, 0x36b1,
|
||||
0xb762, 0x3902, 0x389b, 0x36c9,
|
||||
0xb77a, 0x38f5, 0x388f, 0x36e1,
|
||||
0xb793, 0x38e7, 0x3883, 0x36f8,
|
||||
0xb7ac, 0x38da, 0x3877, 0x3710,
|
||||
0xb7c5, 0x38cc, 0x386b, 0x3728,
|
||||
0xb7de, 0x38bf, 0x385f, 0x3740,
|
||||
0xb7f7, 0x38b1, 0x3853, 0x3758,
|
||||
0xb808, 0x38a4, 0x3847, 0x3770,
|
||||
0xb815, 0x3897, 0x383b, 0x3788,
|
||||
0xb821, 0x3889, 0x382f, 0x37a0,
|
||||
0xb82e, 0x387c, 0x3823, 0x37b8,
|
||||
0xb83b, 0x386f, 0x3817, 0x37d0,
|
||||
0xb848, 0x3862, 0x380b, 0x37e8,
|
||||
0xb855, 0x3855, 0x3800, 0x3800,
|
||||
0xb862, 0x3848, 0x37e8, 0x380b,
|
||||
0xb86f, 0x383b, 0x37d0, 0x3817,
|
||||
0xb87c, 0x382e, 0x37b8, 0x3823,
|
||||
0xb889, 0x3821, 0x37a0, 0x382f,
|
||||
0xb897, 0x3815, 0x3788, 0x383b,
|
||||
0xb8a4, 0x3808, 0x3770, 0x3847,
|
||||
0xb8b1, 0x37f7, 0x3758, 0x3853,
|
||||
0xb8bf, 0x37de, 0x3740, 0x385f,
|
||||
0xb8cc, 0x37c5, 0x3728, 0x386b,
|
||||
0xb8da, 0x37ac, 0x3710, 0x3877,
|
||||
0xb8e7, 0x3793, 0x36f8, 0x3883,
|
||||
0xb8f5, 0x377a, 0x36e1, 0x388f,
|
||||
0xb902, 0x3762, 0x36c9, 0x389b,
|
||||
0xb910, 0x3749, 0x36b1, 0x38a7,
|
||||
0xb91e, 0x3731, 0x369a, 0x38b2,
|
||||
0xb92c, 0x3719, 0x3682, 0x38be,
|
||||
0xb93a, 0x3700, 0x366b, 0x38ca,
|
||||
0xb948, 0x36e8, 0x3653, 0x38d6,
|
||||
0xb956, 0x36d1, 0x363c, 0x38e1,
|
||||
0xb964, 0x36b9, 0x3625, 0x38ed,
|
||||
0xb972, 0x36a1, 0x360e, 0x38f8,
|
||||
0xb980, 0x368a, 0x35f6, 0x3904,
|
||||
0xb98e, 0x3672, 0x35df, 0x3910,
|
||||
0xb99c, 0x365b, 0x35c9, 0x391b,
|
||||
0xb9ab, 0x3644, 0x35b2, 0x3926,
|
||||
0xb9b9, 0x362d, 0x359b, 0x3932,
|
||||
0xb9c7, 0x3616, 0x3584, 0x393d,
|
||||
0xb9d6, 0x35ff, 0x356e, 0x3948,
|
||||
0xb9e4, 0x35e9, 0x3557, 0x3954,
|
||||
0xb9f3, 0x35d2, 0x3541, 0x395f,
|
||||
0xba02, 0x35bc, 0x352b, 0x396a,
|
||||
0xba10, 0x35a6, 0x3515, 0x3975,
|
||||
0xba1f, 0x3590, 0x34ff, 0x3980,
|
||||
0xba2e, 0x357a, 0x34e9, 0x398b,
|
||||
0xba3d, 0x3564, 0x34d3, 0x3996,
|
||||
0xba4c, 0x354e, 0x34be, 0x39a0,
|
||||
0xba5a, 0x3539, 0x34a8, 0x39ab,
|
||||
0xba6a, 0x3523, 0x3493, 0x39b6,
|
||||
0xba79, 0x350e, 0x347e, 0x39c0,
|
||||
0xba88, 0x34f9, 0x3469, 0x39cb,
|
||||
0xba97, 0x34e4, 0x3454, 0x39d5,
|
||||
0xbaa6, 0x34cf, 0x3440, 0x39df,
|
||||
0xbab5, 0x34bb, 0x342b, 0x39ea,
|
||||
0xbac5, 0x34a6, 0x3417, 0x39f4,
|
||||
0xbad4, 0x3492, 0x3403, 0x39fe,
|
||||
0xbae3, 0x347e, 0x33de, 0x3a08,
|
||||
0xbaf3, 0x346a, 0x33b7, 0x3a12,
|
||||
0xbb02, 0x3456, 0x3390, 0x3a1c,
|
||||
0xbb12, 0x3443, 0x3369, 0x3a25,
|
||||
0xbb21, 0x342f, 0x3342, 0x3a2f,
|
||||
0xbb31, 0x341c, 0x331c, 0x3a38,
|
||||
0xbb41, 0x3409, 0x32f7, 0x3a42,
|
||||
0xbb51, 0x33ed, 0x32d1, 0x3a4b,
|
||||
0xbb60, 0x33c7, 0x32ad, 0x3a54,
|
||||
0xbb70, 0x33a2, 0x3288, 0x3a5d,
|
||||
0xbb80, 0x337d, 0x3264, 0x3a66,
|
||||
0xbb90, 0x3359, 0x3241, 0x3a6f,
|
||||
0xbba0, 0x3335, 0x321e, 0x3a78,
|
||||
0xbbb0, 0x3312, 0x31fb, 0x3a81,
|
||||
0xbbc0, 0x32ee, 0x31d9, 0x3a89,
|
||||
0xbbd0, 0x32cc, 0x31b7, 0x3a92,
|
||||
0xbbe0, 0x32a9, 0x3196, 0x3a9a,
|
||||
0xbbf0, 0x3287, 0x3175, 0x3aa2,
|
||||
0 };
|
||||
|
||||
static const uint16_t bicubic_tex_2048[] = {
|
||||
0xb266, 0x3c00, 0x3aaa, 0x3155,
|
||||
0xb26e, 0x3bfc, 0x3aa8, 0x315d,
|
||||
0xb277, 0x3bf8, 0x3aa6, 0x3165,
|
||||
0xb27f, 0x3bf4, 0x3aa4, 0x316d,
|
||||
0xb287, 0x3bf0, 0x3aa2, 0x3175,
|
||||
0xb290, 0x3bec, 0x3aa0, 0x317d,
|
||||
0xb298, 0x3be8, 0x3a9e, 0x3185,
|
||||
0xb2a1, 0x3be4, 0x3a9c, 0x318e,
|
||||
0xb2a9, 0x3be0, 0x3a9a, 0x3196,
|
||||
0xb2b2, 0x3bdc, 0x3a98, 0x319e,
|
||||
0xb2ba, 0x3bd8, 0x3a96, 0x31a6,
|
||||
0xb2c3, 0x3bd4, 0x3a94, 0x31af,
|
||||
0xb2cc, 0x3bd0, 0x3a92, 0x31b7,
|
||||
0xb2d4, 0x3bcc, 0x3a90, 0x31bf,
|
||||
0xb2dd, 0x3bc8, 0x3a8d, 0x31c8,
|
||||
0xb2e6, 0x3bc4, 0x3a8b, 0x31d0,
|
||||
0xb2ee, 0x3bc0, 0x3a89, 0x31d9,
|
||||
0xb2f7, 0x3bbc, 0x3a87, 0x31e1,
|
||||
0xb300, 0x3bb8, 0x3a85, 0x31ea,
|
||||
0xb309, 0x3bb4, 0x3a83, 0x31f2,
|
||||
0xb312, 0x3bb0, 0x3a81, 0x31fb,
|
||||
0xb31a, 0x3bac, 0x3a7e, 0x3204,
|
||||
0xb323, 0x3ba8, 0x3a7c, 0x320c,
|
||||
0xb32c, 0x3ba4, 0x3a7a, 0x3215,
|
||||
0xb335, 0x3ba0, 0x3a78, 0x321e,
|
||||
0xb33e, 0x3b9c, 0x3a76, 0x3226,
|
||||
0xb347, 0x3b98, 0x3a74, 0x322f,
|
||||
0xb350, 0x3b94, 0x3a71, 0x3238,
|
||||
0xb359, 0x3b90, 0x3a6f, 0x3241,
|
||||
0xb362, 0x3b8c, 0x3a6d, 0x3249,
|
||||
0xb36b, 0x3b88, 0x3a6b, 0x3252,
|
||||
0xb374, 0x3b84, 0x3a69, 0x325b,
|
||||
0xb37d, 0x3b80, 0x3a66, 0x3264,
|
||||
0xb387, 0x3b7c, 0x3a64, 0x326d,
|
||||
0xb390, 0x3b78, 0x3a62, 0x3276,
|
||||
0xb399, 0x3b74, 0x3a60, 0x327f,
|
||||
0xb3a2, 0x3b70, 0x3a5d, 0x3288,
|
||||
0xb3ab, 0x3b6c, 0x3a5b, 0x3291,
|
||||
0xb3b5, 0x3b68, 0x3a59, 0x329a,
|
||||
0xb3be, 0x3b64, 0x3a57, 0x32a3,
|
||||
0xb3c7, 0x3b60, 0x3a54, 0x32ad,
|
||||
0xb3d0, 0x3b5c, 0x3a52, 0x32b6,
|
||||
0xb3da, 0x3b58, 0x3a50, 0x32bf,
|
||||
0xb3e3, 0x3b54, 0x3a4d, 0x32c8,
|
||||
0xb3ed, 0x3b51, 0x3a4b, 0x32d1,
|
||||
0xb3f6, 0x3b4d, 0x3a49, 0x32db,
|
||||
0xb3ff, 0x3b49, 0x3a46, 0x32e4,
|
||||
0xb404, 0x3b45, 0x3a44, 0x32ed,
|
||||
0xb409, 0x3b41, 0x3a42, 0x32f7,
|
||||
0xb40e, 0x3b3d, 0x3a3f, 0x3300,
|
||||
0xb412, 0x3b39, 0x3a3d, 0x3309,
|
||||
0xb417, 0x3b35, 0x3a3b, 0x3313,
|
||||
0xb41c, 0x3b31, 0x3a38, 0x331c,
|
||||
0xb421, 0x3b2d, 0x3a36, 0x3326,
|
||||
0xb426, 0x3b29, 0x3a34, 0x332f,
|
||||
0xb42a, 0x3b25, 0x3a31, 0x3339,
|
||||
0xb42f, 0x3b21, 0x3a2f, 0x3342,
|
||||
0xb434, 0x3b1e, 0x3a2c, 0x334c,
|
||||
0xb439, 0x3b1a, 0x3a2a, 0x3355,
|
||||
0xb43e, 0x3b16, 0x3a28, 0x335f,
|
||||
0xb443, 0x3b12, 0x3a25, 0x3369,
|
||||
0xb448, 0x3b0e, 0x3a23, 0x3372,
|
||||
0xb44d, 0x3b0a, 0x3a20, 0x337c,
|
||||
0xb451, 0x3b06, 0x3a1e, 0x3386,
|
||||
0xb456, 0x3b02, 0x3a1c, 0x3390,
|
||||
0xb45b, 0x3afe, 0x3a19, 0x3399,
|
||||
0xb460, 0x3afb, 0x3a17, 0x33a3,
|
||||
0xb465, 0x3af7, 0x3a14, 0x33ad,
|
||||
0xb46a, 0x3af3, 0x3a12, 0x33b7,
|
||||
0xb46f, 0x3aef, 0x3a0f, 0x33c1,
|
||||
0xb474, 0x3aeb, 0x3a0d, 0x33ca,
|
||||
0xb479, 0x3ae7, 0x3a0a, 0x33d4,
|
||||
0xb47e, 0x3ae3, 0x3a08, 0x33de,
|
||||
0xb483, 0x3ae0, 0x3a05, 0x33e8,
|
||||
0xb488, 0x3adc, 0x3a03, 0x33f2,
|
||||
0xb48d, 0x3ad8, 0x3a00, 0x33fc,
|
||||
0xb492, 0x3ad4, 0x39fe, 0x3403,
|
||||
0xb497, 0x3ad0, 0x39fb, 0x3408,
|
||||
0xb49c, 0x3acc, 0x39f9, 0x340d,
|
||||
0xb4a1, 0x3ac8, 0x39f6, 0x3412,
|
||||
0xb4a6, 0x3ac5, 0x39f4, 0x3417,
|
||||
0xb4ac, 0x3ac1, 0x39f1, 0x341c,
|
||||
0xb4b1, 0x3abd, 0x39ef, 0x3421,
|
||||
0xb4b6, 0x3ab9, 0x39ec, 0x3426,
|
||||
0xb4bb, 0x3ab5, 0x39ea, 0x342b,
|
||||
0xb4c0, 0x3ab1, 0x39e7, 0x3430,
|
||||
0xb4c5, 0x3aae, 0x39e5, 0x3435,
|
||||
0xb4ca, 0x3aaa, 0x39e2, 0x343b,
|
||||
0xb4cf, 0x3aa6, 0x39df, 0x3440,
|
||||
0xb4d5, 0x3aa2, 0x39dd, 0x3445,
|
||||
0xb4da, 0x3a9e, 0x39da, 0x344a,
|
||||
0xb4df, 0x3a9b, 0x39d8, 0x344f,
|
||||
0xb4e4, 0x3a97, 0x39d5, 0x3454,
|
||||
0xb4e9, 0x3a93, 0x39d2, 0x345a,
|
||||
0xb4ef, 0x3a8f, 0x39d0, 0x345f,
|
||||
0xb4f4, 0x3a8b, 0x39cd, 0x3464,
|
||||
0xb4f9, 0x3a88, 0x39cb, 0x3469,
|
||||
0xb4fe, 0x3a84, 0x39c8, 0x346e,
|
||||
0xb504, 0x3a80, 0x39c5, 0x3474,
|
||||
0xb509, 0x3a7c, 0x39c3, 0x3479,
|
||||
0xb50e, 0x3a79, 0x39c0, 0x347e,
|
||||
0xb513, 0x3a75, 0x39be, 0x3483,
|
||||
0xb519, 0x3a71, 0x39bb, 0x3489,
|
||||
0xb51e, 0x3a6d, 0x39b8, 0x348e,
|
||||
0xb523, 0x3a6a, 0x39b6, 0x3493,
|
||||
0xb529, 0x3a66, 0x39b3, 0x3499,
|
||||
0xb52e, 0x3a62, 0x39b0, 0x349e,
|
||||
0xb533, 0x3a5e, 0x39ae, 0x34a3,
|
||||
0xb539, 0x3a5a, 0x39ab, 0x34a8,
|
||||
0xb53e, 0x3a57, 0x39a8, 0x34ae,
|
||||
0xb543, 0x3a53, 0x39a6, 0x34b3,
|
||||
0xb549, 0x3a4f, 0x39a3, 0x34b9,
|
||||
0xb54e, 0x3a4c, 0x39a0, 0x34be,
|
||||
0xb554, 0x3a48, 0x399e, 0x34c3,
|
||||
0xb559, 0x3a44, 0x399b, 0x34c9,
|
||||
0xb55e, 0x3a40, 0x3998, 0x34ce,
|
||||
0xb564, 0x3a3d, 0x3996, 0x34d3,
|
||||
0xb569, 0x3a39, 0x3993, 0x34d9,
|
||||
0xb56f, 0x3a35, 0x3990, 0x34de,
|
||||
0xb574, 0x3a32, 0x398d, 0x34e4,
|
||||
0xb57a, 0x3a2e, 0x398b, 0x34e9,
|
||||
0xb57f, 0x3a2a, 0x3988, 0x34ef,
|
||||
0xb585, 0x3a26, 0x3985, 0x34f4,
|
||||
0xb58a, 0x3a23, 0x3983, 0x34f9,
|
||||
0xb590, 0x3a1f, 0x3980, 0x34ff,
|
||||
0xb595, 0x3a1b, 0x397d, 0x3504,
|
||||
0xb59b, 0x3a18, 0x397a, 0x350a,
|
||||
0xb5a0, 0x3a14, 0x3978, 0x350f,
|
||||
0xb5a6, 0x3a10, 0x3975, 0x3515,
|
||||
0xb5ab, 0x3a0d, 0x3972, 0x351a,
|
||||
0xb5b1, 0x3a09, 0x396f, 0x3520,
|
||||
0xb5b6, 0x3a05, 0x396d, 0x3525,
|
||||
0xb5bc, 0x3a02, 0x396a, 0x352b,
|
||||
0xb5c1, 0x39fe, 0x3967, 0x3530,
|
||||
0xb5c7, 0x39fa, 0x3964, 0x3536,
|
||||
0xb5cd, 0x39f7, 0x3961, 0x353c,
|
||||
0xb5d2, 0x39f3, 0x395f, 0x3541,
|
||||
0xb5d8, 0x39ef, 0x395c, 0x3547,
|
||||
0xb5dd, 0x39ec, 0x3959, 0x354c,
|
||||
0xb5e3, 0x39e8, 0x3956, 0x3552,
|
||||
0xb5e9, 0x39e4, 0x3954, 0x3557,
|
||||
0xb5ee, 0x39e1, 0x3951, 0x355d,
|
||||
0xb5f4, 0x39dd, 0x394e, 0x3563,
|
||||
0xb5fa, 0x39d9, 0x394b, 0x3568,
|
||||
0xb5ff, 0x39d6, 0x3948, 0x356e,
|
||||
0xb605, 0x39d2, 0x3946, 0x3573,
|
||||
0xb60b, 0x39cf, 0x3943, 0x3579,
|
||||
0xb610, 0x39cb, 0x3940, 0x357f,
|
||||
0xb616, 0x39c7, 0x393d, 0x3584,
|
||||
0xb61c, 0x39c4, 0x393a, 0x358a,
|
||||
0xb621, 0x39c0, 0x3937, 0x3590,
|
||||
0xb627, 0x39bd, 0x3935, 0x3595,
|
||||
0xb62d, 0x39b9, 0x3932, 0x359b,
|
||||
0xb633, 0x39b5, 0x392f, 0x35a1,
|
||||
0xb638, 0x39b2, 0x392c, 0x35a6,
|
||||
0xb63e, 0x39ae, 0x3929, 0x35ac,
|
||||
0xb644, 0x39ab, 0x3926, 0x35b2,
|
||||
0xb64a, 0x39a7, 0x3924, 0x35b7,
|
||||
0xb64f, 0x39a3, 0x3921, 0x35bd,
|
||||
0xb655, 0x39a0, 0x391e, 0x35c3,
|
||||
0xb65b, 0x399c, 0x391b, 0x35c9,
|
||||
0xb661, 0x3999, 0x3918, 0x35ce,
|
||||
0xb667, 0x3995, 0x3915, 0x35d4,
|
||||
0xb66c, 0x3992, 0x3912, 0x35da,
|
||||
0xb672, 0x398e, 0x3910, 0x35df,
|
||||
0xb678, 0x398a, 0x390d, 0x35e5,
|
||||
0xb67e, 0x3987, 0x390a, 0x35eb,
|
||||
0xb684, 0x3983, 0x3907, 0x35f1,
|
||||
0xb68a, 0x3980, 0x3904, 0x35f6,
|
||||
0xb68f, 0x397c, 0x3901, 0x35fc,
|
||||
0xb695, 0x3979, 0x38fe, 0x3602,
|
||||
0xb69b, 0x3975, 0x38fb, 0x3608,
|
||||
0xb6a1, 0x3972, 0x38f8, 0x360e,
|
||||
0xb6a7, 0x396e, 0x38f6, 0x3613,
|
||||
0xb6ad, 0x396b, 0x38f3, 0x3619,
|
||||
0xb6b3, 0x3967, 0x38f0, 0x361f,
|
||||
0xb6b9, 0x3964, 0x38ed, 0x3625,
|
||||
0xb6bf, 0x3960, 0x38ea, 0x362b,
|
||||
0xb6c5, 0x395d, 0x38e7, 0x3630,
|
||||
0xb6cb, 0x3959, 0x38e4, 0x3636,
|
||||
0xb6d1, 0x3956, 0x38e1, 0x363c,
|
||||
0xb6d6, 0x3952, 0x38de, 0x3642,
|
||||
0xb6dc, 0x394f, 0x38db, 0x3648,
|
||||
0xb6e2, 0x394b, 0x38d9, 0x364d,
|
||||
0xb6e8, 0x3948, 0x38d6, 0x3653,
|
||||
0xb6ee, 0x3944, 0x38d3, 0x3659,
|
||||
0xb6f4, 0x3941, 0x38d0, 0x365f,
|
||||
0xb6fa, 0x393d, 0x38cd, 0x3665,
|
||||
0xb700, 0x393a, 0x38ca, 0x366b,
|
||||
0xb706, 0x3936, 0x38c7, 0x3671,
|
||||
0xb70c, 0x3933, 0x38c4, 0x3676,
|
||||
0xb712, 0x392f, 0x38c1, 0x367c,
|
||||
0xb719, 0x392c, 0x38be, 0x3682,
|
||||
0xb71f, 0x3928, 0x38bb, 0x3688,
|
||||
0xb725, 0x3925, 0x38b8, 0x368e,
|
||||
0xb72b, 0x3921, 0x38b5, 0x3694,
|
||||
0xb731, 0x391e, 0x38b2, 0x369a,
|
||||
0xb737, 0x391a, 0x38af, 0x36a0,
|
||||
0xb73d, 0x3917, 0x38ad, 0x36a5,
|
||||
0xb743, 0x3914, 0x38aa, 0x36ab,
|
||||
0xb749, 0x3910, 0x38a7, 0x36b1,
|
||||
0xb74f, 0x390d, 0x38a4, 0x36b7,
|
||||
0xb755, 0x3909, 0x38a1, 0x36bd,
|
||||
0xb75b, 0x3906, 0x389e, 0x36c3,
|
||||
0xb762, 0x3902, 0x389b, 0x36c9,
|
||||
0xb768, 0x38ff, 0x3898, 0x36cf,
|
||||
0xb76e, 0x38fc, 0x3895, 0x36d5,
|
||||
0xb774, 0x38f8, 0x3892, 0x36db,
|
||||
0xb77a, 0x38f5, 0x388f, 0x36e1,
|
||||
0xb780, 0x38f1, 0x388c, 0x36e7,
|
||||
0xb787, 0x38ee, 0x3889, 0x36ec,
|
||||
0xb78d, 0x38eb, 0x3886, 0x36f2,
|
||||
0xb793, 0x38e7, 0x3883, 0x36f8,
|
||||
0xb799, 0x38e4, 0x3880, 0x36fe,
|
||||
0xb79f, 0x38e0, 0x387d, 0x3704,
|
||||
0xb7a5, 0x38dd, 0x387a, 0x370a,
|
||||
0xb7ac, 0x38da, 0x3877, 0x3710,
|
||||
0xb7b2, 0x38d6, 0x3874, 0x3716,
|
||||
0xb7b8, 0x38d3, 0x3871, 0x371c,
|
||||
0xb7be, 0x38cf, 0x386e, 0x3722,
|
||||
0xb7c5, 0x38cc, 0x386b, 0x3728,
|
||||
0xb7cb, 0x38c9, 0x3868, 0x372e,
|
||||
0xb7d1, 0x38c5, 0x3865, 0x3734,
|
||||
0xb7d7, 0x38c2, 0x3862, 0x373a,
|
||||
0xb7de, 0x38bf, 0x385f, 0x3740,
|
||||
0xb7e4, 0x38bb, 0x385c, 0x3746,
|
||||
0xb7ea, 0x38b8, 0x3859, 0x374c,
|
||||
0xb7f1, 0x38b5, 0x3856, 0x3752,
|
||||
0xb7f7, 0x38b1, 0x3853, 0x3758,
|
||||
0xb7fd, 0x38ae, 0x3850, 0x375e,
|
||||
0xb801, 0x38aa, 0x384d, 0x3764,
|
||||
0xb805, 0x38a7, 0x384a, 0x376a,
|
||||
0xb808, 0x38a4, 0x3847, 0x3770,
|
||||
0xb80b, 0x38a0, 0x3844, 0x3776,
|
||||
0xb80e, 0x389d, 0x3841, 0x377c,
|
||||
0xb811, 0x389a, 0x383e, 0x3782,
|
||||
0xb815, 0x3897, 0x383b, 0x3788,
|
||||
0xb818, 0x3893, 0x3838, 0x378e,
|
||||
0xb81b, 0x3890, 0x3835, 0x3794,
|
||||
0xb81e, 0x388d, 0x3832, 0x379a,
|
||||
0xb821, 0x3889, 0x382f, 0x37a0,
|
||||
0xb824, 0x3886, 0x382c, 0x37a6,
|
||||
0xb828, 0x3883, 0x3829, 0x37ac,
|
||||
0xb82b, 0x387f, 0x3826, 0x37b2,
|
||||
0xb82e, 0x387c, 0x3823, 0x37b8,
|
||||
0xb831, 0x3879, 0x3820, 0x37be,
|
||||
0xb835, 0x3876, 0x381d, 0x37c4,
|
||||
0xb838, 0x3872, 0x381a, 0x37ca,
|
||||
0xb83b, 0x386f, 0x3817, 0x37d0,
|
||||
0xb83e, 0x386c, 0x3814, 0x37d6,
|
||||
0xb841, 0x3868, 0x3811, 0x37dc,
|
||||
0xb845, 0x3865, 0x380e, 0x37e2,
|
||||
0xb848, 0x3862, 0x380b, 0x37e8,
|
||||
0xb84b, 0x385f, 0x3808, 0x37ee,
|
||||
0xb84e, 0x385b, 0x3806, 0x37f4,
|
||||
0xb852, 0x3858, 0x3803, 0x37fa,
|
||||
0xb855, 0x3855, 0x3800, 0x3800,
|
||||
0xb858, 0x3852, 0x37fa, 0x3803,
|
||||
0xb85b, 0x384e, 0x37f4, 0x3806,
|
||||
0xb85f, 0x384b, 0x37ee, 0x3808,
|
||||
0xb862, 0x3848, 0x37e8, 0x380b,
|
||||
0xb865, 0x3845, 0x37e2, 0x380e,
|
||||
0xb868, 0x3841, 0x37dc, 0x3811,
|
||||
0xb86c, 0x383e, 0x37d6, 0x3814,
|
||||
0xb86f, 0x383b, 0x37d0, 0x3817,
|
||||
0xb872, 0x3838, 0x37ca, 0x381a,
|
||||
0xb876, 0x3835, 0x37c4, 0x381d,
|
||||
0xb879, 0x3831, 0x37be, 0x3820,
|
||||
0xb87c, 0x382e, 0x37b8, 0x3823,
|
||||
0xb87f, 0x382b, 0x37b2, 0x3826,
|
||||
0xb883, 0x3828, 0x37ac, 0x3829,
|
||||
0xb886, 0x3824, 0x37a6, 0x382c,
|
||||
0xb889, 0x3821, 0x37a0, 0x382f,
|
||||
0xb88d, 0x381e, 0x379a, 0x3832,
|
||||
0xb890, 0x381b, 0x3794, 0x3835,
|
||||
0xb893, 0x3818, 0x378e, 0x3838,
|
||||
0xb897, 0x3815, 0x3788, 0x383b,
|
||||
0xb89a, 0x3811, 0x3782, 0x383e,
|
||||
0xb89d, 0x380e, 0x377c, 0x3841,
|
||||
0xb8a0, 0x380b, 0x3776, 0x3844,
|
||||
0xb8a4, 0x3808, 0x3770, 0x3847,
|
||||
0xb8a7, 0x3805, 0x376a, 0x384a,
|
||||
0xb8aa, 0x3801, 0x3764, 0x384d,
|
||||
0xb8ae, 0x37fd, 0x375e, 0x3850,
|
||||
0xb8b1, 0x37f7, 0x3758, 0x3853,
|
||||
0xb8b5, 0x37f1, 0x3752, 0x3856,
|
||||
0xb8b8, 0x37ea, 0x374c, 0x3859,
|
||||
0xb8bb, 0x37e4, 0x3746, 0x385c,
|
||||
0xb8bf, 0x37de, 0x3740, 0x385f,
|
||||
0xb8c2, 0x37d7, 0x373a, 0x3862,
|
||||
0xb8c5, 0x37d1, 0x3734, 0x3865,
|
||||
0xb8c9, 0x37cb, 0x372e, 0x3868,
|
||||
0xb8cc, 0x37c5, 0x3728, 0x386b,
|
||||
0xb8cf, 0x37be, 0x3722, 0x386e,
|
||||
0xb8d3, 0x37b8, 0x371c, 0x3871,
|
||||
0xb8d6, 0x37b2, 0x3716, 0x3874,
|
||||
0xb8da, 0x37ac, 0x3710, 0x3877,
|
||||
0xb8dd, 0x37a5, 0x370a, 0x387a,
|
||||
0xb8e0, 0x379f, 0x3704, 0x387d,
|
||||
0xb8e4, 0x3799, 0x36fe, 0x3880,
|
||||
0xb8e7, 0x3793, 0x36f8, 0x3883,
|
||||
0xb8eb, 0x378d, 0x36f2, 0x3886,
|
||||
0xb8ee, 0x3787, 0x36ec, 0x3889,
|
||||
0xb8f1, 0x3780, 0x36e7, 0x388c,
|
||||
0xb8f5, 0x377a, 0x36e1, 0x388f,
|
||||
0xb8f8, 0x3774, 0x36db, 0x3892,
|
||||
0xb8fc, 0x376e, 0x36d5, 0x3895,
|
||||
0xb8ff, 0x3768, 0x36cf, 0x3898,
|
||||
0xb902, 0x3762, 0x36c9, 0x389b,
|
||||
0xb906, 0x375b, 0x36c3, 0x389e,
|
||||
0xb909, 0x3755, 0x36bd, 0x38a1,
|
||||
0xb90d, 0x374f, 0x36b7, 0x38a4,
|
||||
0xb910, 0x3749, 0x36b1, 0x38a7,
|
||||
0xb914, 0x3743, 0x36ab, 0x38aa,
|
||||
0xb917, 0x373d, 0x36a5, 0x38ad,
|
||||
0xb91a, 0x3737, 0x36a0, 0x38af,
|
||||
0xb91e, 0x3731, 0x369a, 0x38b2,
|
||||
0xb921, 0x372b, 0x3694, 0x38b5,
|
||||
0xb925, 0x3725, 0x368e, 0x38b8,
|
||||
0xb928, 0x371f, 0x3688, 0x38bb,
|
||||
0xb92c, 0x3719, 0x3682, 0x38be,
|
||||
0xb92f, 0x3712, 0x367c, 0x38c1,
|
||||
0xb933, 0x370c, 0x3676, 0x38c4,
|
||||
0xb936, 0x3706, 0x3671, 0x38c7,
|
||||
0xb93a, 0x3700, 0x366b, 0x38ca,
|
||||
0xb93d, 0x36fa, 0x3665, 0x38cd,
|
||||
0xb941, 0x36f4, 0x365f, 0x38d0,
|
||||
0xb944, 0x36ee, 0x3659, 0x38d3,
|
||||
0xb948, 0x36e8, 0x3653, 0x38d6,
|
||||
0xb94b, 0x36e2, 0x364d, 0x38d9,
|
||||
0xb94f, 0x36dc, 0x3648, 0x38db,
|
||||
0xb952, 0x36d6, 0x3642, 0x38de,
|
||||
0xb956, 0x36d1, 0x363c, 0x38e1,
|
||||
0xb959, 0x36cb, 0x3636, 0x38e4,
|
||||
0xb95d, 0x36c5, 0x3630, 0x38e7,
|
||||
0xb960, 0x36bf, 0x362b, 0x38ea,
|
||||
0xb964, 0x36b9, 0x3625, 0x38ed,
|
||||
0xb967, 0x36b3, 0x361f, 0x38f0,
|
||||
0xb96b, 0x36ad, 0x3619, 0x38f3,
|
||||
0xb96e, 0x36a7, 0x3613, 0x38f6,
|
||||
0xb972, 0x36a1, 0x360e, 0x38f8,
|
||||
0xb975, 0x369b, 0x3608, 0x38fb,
|
||||
0xb979, 0x3695, 0x3602, 0x38fe,
|
||||
0xb97c, 0x368f, 0x35fc, 0x3901,
|
||||
0xb980, 0x368a, 0x35f6, 0x3904,
|
||||
0xb983, 0x3684, 0x35f1, 0x3907,
|
||||
0xb987, 0x367e, 0x35eb, 0x390a,
|
||||
0xb98a, 0x3678, 0x35e5, 0x390d,
|
||||
0xb98e, 0x3672, 0x35df, 0x3910,
|
||||
0xb992, 0x366c, 0x35da, 0x3912,
|
||||
0xb995, 0x3667, 0x35d4, 0x3915,
|
||||
0xb999, 0x3661, 0x35ce, 0x3918,
|
||||
0xb99c, 0x365b, 0x35c9, 0x391b,
|
||||
0xb9a0, 0x3655, 0x35c3, 0x391e,
|
||||
0xb9a3, 0x364f, 0x35bd, 0x3921,
|
||||
0xb9a7, 0x364a, 0x35b7, 0x3924,
|
||||
0xb9ab, 0x3644, 0x35b2, 0x3926,
|
||||
0xb9ae, 0x363e, 0x35ac, 0x3929,
|
||||
0xb9b2, 0x3638, 0x35a6, 0x392c,
|
||||
0xb9b5, 0x3633, 0x35a1, 0x392f,
|
||||
0xb9b9, 0x362d, 0x359b, 0x3932,
|
||||
0xb9bd, 0x3627, 0x3595, 0x3935,
|
||||
0xb9c0, 0x3621, 0x3590, 0x3937,
|
||||
0xb9c4, 0x361c, 0x358a, 0x393a,
|
||||
0xb9c7, 0x3616, 0x3584, 0x393d,
|
||||
0xb9cb, 0x3610, 0x357f, 0x3940,
|
||||
0xb9cf, 0x360b, 0x3579, 0x3943,
|
||||
0xb9d2, 0x3605, 0x3573, 0x3946,
|
||||
0xb9d6, 0x35ff, 0x356e, 0x3948,
|
||||
0xb9d9, 0x35fa, 0x3568, 0x394b,
|
||||
0xb9dd, 0x35f4, 0x3563, 0x394e,
|
||||
0xb9e1, 0x35ee, 0x355d, 0x3951,
|
||||
0xb9e4, 0x35e9, 0x3557, 0x3954,
|
||||
0xb9e8, 0x35e3, 0x3552, 0x3956,
|
||||
0xb9ec, 0x35dd, 0x354c, 0x3959,
|
||||
0xb9ef, 0x35d8, 0x3547, 0x395c,
|
||||
0xb9f3, 0x35d2, 0x3541, 0x395f,
|
||||
0xb9f7, 0x35cd, 0x353c, 0x3961,
|
||||
0xb9fa, 0x35c7, 0x3536, 0x3964,
|
||||
0xb9fe, 0x35c1, 0x3530, 0x3967,
|
||||
0xba02, 0x35bc, 0x352b, 0x396a,
|
||||
0xba05, 0x35b6, 0x3525, 0x396d,
|
||||
0xba09, 0x35b1, 0x3520, 0x396f,
|
||||
0xba0d, 0x35ab, 0x351a, 0x3972,
|
||||
0xba10, 0x35a6, 0x3515, 0x3975,
|
||||
0xba14, 0x35a0, 0x350f, 0x3978,
|
||||
0xba18, 0x359b, 0x350a, 0x397a,
|
||||
0xba1b, 0x3595, 0x3504, 0x397d,
|
||||
0xba1f, 0x3590, 0x34ff, 0x3980,
|
||||
0xba23, 0x358a, 0x34f9, 0x3983,
|
||||
0xba26, 0x3585, 0x34f4, 0x3985,
|
||||
0xba2a, 0x357f, 0x34ef, 0x3988,
|
||||
0xba2e, 0x357a, 0x34e9, 0x398b,
|
||||
0xba32, 0x3574, 0x34e4, 0x398d,
|
||||
0xba35, 0x356f, 0x34de, 0x3990,
|
||||
0xba39, 0x3569, 0x34d9, 0x3993,
|
||||
0xba3d, 0x3564, 0x34d3, 0x3996,
|
||||
0xba40, 0x355e, 0x34ce, 0x3998,
|
||||
0xba44, 0x3559, 0x34c9, 0x399b,
|
||||
0xba48, 0x3554, 0x34c3, 0x399e,
|
||||
0xba4c, 0x354e, 0x34be, 0x39a0,
|
||||
0xba4f, 0x3549, 0x34b9, 0x39a3,
|
||||
0xba53, 0x3543, 0x34b3, 0x39a6,
|
||||
0xba57, 0x353e, 0x34ae, 0x39a8,
|
||||
0xba5a, 0x3539, 0x34a8, 0x39ab,
|
||||
0xba5e, 0x3533, 0x34a3, 0x39ae,
|
||||
0xba62, 0x352e, 0x349e, 0x39b0,
|
||||
0xba66, 0x3529, 0x3499, 0x39b3,
|
||||
0xba6a, 0x3523, 0x3493, 0x39b6,
|
||||
0xba6d, 0x351e, 0x348e, 0x39b8,
|
||||
0xba71, 0x3519, 0x3489, 0x39bb,
|
||||
0xba75, 0x3513, 0x3483, 0x39be,
|
||||
0xba79, 0x350e, 0x347e, 0x39c0,
|
||||
0xba7c, 0x3509, 0x3479, 0x39c3,
|
||||
0xba80, 0x3504, 0x3474, 0x39c5,
|
||||
0xba84, 0x34fe, 0x346e, 0x39c8,
|
||||
0xba88, 0x34f9, 0x3469, 0x39cb,
|
||||
0xba8b, 0x34f4, 0x3464, 0x39cd,
|
||||
0xba8f, 0x34ef, 0x345f, 0x39d0,
|
||||
0xba93, 0x34e9, 0x345a, 0x39d2,
|
||||
0xba97, 0x34e4, 0x3454, 0x39d5,
|
||||
0xba9b, 0x34df, 0x344f, 0x39d8,
|
||||
0xba9e, 0x34da, 0x344a, 0x39da,
|
||||
0xbaa2, 0x34d5, 0x3445, 0x39dd,
|
||||
0xbaa6, 0x34cf, 0x3440, 0x39df,
|
||||
0xbaaa, 0x34ca, 0x343b, 0x39e2,
|
||||
0xbaae, 0x34c5, 0x3435, 0x39e5,
|
||||
0xbab1, 0x34c0, 0x3430, 0x39e7,
|
||||
0xbab5, 0x34bb, 0x342b, 0x39ea,
|
||||
0xbab9, 0x34b6, 0x3426, 0x39ec,
|
||||
0xbabd, 0x34b1, 0x3421, 0x39ef,
|
||||
0xbac1, 0x34ac, 0x341c, 0x39f1,
|
||||
0xbac5, 0x34a6, 0x3417, 0x39f4,
|
||||
0xbac8, 0x34a1, 0x3412, 0x39f6,
|
||||
0xbacc, 0x349c, 0x340d, 0x39f9,
|
||||
0xbad0, 0x3497, 0x3408, 0x39fb,
|
||||
0xbad4, 0x3492, 0x3403, 0x39fe,
|
||||
0xbad8, 0x348d, 0x33fc, 0x3a00,
|
||||
0xbadc, 0x3488, 0x33f2, 0x3a03,
|
||||
0xbae0, 0x3483, 0x33e8, 0x3a05,
|
||||
0xbae3, 0x347e, 0x33de, 0x3a08,
|
||||
0xbae7, 0x3479, 0x33d4, 0x3a0a,
|
||||
0xbaeb, 0x3474, 0x33ca, 0x3a0d,
|
||||
0xbaef, 0x346f, 0x33c1, 0x3a0f,
|
||||
0xbaf3, 0x346a, 0x33b7, 0x3a12,
|
||||
0xbaf7, 0x3465, 0x33ad, 0x3a14,
|
||||
0xbafb, 0x3460, 0x33a3, 0x3a17,
|
||||
0xbafe, 0x345b, 0x3399, 0x3a19,
|
||||
0xbb02, 0x3456, 0x3390, 0x3a1c,
|
||||
0xbb06, 0x3451, 0x3386, 0x3a1e,
|
||||
0xbb0a, 0x344d, 0x337c, 0x3a20,
|
||||
0xbb0e, 0x3448, 0x3372, 0x3a23,
|
||||
0xbb12, 0x3443, 0x3369, 0x3a25,
|
||||
0xbb16, 0x343e, 0x335f, 0x3a28,
|
||||
0xbb1a, 0x3439, 0x3355, 0x3a2a,
|
||||
0xbb1e, 0x3434, 0x334c, 0x3a2c,
|
||||
0xbb21, 0x342f, 0x3342, 0x3a2f,
|
||||
0xbb25, 0x342a, 0x3339, 0x3a31,
|
||||
0xbb29, 0x3426, 0x332f, 0x3a34,
|
||||
0xbb2d, 0x3421, 0x3326, 0x3a36,
|
||||
0xbb31, 0x341c, 0x331c, 0x3a38,
|
||||
0xbb35, 0x3417, 0x3313, 0x3a3b,
|
||||
0xbb39, 0x3412, 0x3309, 0x3a3d,
|
||||
0xbb3d, 0x340e, 0x3300, 0x3a3f,
|
||||
0xbb41, 0x3409, 0x32f7, 0x3a42,
|
||||
0xbb45, 0x3404, 0x32ed, 0x3a44,
|
||||
0xbb49, 0x33ff, 0x32e4, 0x3a46,
|
||||
0xbb4d, 0x33f6, 0x32db, 0x3a49,
|
||||
0xbb51, 0x33ed, 0x32d1, 0x3a4b,
|
||||
0xbb54, 0x33e3, 0x32c8, 0x3a4d,
|
||||
0xbb58, 0x33da, 0x32bf, 0x3a50,
|
||||
0xbb5c, 0x33d0, 0x32b6, 0x3a52,
|
||||
0xbb60, 0x33c7, 0x32ad, 0x3a54,
|
||||
0xbb64, 0x33be, 0x32a3, 0x3a57,
|
||||
0xbb68, 0x33b5, 0x329a, 0x3a59,
|
||||
0xbb6c, 0x33ab, 0x3291, 0x3a5b,
|
||||
0xbb70, 0x33a2, 0x3288, 0x3a5d,
|
||||
0xbb74, 0x3399, 0x327f, 0x3a60,
|
||||
0xbb78, 0x3390, 0x3276, 0x3a62,
|
||||
0xbb7c, 0x3387, 0x326d, 0x3a64,
|
||||
0xbb80, 0x337d, 0x3264, 0x3a66,
|
||||
0xbb84, 0x3374, 0x325b, 0x3a69,
|
||||
0xbb88, 0x336b, 0x3252, 0x3a6b,
|
||||
0xbb8c, 0x3362, 0x3249, 0x3a6d,
|
||||
0xbb90, 0x3359, 0x3241, 0x3a6f,
|
||||
0xbb94, 0x3350, 0x3238, 0x3a71,
|
||||
0xbb98, 0x3347, 0x322f, 0x3a74,
|
||||
0xbb9c, 0x333e, 0x3226, 0x3a76,
|
||||
0xbba0, 0x3335, 0x321e, 0x3a78,
|
||||
0xbba4, 0x332c, 0x3215, 0x3a7a,
|
||||
0xbba8, 0x3323, 0x320c, 0x3a7c,
|
||||
0xbbac, 0x331a, 0x3204, 0x3a7e,
|
||||
0xbbb0, 0x3312, 0x31fb, 0x3a81,
|
||||
0xbbb4, 0x3309, 0x31f2, 0x3a83,
|
||||
0xbbb8, 0x3300, 0x31ea, 0x3a85,
|
||||
0xbbbc, 0x32f7, 0x31e1, 0x3a87,
|
||||
0xbbc0, 0x32ee, 0x31d9, 0x3a89,
|
||||
0xbbc4, 0x32e6, 0x31d0, 0x3a8b,
|
||||
0xbbc8, 0x32dd, 0x31c8, 0x3a8d,
|
||||
0xbbcc, 0x32d4, 0x31bf, 0x3a90,
|
||||
0xbbd0, 0x32cc, 0x31b7, 0x3a92,
|
||||
0xbbd4, 0x32c3, 0x31af, 0x3a94,
|
||||
0xbbd8, 0x32ba, 0x31a6, 0x3a96,
|
||||
0xbbdc, 0x32b2, 0x319e, 0x3a98,
|
||||
0xbbe0, 0x32a9, 0x3196, 0x3a9a,
|
||||
0xbbe4, 0x32a1, 0x318e, 0x3a9c,
|
||||
0xbbe8, 0x3298, 0x3185, 0x3a9e,
|
||||
0xbbec, 0x3290, 0x317d, 0x3aa0,
|
||||
0xbbf0, 0x3287, 0x3175, 0x3aa2,
|
||||
0xbbf4, 0x327f, 0x316d, 0x3aa4,
|
||||
0xbbf8, 0x3277, 0x3165, 0x3aa6,
|
||||
0xbbfc, 0x326e, 0x315d, 0x3aa8,
|
||||
0 };
|
||||
|
||||
72
src/bicubic_table.py
Executable file
72
src/bicubic_table.py
Executable file
|
|
@ -0,0 +1,72 @@
|
|||
#!/usr/bin/python
|
||||
|
||||
import struct
|
||||
|
||||
def half(i):
|
||||
fs, fe, fm = ((i >> 31) & 0x1, (i >> 23) & 0xff, i & 0x7fffff)
|
||||
s, e, m = (fs, 0, 0)
|
||||
|
||||
if (fe == 0x0):
|
||||
pass
|
||||
if ((fe == 0xff) and (fm == 0x0)):
|
||||
e = 31
|
||||
elif (fe == 0xff):
|
||||
m = 1
|
||||
e = 31
|
||||
else:
|
||||
exp = fe - 127;
|
||||
if (exp < -24):
|
||||
pass
|
||||
elif (exp < -14):
|
||||
temp = 10 - (-14 - exp)
|
||||
m = 2**temp + (m >> (23 - temp))
|
||||
elif (exp > 15):
|
||||
e = 31
|
||||
else:
|
||||
e = exp + 15
|
||||
m = fm >> 13
|
||||
|
||||
return ((s << 15) | (e << 10) | m)
|
||||
|
||||
def texgen(pix):
|
||||
|
||||
tex = []
|
||||
|
||||
for i in range(0,pix,4):
|
||||
|
||||
a = i / float(pix)
|
||||
a2 = a ** 2
|
||||
a3 = a ** 3
|
||||
|
||||
w0 = 1 / 6.0 * (-a3 + 3 * a2 + -3 * a + 1)
|
||||
w1 = 1 / 6.0 * (3 * a3 + -6 * a2 + 4)
|
||||
w2 = 1 / 6.0 * (-3 * a3 + 3 * a2 + 3 * a + 1)
|
||||
w3 = 1 / 6.0 * a3
|
||||
|
||||
tex.append(-(1 - (w1 / (w0 + w1)) + a))
|
||||
tex.append(1 + (w3 / (w2 + w3)) - a)
|
||||
tex.append(w0 + w1)
|
||||
tex.append(w2 + w3)
|
||||
|
||||
return tex
|
||||
|
||||
def printrow(l, offset):
|
||||
|
||||
seq = [ struct.unpack('<I',struct.pack('f',i))[0] for i in l[offset:offset+4] ]
|
||||
seq = [ hex(half(i)) for i in seq ]
|
||||
return "\t" + ", ".join(seq) + ","
|
||||
|
||||
def maketable(pix):
|
||||
|
||||
l = texgen(pix)
|
||||
|
||||
print "static const uint16_t bicubic_tex_" + str(pix) + "[] = {"
|
||||
|
||||
for i in range(0, pix, 4):
|
||||
|
||||
print printrow(l, i)
|
||||
|
||||
print "\t0 };\n"
|
||||
|
||||
maketable(512)
|
||||
maketable(2048)
|
||||
301
src/cayman_accel.c
Normal file
301
src/cayman_accel.c
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors: Alex Deucher <alexander.deucher@amd.com>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "cayman_reg.h"
|
||||
#include "evergreen_state.h"
|
||||
|
||||
#include "radeon_vbo.h"
|
||||
#include "radeon_exa_shared.h"
|
||||
|
||||
/*
|
||||
* Setup of default state
|
||||
*/
|
||||
|
||||
void
|
||||
cayman_set_default_state(ScrnInfoPtr pScrn)
|
||||
{
|
||||
tex_resource_t tex_res;
|
||||
shader_config_t fs_conf;
|
||||
int i;
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
if (accel_state->XInited3D)
|
||||
return;
|
||||
|
||||
memset(&tex_res, 0, sizeof(tex_resource_t));
|
||||
memset(&fs_conf, 0, sizeof(shader_config_t));
|
||||
|
||||
accel_state->XInited3D = TRUE;
|
||||
|
||||
evergreen_start_3d(pScrn);
|
||||
|
||||
BEGIN_BATCH(21);
|
||||
EREG(SQ_LDS_ALLOC_PS, 0);
|
||||
|
||||
PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
PACK0(SQ_GS_VERT_ITEMSIZE, 4);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
PACK0(SQ_VTX_BASE_VTX_LOC, 2);
|
||||
E32(0);
|
||||
E32(0);
|
||||
END_BATCH();
|
||||
|
||||
/* DB */
|
||||
BEGIN_BATCH(3 + 2);
|
||||
EREG(DB_Z_INFO, 0);
|
||||
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH(3 + 2);
|
||||
EREG(DB_STENCIL_INFO, 0);
|
||||
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH(3 + 2);
|
||||
EREG(DB_HTILE_DATA_BASE, 0);
|
||||
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH(52);
|
||||
EREG(DB_DEPTH_INFO, 0);
|
||||
EREG(DB_DEPTH_CONTROL, 0);
|
||||
|
||||
PACK0(PA_SC_VPORT_ZMIN_0, 2);
|
||||
EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
|
||||
EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
|
||||
|
||||
PACK0(DB_RENDER_CONTROL, 5);
|
||||
E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
|
||||
E32(0); // DB_COUNT_CONTROL
|
||||
E32(0); // DB_DEPTH_VIEW
|
||||
E32(0x2a); // DB_RENDER_OVERRIDE
|
||||
E32(0); // DB_RENDER_OVERRIDE2
|
||||
|
||||
PACK0(DB_STENCIL_CLEAR, 2);
|
||||
E32(0); // DB_STENCIL_CLEAR
|
||||
E32(0); // DB_DEPTH_CLEAR
|
||||
|
||||
EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) |
|
||||
(2 << ALPHA_TO_MASK_OFFSET1_shift) |
|
||||
(2 << ALPHA_TO_MASK_OFFSET2_shift) |
|
||||
(2 << ALPHA_TO_MASK_OFFSET3_shift)));
|
||||
|
||||
EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
|
||||
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
|
||||
|
||||
// SX
|
||||
EREG(SX_MISC, 0);
|
||||
|
||||
// CB
|
||||
PACK0(SX_ALPHA_TEST_CONTROL, 5);
|
||||
E32(0); // SX_ALPHA_TEST_CONTROL
|
||||
E32(0x00000000); //CB_BLEND_RED
|
||||
E32(0x00000000); //CB_BLEND_GREEN
|
||||
E32(0x00000000); //CB_BLEND_BLUE
|
||||
E32(0x00000000); //CB_BLEND_ALPHA
|
||||
|
||||
EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
|
||||
|
||||
// SC
|
||||
EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
|
||||
(0 << WINDOW_Y_OFFSET_shift)));
|
||||
EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
|
||||
EREG(PA_SC_EDGERULE, 0xAAAAAAAA);
|
||||
EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
|
||||
END_BATCH();
|
||||
|
||||
/* clip boolean is set to always visible -> doesn't matter */
|
||||
for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
|
||||
evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192);
|
||||
|
||||
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
|
||||
evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
|
||||
|
||||
BEGIN_BATCH(73);
|
||||
PACK0(PA_SC_MODE_CNTL_0, 2);
|
||||
E32(0); // PA_SC_MODE_CNTL_0
|
||||
E32(0); // PA_SC_MODE_CNTL_1
|
||||
|
||||
PACK0(PA_SC_CENTROID_PRIORITY_0, 27);
|
||||
E32((0 << DISTANCE_0_shift) |
|
||||
(1 << DISTANCE_1_shift) |
|
||||
(2 << DISTANCE_2_shift) |
|
||||
(3 << DISTANCE_3_shift) |
|
||||
(4 << DISTANCE_4_shift) |
|
||||
(5 << DISTANCE_5_shift) |
|
||||
(6 << DISTANCE_6_shift) |
|
||||
(7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0
|
||||
E32((8 << DISTANCE_8_shift) |
|
||||
(9 << DISTANCE_9_shift) |
|
||||
(10 << DISTANCE_10_shift) |
|
||||
(11 << DISTANCE_11_shift) |
|
||||
(12 << DISTANCE_12_shift) |
|
||||
(13 << DISTANCE_13_shift) |
|
||||
(14 << DISTANCE_14_shift) |
|
||||
(15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1
|
||||
E32(0); // PA_SC_LINE_CNTL
|
||||
E32(0); // PA_SC_AA_CONFIG
|
||||
E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
|
||||
PIX_CENTER_bit)); // PA_SU_VTX_CNTL
|
||||
EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ
|
||||
EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ
|
||||
EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ
|
||||
EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ
|
||||
E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_*
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_*
|
||||
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
|
||||
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
|
||||
|
||||
// CL
|
||||
PACK0(PA_CL_CLIP_CNTL, 8);
|
||||
E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
|
||||
E32(FACE_bit); // PA_SU_SC_MODE_CNTL
|
||||
E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
|
||||
E32(0); // PA_CL_VS_OUT_CNTL
|
||||
E32(0); // PA_CL_NANINF_CNTL
|
||||
E32(0); // PA_SU_LINE_STIPPLE_CNTL
|
||||
E32(0); // PA_SU_LINE_STIPPLE_SCALE
|
||||
E32(0); // PA_SU_PRIM_FILTER_CNTL
|
||||
|
||||
// SU
|
||||
PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
/* src = semantic id 0; mask = semantic id 1 */
|
||||
EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
|
||||
(1 << SEMANTIC_1_shift)));
|
||||
PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
|
||||
/* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
|
||||
E32(((0 << SEMANTIC_shift) |
|
||||
(0x01 << DEFAULT_VAL_shift)));
|
||||
/* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
|
||||
E32(((1 << SEMANTIC_shift) |
|
||||
(0x01 << DEFAULT_VAL_shift)));
|
||||
|
||||
PACK0(SPI_INPUT_Z, 13);
|
||||
E32(0); // SPI_INPUT_Z
|
||||
E32(0); // SPI_FOG_CNTL
|
||||
E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
|
||||
E32(0); // SPI_PS_IN_CONTROL_2
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0); // SPI_GPR_MGMT
|
||||
E32(0); // SPI_LDS_MGMT
|
||||
E32(0); // SPI_STACK_MGMT
|
||||
E32(0); // SPI_WAVE_MGMT_1
|
||||
E32(0); // SPI_WAVE_MGMT_2
|
||||
END_BATCH();
|
||||
|
||||
// clear FS
|
||||
fs_conf.bo = accel_state->shaders_bo;
|
||||
evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
// VGT
|
||||
BEGIN_BATCH(46);
|
||||
|
||||
PACK0(VGT_MAX_VTX_INDX, 4);
|
||||
E32(0xffffff);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
PACK0(VGT_REUSE_OFF, 2);
|
||||
E32(0);
|
||||
E32(0);
|
||||
|
||||
PACK0(PA_SU_POINT_SIZE, 17);
|
||||
E32(0); // PA_SU_POINT_SIZE
|
||||
E32(0); // PA_SU_POINT_MINMAX
|
||||
E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
|
||||
E32(0); // PA_SC_LINE_STIPPLE
|
||||
E32(0); // VGT_OUTPUT_PATH_CNTL
|
||||
E32(0); // VGT_HOS_CNTL
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0);
|
||||
E32(0); // VGT_GS_MODE
|
||||
|
||||
EREG(VGT_PRIMITIVEID_EN, 0);
|
||||
EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0);
|
||||
EREG(VGT_SHADER_STAGES_EN, 0);
|
||||
|
||||
PACK0(VGT_STRMOUT_CONFIG, 2);
|
||||
E32(0);
|
||||
E32(0);
|
||||
END_BATCH();
|
||||
}
|
||||
|
||||
235
src/cayman_reg.h
Normal file
235
src/cayman_reg.h
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
/*
|
||||
* Cayman Register documentation
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _CAYMAN_REG_H_
|
||||
#define _CAYMAN_REG_H_
|
||||
|
||||
/*
|
||||
* Register definitions
|
||||
*/
|
||||
|
||||
#include "cayman_reg_auto.h"
|
||||
|
||||
enum {
|
||||
SHADER_TYPE_PS,
|
||||
SHADER_TYPE_VS,
|
||||
SHADER_TYPE_GS,
|
||||
SHADER_TYPE_HS,
|
||||
SHADER_TYPE_LS,
|
||||
SHADER_TYPE_CS,
|
||||
SHADER_TYPE_FS,
|
||||
};
|
||||
|
||||
|
||||
/* SET_*_REG offsets + ends */
|
||||
#define SET_CONFIG_REG_offset 0x00008000
|
||||
#define SET_CONFIG_REG_end 0x0000ac00
|
||||
#define SET_CONTEXT_REG_offset 0x00028000
|
||||
#define SET_CONTEXT_REG_end 0x00029000
|
||||
#define SET_RESOURCE_offset 0x00030000
|
||||
#define SET_RESOURCE_end 0x00038000
|
||||
#define SET_SAMPLER_offset 0x0003c000
|
||||
#define SET_SAMPLER_end 0x0003c600
|
||||
#define SET_CTL_CONST_offset 0x0003cff0
|
||||
#define SET_CTL_CONST_end 0x0003ff0c
|
||||
#define SET_LOOP_CONST_offset 0x0003a200
|
||||
#define SET_LOOP_CONST_end 0x0003a500
|
||||
#define SET_BOOL_CONST_offset 0x0003a500
|
||||
#define SET_BOOL_CONST_end 0x0003a518
|
||||
|
||||
|
||||
/* Packet3 commands */
|
||||
enum {
|
||||
IT_NOP = 0x10,
|
||||
IT_INDIRECT_BUFFER_END = 0x17,
|
||||
IT_SET_PREDICATION = 0x20,
|
||||
IT_COND_EXEC = 0x22,
|
||||
IT_PRED_EXEC = 0x23,
|
||||
IT_DRAW_INDEX_2 = 0x27,
|
||||
IT_CONTEXT_CONTROL = 0x28,
|
||||
IT_DRAW_INDEX_OFFSET = 0x29,
|
||||
IT_INDEX_TYPE = 0x2A,
|
||||
IT_DRAW_INDEX = 0x2B,
|
||||
IT_DRAW_INDEX_AUTO = 0x2D,
|
||||
IT_DRAW_INDEX_IMMD = 0x2E,
|
||||
IT_NUM_INSTANCES = 0x2F,
|
||||
IT_INDIRECT_BUFFER = 0x32,
|
||||
IT_STRMOUT_BUFFER_UPDATE = 0x34,
|
||||
IT_MEM_SEMAPHORE = 0x39,
|
||||
IT_MPEG_INDEX = 0x3A,
|
||||
IT_WAIT_REG_MEM = 0x3C,
|
||||
IT_MEM_WRITE = 0x3D,
|
||||
IT_SURFACE_SYNC = 0x43,
|
||||
IT_ME_INITIALIZE = 0x44,
|
||||
IT_COND_WRITE = 0x45,
|
||||
IT_EVENT_WRITE = 0x46,
|
||||
IT_EVENT_WRITE_EOP = 0x47,
|
||||
IT_EVENT_WRITE_EOS = 0x48,
|
||||
IT_SET_CONFIG_REG = 0x68,
|
||||
IT_SET_CONTEXT_REG = 0x69,
|
||||
IT_SET_ALU_CONST = 0x6A,
|
||||
IT_SET_BOOL_CONST = 0x6B,
|
||||
IT_SET_LOOP_CONST = 0x6C,
|
||||
IT_SET_RESOURCE = 0x6D,
|
||||
IT_SET_SAMPLER = 0x6E,
|
||||
IT_SET_CTL_CONST = 0x6F,
|
||||
};
|
||||
|
||||
/* IT_WAIT_REG_MEM operation encoding */
|
||||
|
||||
#define IT_WAIT_ALWAYS (0 << 0)
|
||||
#define IT_WAIT_LT (1 << 0)
|
||||
#define IT_WAIT_LE (2 << 0)
|
||||
#define IT_WAIT_EQ (3 << 0)
|
||||
#define IT_WAIT_NE (4 << 0)
|
||||
#define IT_WAIT_GE (5 << 0)
|
||||
#define IT_WAIT_GT (6 << 0)
|
||||
#define IT_WAIT_REG (0 << 4)
|
||||
#define IT_WAIT_MEM (1 << 4)
|
||||
|
||||
#define IT_WAIT_ADDR(x) ((x) >> 2)
|
||||
|
||||
enum {
|
||||
|
||||
SQ_LDS_ALLOC_PS = 0x288ec,
|
||||
SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c,
|
||||
|
||||
CP_COHER_CNTL = 0x85f0,
|
||||
DEST_BASE_0_ENA_bit = 1 << 0,
|
||||
DEST_BASE_1_ENA_bit = 1 << 1,
|
||||
SO0_DEST_BASE_ENA_bit = 1 << 2,
|
||||
SO1_DEST_BASE_ENA_bit = 1 << 3,
|
||||
SO2_DEST_BASE_ENA_bit = 1 << 4,
|
||||
SO3_DEST_BASE_ENA_bit = 1 << 5,
|
||||
CB0_DEST_BASE_ENA_bit = 1 << 6,
|
||||
CB1_DEST_BASE_ENA_bit = 1 << 7,
|
||||
CB2_DEST_BASE_ENA_bit = 1 << 8,
|
||||
CB3_DEST_BASE_ENA_bit = 1 << 9,
|
||||
CB4_DEST_BASE_ENA_bit = 1 << 10,
|
||||
CB5_DEST_BASE_ENA_bit = 1 << 11,
|
||||
CB6_DEST_BASE_ENA_bit = 1 << 12,
|
||||
CB7_DEST_BASE_ENA_bit = 1 << 13,
|
||||
DB_DEST_BASE_ENA_bit = 1 << 14,
|
||||
CB8_DEST_BASE_ENA_bit = 1 << 15,
|
||||
CB9_DEST_BASE_ENA_bit = 1 << 16,
|
||||
CB10_DEST_BASE_ENA_bit = 1 << 17,
|
||||
CB11_DEST_BASE_ENA_bit = 1 << 18,
|
||||
FULL_CACHE_ENA_bit = 1 << 20,
|
||||
TC_ACTION_ENA_bit = 1 << 23,
|
||||
CB_ACTION_ENA_bit = 1 << 25,
|
||||
DB_ACTION_ENA_bit = 1 << 26,
|
||||
SH_ACTION_ENA_bit = 1 << 27,
|
||||
SX_ACTION_ENA_bit = 1 << 28,
|
||||
CP_COHER_SIZE = 0x85f4,
|
||||
CP_COHER_BASE = 0x85f8,
|
||||
CP_COHER_STATUS = 0x85fc,
|
||||
MATCHING_GFX_CNTX_mask = 0xff << 0,
|
||||
MATCHING_GFX_CNTX_shift = 0,
|
||||
STATUS_bit = 1 << 31,
|
||||
|
||||
// SQ_VTX_CONSTANT_WORD2_0 = 0x00030008,
|
||||
// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
|
||||
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
|
||||
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
|
||||
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
|
||||
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
|
||||
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
|
||||
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
|
||||
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
|
||||
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
|
||||
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
|
||||
FMT_1 = 37, FMT_GB_GR=39,
|
||||
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
|
||||
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
|
||||
FMT_32_32_32_FLOAT=48,
|
||||
|
||||
// High level register file lengths
|
||||
SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0,
|
||||
SQ_FETCH_RESOURCE_ps_num = 176,
|
||||
SQ_FETCH_RESOURCE_vs_num = 160,
|
||||
SQ_FETCH_RESOURCE_gs_num = 160,
|
||||
SQ_FETCH_RESOURCE_hs_num = 160,
|
||||
SQ_FETCH_RESOURCE_ls_num = 160,
|
||||
SQ_FETCH_RESOURCE_cs_num = 176,
|
||||
SQ_FETCH_RESOURCE_fs_num = 32,
|
||||
SQ_FETCH_RESOURCE_all_num = 1024,
|
||||
SQ_FETCH_RESOURCE_offset = 32,
|
||||
SQ_FETCH_RESOURCE_ps = 0, // 0...175
|
||||
SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335
|
||||
SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495
|
||||
SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655
|
||||
SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815
|
||||
SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991
|
||||
SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023
|
||||
|
||||
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0,
|
||||
SQ_TEX_SAMPLER_WORD_ps_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_vs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_gs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_hs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_ls_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_cs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_all_num = 108,
|
||||
SQ_TEX_SAMPLER_WORD_offset = 12,
|
||||
SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17
|
||||
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35
|
||||
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53
|
||||
SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71
|
||||
SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89
|
||||
SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107
|
||||
|
||||
SQ_LOOP_CONST = SQ_LOOP_CONST_0,
|
||||
SQ_LOOP_CONST_ps_num = 32,
|
||||
SQ_LOOP_CONST_vs_num = 32,
|
||||
SQ_LOOP_CONST_gs_num = 32,
|
||||
SQ_LOOP_CONST_hs_num = 32,
|
||||
SQ_LOOP_CONST_ls_num = 32,
|
||||
SQ_LOOP_CONST_cs_num = 32,
|
||||
SQ_LOOP_CONST_all_num = 192,
|
||||
SQ_LOOP_CONST_offset = 4,
|
||||
SQ_LOOP_CONST_ps = 0, // 0...31
|
||||
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63
|
||||
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95
|
||||
SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127
|
||||
SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159
|
||||
SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191
|
||||
|
||||
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */
|
||||
SQ_BOOL_CONST_ps_num = 1,
|
||||
SQ_BOOL_CONST_vs_num = 1,
|
||||
SQ_BOOL_CONST_gs_num = 1,
|
||||
SQ_BOOL_CONST_hs_num = 1,
|
||||
SQ_BOOL_CONST_ls_num = 1,
|
||||
SQ_BOOL_CONST_cs_num = 1,
|
||||
SQ_BOOL_CONST_all_num = 6,
|
||||
SQ_BOOL_CONST_offset = 4,
|
||||
SQ_BOOL_CONST_ps = 0,
|
||||
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
|
||||
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num,
|
||||
SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num,
|
||||
SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num,
|
||||
SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num,
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
4351
src/cayman_reg_auto.h
Normal file
4351
src/cayman_reg_auto.h
Normal file
File diff suppressed because it is too large
Load diff
3310
src/cayman_shader.c
Normal file
3310
src/cayman_shader.c
Normal file
File diff suppressed because it is too large
Load diff
279
src/cayman_shader.h
Normal file
279
src/cayman_shader.h
Normal file
|
|
@ -0,0 +1,279 @@
|
|||
/*
|
||||
* Cayman shaders
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Shader macros
|
||||
*/
|
||||
|
||||
#ifndef __SHADER_H__
|
||||
#define __SHADER_H__
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
|
||||
|
||||
|
||||
// CF insts
|
||||
// addr
|
||||
#define ADDR(x) (x)
|
||||
// jumptable
|
||||
#define JUMPTABLE_SEL(x) (x)
|
||||
// pc
|
||||
#define POP_COUNT(x) (x)
|
||||
// const
|
||||
#define CF_CONST(x) (x)
|
||||
// cond
|
||||
#define COND(x) (x) // SQ_COND_*
|
||||
// count
|
||||
#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
|
||||
// vpm
|
||||
#define VALID_PIXEL_MODE(x) (x)
|
||||
// cf inst
|
||||
#define CF_INST(x) (x) // SQ_CF_INST_*
|
||||
// wqm
|
||||
#define WHOLE_QUAD_MODE(x) (x)
|
||||
// barrier
|
||||
#define BARRIER(x) (x)
|
||||
//kb0
|
||||
#define KCACHE_BANK0(x) (x)
|
||||
//kb1
|
||||
#define KCACHE_BANK1(x) (x)
|
||||
// km0/1
|
||||
#define KCACHE_MODE0(x) (x)
|
||||
#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_*
|
||||
//
|
||||
#define KCACHE_ADDR0(x) (x)
|
||||
#define KCACHE_ADDR1(x) (x)
|
||||
|
||||
#define ALT_CONST(x) (x)
|
||||
|
||||
#define ARRAY_BASE(x) (x)
|
||||
// export pixel
|
||||
#define CF_PIXEL_MRT0 0
|
||||
#define CF_PIXEL_MRT1 1
|
||||
#define CF_PIXEL_MRT2 2
|
||||
#define CF_PIXEL_MRT3 3
|
||||
#define CF_PIXEL_MRT4 4
|
||||
#define CF_PIXEL_MRT5 5
|
||||
#define CF_PIXEL_MRT6 6
|
||||
#define CF_PIXEL_MRT7 7
|
||||
// computed Z
|
||||
#define CF_COMPUTED_Z 61
|
||||
// export pos
|
||||
#define CF_POS0 60
|
||||
#define CF_POS1 61
|
||||
#define CF_POS2 62
|
||||
#define CF_POS3 63
|
||||
// export param
|
||||
// 0...31
|
||||
#define TYPE(x) (x) // SQ_EXPORT_*
|
||||
#define RW_GPR(x) (x)
|
||||
#define RW_REL(x) (x)
|
||||
#define ABSOLUTE 0
|
||||
#define RELATIVE 1
|
||||
#define INDEX_GPR(x) (x)
|
||||
#define ELEM_SIZE(x) (x ? (x - 1) : 0)
|
||||
#define BURST_COUNT(x) (x ? (x - 1) : 0)
|
||||
#define MARK(x) (x)
|
||||
|
||||
// swiz
|
||||
#define SRC_SEL_X(x) (x) // SQ_SEL_* each
|
||||
#define SRC_SEL_Y(x) (x)
|
||||
#define SRC_SEL_Z(x) (x)
|
||||
#define SRC_SEL_W(x) (x)
|
||||
|
||||
#define CF_DWORD0(addr, jmptbl) cpu_to_le32(((addr) | ((jmptbl) << 24)))
|
||||
#define CF_DWORD1(pc, cf_const, cond, count, vpm, cf_inst, b) \
|
||||
cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \
|
||||
((vpm) << 20) | ((cf_inst) << 22) | ((b) << 31)))
|
||||
|
||||
#define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)))
|
||||
#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
|
||||
((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
|
||||
cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \
|
||||
((index_gpr) << 23) | ((es) << 30)))
|
||||
#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, cf_inst, m, b) \
|
||||
cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \
|
||||
((bc) << 16) | ((vpm) << 20) | ((cf_inst) << 22) | ((m) << 30) | ((b) << 31)))
|
||||
|
||||
// ALU clause insts
|
||||
#define SRC0_SEL(x) (x)
|
||||
#define SRC1_SEL(x) (x)
|
||||
#define SRC2_SEL(x) (x)
|
||||
// src[0-2]_sel
|
||||
// 0-127 GPR
|
||||
// 128-159 kcache constants bank 0
|
||||
// 160-191 kcache constants bank 1
|
||||
// 192-255 inline const values
|
||||
// 256-287 kcache constants bank 2
|
||||
// 288-319 kcache constants bank 3
|
||||
// 219-255 special SQ_ALU_SRC_* (0, 1, etc.)
|
||||
// 488-520 src param space
|
||||
#define ALU_SRC_GPR_BASE 0
|
||||
#define ALU_SRC_KCACHE0_BASE 128
|
||||
#define ALU_SRC_KCACHE1_BASE 160
|
||||
#define ALU_SRC_INLINE_K_BASE 192
|
||||
#define ALU_SRC_KCACHE2_BASE 256
|
||||
#define ALU_SRC_KCACHE3_BASE 288
|
||||
#define ALU_SRC_PARAM_BASE 448
|
||||
|
||||
#define SRC0_REL(x) (x)
|
||||
#define SRC1_REL(x) (x)
|
||||
#define SRC2_REL(x) (x)
|
||||
// elem
|
||||
#define SRC0_ELEM(x) (x)
|
||||
#define SRC1_ELEM(x) (x)
|
||||
#define SRC2_ELEM(x) (x)
|
||||
#define ELEM_X 0
|
||||
#define ELEM_Y 1
|
||||
#define ELEM_Z 2
|
||||
#define ELEM_W 3
|
||||
// neg
|
||||
#define SRC0_NEG(x) (x)
|
||||
#define SRC1_NEG(x) (x)
|
||||
#define SRC2_NEG(x) (x)
|
||||
// im
|
||||
#define INDEX_MODE(x) (x) // SQ_INDEX_*
|
||||
// ps
|
||||
#define PRED_SEL(x) (x) // SQ_PRED_SEL_*
|
||||
// last
|
||||
#define LAST(x) (x)
|
||||
// abs
|
||||
#define SRC0_ABS(x) (x)
|
||||
#define SRC1_ABS(x) (x)
|
||||
// uem
|
||||
#define UPDATE_EXECUTE_MASK(x) (x)
|
||||
// up
|
||||
#define UPDATE_PRED(x) (x)
|
||||
// wm
|
||||
#define WRITE_MASK(x) (x)
|
||||
// omod
|
||||
#define OMOD(x) (x) // SQ_ALU_OMOD_*
|
||||
// alu inst
|
||||
#define ALU_INST(x) (x) // SQ_ALU_INST_*
|
||||
//bs
|
||||
#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_*
|
||||
#define DST_GPR(x) (x)
|
||||
#define DST_REL(x) (x)
|
||||
#define DST_ELEM(x) (x)
|
||||
#define CLAMP(x) (x)
|
||||
|
||||
#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
|
||||
cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
|
||||
((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
|
||||
((im) << 26) | ((ps) << 29) | ((last) << 31)))
|
||||
|
||||
#define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
|
||||
((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
|
||||
((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
|
||||
|
||||
#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
|
||||
((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
|
||||
((de) << 29) | ((clamp) << 31)))
|
||||
|
||||
// VTX clause insts
|
||||
// vxt insts
|
||||
#define VTX_INST(x) (x) // SQ_VTX_INST_*
|
||||
|
||||
// fetch type
|
||||
#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_*
|
||||
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define BUFFER_ID(x) (x)
|
||||
#define SRC_GPR(x) (x)
|
||||
#define SRC_REL(x) (x)
|
||||
|
||||
#define STRUCTURED_READ(x) (x)
|
||||
#define LDS_REQ(x) (x)
|
||||
#define COALESCED_READ(x) (x)
|
||||
|
||||
#define DST_SEL_X(x) (x)
|
||||
#define DST_SEL_Y(x) (x)
|
||||
#define DST_SEL_Z(x) (x)
|
||||
#define DST_SEL_W(x) (x)
|
||||
#define USE_CONST_FIELDS(x) (x)
|
||||
#define DATA_FORMAT(x) (x)
|
||||
// num format
|
||||
#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_*
|
||||
// format comp
|
||||
#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_*
|
||||
// sma
|
||||
#define SRF_MODE_ALL(x) (x)
|
||||
#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
|
||||
#define SRF_MODE_NO_ZERO 1
|
||||
#define OFFSET(x) (x)
|
||||
// endian swap
|
||||
#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_*
|
||||
#define CONST_BUF_NO_STRIDE(x) (x)
|
||||
#define BUFFER_INDEX_MODE(x) (x)
|
||||
|
||||
#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, ssy, str, ldsr, cr) \
|
||||
cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((ssy) << 26) | \
|
||||
((str) << 28) | ((ldsr) << 30) | ((cr) << 31)))
|
||||
#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
|
||||
#define VTX_DWORD2(offset, es, cbns, alt_const, bim) \
|
||||
cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((alt_const) << 20) | ((bim) << 21)))
|
||||
#define VTX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
// TEX clause insts
|
||||
// tex insts
|
||||
#define TEX_INST(x) (x) // SQ_TEX_INST_*
|
||||
#define INST_MOD(x) (x)
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define RESOURCE_ID(x) (x)
|
||||
#define RESOURCE_INDEX_MODE(x) (x)
|
||||
#define SAMPLER_INDEX_MODE(x) (x)
|
||||
|
||||
#define LOD_BIAS(x) (x)
|
||||
//ct
|
||||
#define COORD_TYPE_X(x) (x)
|
||||
#define COORD_TYPE_Y(x) (x)
|
||||
#define COORD_TYPE_Z(x) (x)
|
||||
#define COORD_TYPE_W(x) (x)
|
||||
#define TEX_UNNORMALIZED 0
|
||||
#define TEX_NORMALIZED 1
|
||||
#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
|
||||
#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
|
||||
#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
|
||||
#define SAMPLER_ID(x) (x)
|
||||
|
||||
#define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \
|
||||
cpu_to_le32((((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27)))
|
||||
#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)))
|
||||
#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
|
||||
cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
|
||||
((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)))
|
||||
#define TEX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
#endif
|
||||
3408
src/drmmode_display.c
Normal file
3408
src/drmmode_display.c
Normal file
File diff suppressed because it is too large
Load diff
269
src/drmmode_display.h
Normal file
269
src/drmmode_display.h
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Copyright © 2007 Red Hat, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Dave Airlie <airlied@redhat.com>
|
||||
*
|
||||
*/
|
||||
#ifndef DRMMODE_DISPLAY_H
|
||||
#define DRMMODE_DISPLAY_H
|
||||
|
||||
#include <X11/extensions/dpmsconst.h>
|
||||
|
||||
#include "xf86drmMode.h"
|
||||
#ifdef HAVE_LIBUDEV
|
||||
#include "libudev.h"
|
||||
#endif
|
||||
|
||||
#include "radeon_drm_queue.h"
|
||||
#include "radeon_probe.h"
|
||||
|
||||
#ifndef DRM_CAP_TIMESTAMP_MONOTONIC
|
||||
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
struct radeon_bo_manager *bufmgr;
|
||||
ScrnInfoPtr scrn;
|
||||
#ifdef HAVE_LIBUDEV
|
||||
struct udev_monitor *uevent_monitor;
|
||||
InputHandlerProc uevent_handler;
|
||||
#endif
|
||||
drmEventContext event_context;
|
||||
int count_crtcs;
|
||||
|
||||
Bool delete_dp_12_displays;
|
||||
|
||||
Bool dri2_flipping;
|
||||
Bool present_flipping;
|
||||
} drmmode_rec, *drmmode_ptr;
|
||||
|
||||
typedef struct {
|
||||
void *event_data;
|
||||
int flip_count;
|
||||
unsigned int fe_frame;
|
||||
uint64_t fe_usec;
|
||||
xf86CrtcPtr fe_crtc;
|
||||
radeon_drm_handler_proc handler;
|
||||
radeon_drm_abort_proc abort;
|
||||
struct drmmode_fb *fb[0];
|
||||
} drmmode_flipdata_rec, *drmmode_flipdata_ptr;
|
||||
|
||||
struct drmmode_fb {
|
||||
int refcnt;
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
enum drmmode_scanout_status {
|
||||
DRMMODE_SCANOUT_OK,
|
||||
DRMMODE_SCANOUT_FLIP_FAILED = 1u << 0,
|
||||
DRMMODE_SCANOUT_VBLANK_FAILED = 1u << 1,
|
||||
};
|
||||
|
||||
struct drmmode_scanout {
|
||||
struct radeon_buffer *bo;
|
||||
PixmapPtr pixmap;
|
||||
int width, height;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
drmmode_ptr drmmode;
|
||||
drmModeCrtcPtr mode_crtc;
|
||||
int hw_id;
|
||||
|
||||
CursorPtr cursor;
|
||||
int cursor_x;
|
||||
int cursor_y;
|
||||
int cursor_xhot;
|
||||
int cursor_yhot;
|
||||
unsigned cursor_id;
|
||||
struct radeon_bo *cursor_bo[2];
|
||||
|
||||
struct drmmode_scanout rotate;
|
||||
struct drmmode_scanout scanout[2];
|
||||
DamagePtr scanout_damage;
|
||||
Bool ignore_damage;
|
||||
RegionRec scanout_last_region;
|
||||
unsigned scanout_id;
|
||||
uintptr_t scanout_update_pending;
|
||||
Bool tear_free;
|
||||
enum drmmode_scanout_status scanout_status;
|
||||
|
||||
PixmapPtr prime_scanout_pixmap;
|
||||
|
||||
int dpms_mode;
|
||||
CARD64 dpms_last_ust;
|
||||
uint32_t dpms_last_seq;
|
||||
int dpms_last_fps;
|
||||
uint32_t interpolated_vblanks;
|
||||
|
||||
/* Modeset needed (for DPMS on or after a page flip crossing with a
|
||||
* modeset)
|
||||
*/
|
||||
Bool need_modeset;
|
||||
/* For keeping track of nested calls to drm_wait_pending_flip /
|
||||
* drm_queue_handle_deferred
|
||||
*/
|
||||
int wait_flip_nesting_level;
|
||||
/* A flip to this FB is pending for this CRTC */
|
||||
struct drmmode_fb *flip_pending;
|
||||
/* The FB currently being scanned out by this CRTC, if any */
|
||||
struct drmmode_fb *fb;
|
||||
} drmmode_crtc_private_rec, *drmmode_crtc_private_ptr;
|
||||
|
||||
typedef struct {
|
||||
drmModePropertyPtr mode_prop;
|
||||
uint64_t value;
|
||||
int num_atoms; /* if range prop, num_atoms == 1; if enum prop, num_atoms == num_enums + 1 */
|
||||
Atom *atoms;
|
||||
} drmmode_prop_rec, *drmmode_prop_ptr;
|
||||
|
||||
|
||||
typedef struct {
|
||||
drmmode_ptr drmmode;
|
||||
int output_id;
|
||||
drmModeConnectorPtr mode_output;
|
||||
drmModeEncoderPtr *mode_encoders;
|
||||
drmModePropertyBlobPtr edid_blob;
|
||||
drmModePropertyBlobPtr tile_blob;
|
||||
int dpms_enum_id;
|
||||
int num_props;
|
||||
drmmode_prop_ptr props;
|
||||
int enc_mask;
|
||||
int enc_clone_mask;
|
||||
int tear_free;
|
||||
} drmmode_output_private_rec, *drmmode_output_private_ptr;
|
||||
|
||||
typedef struct {
|
||||
uint32_t lessee_id;
|
||||
} drmmode_lease_private_rec, *drmmode_lease_private_ptr;
|
||||
|
||||
|
||||
enum drmmode_flip_sync {
|
||||
FLIP_VSYNC,
|
||||
FLIP_ASYNC,
|
||||
};
|
||||
|
||||
|
||||
/* Can the page flip ioctl be used for this CRTC? */
|
||||
static inline Bool
|
||||
drmmode_crtc_can_flip(xf86CrtcPtr crtc)
|
||||
{
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
|
||||
return crtc->enabled &&
|
||||
drmmode_crtc->dpms_mode == DPMSModeOn &&
|
||||
!drmmode_crtc->rotate.bo &&
|
||||
(drmmode_crtc->tear_free ||
|
||||
!drmmode_crtc->scanout[drmmode_crtc->scanout_id].bo);
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
drmmode_fb_reference_loc(int drm_fd, struct drmmode_fb **old, struct drmmode_fb *new,
|
||||
const char *caller, unsigned line)
|
||||
{
|
||||
if (new) {
|
||||
if (new->refcnt <= 0) {
|
||||
FatalError("New FB's refcnt was %d at %s:%u",
|
||||
new->refcnt, caller, line);
|
||||
}
|
||||
|
||||
new->refcnt++;
|
||||
}
|
||||
|
||||
if (*old) {
|
||||
if ((*old)->refcnt <= 0) {
|
||||
FatalError("Old FB's refcnt was %d at %s:%u",
|
||||
(*old)->refcnt, caller, line);
|
||||
}
|
||||
|
||||
if (--(*old)->refcnt == 0) {
|
||||
drmModeRmFB(drm_fd, (*old)->handle);
|
||||
free(*old);
|
||||
}
|
||||
}
|
||||
|
||||
*old = new;
|
||||
}
|
||||
|
||||
#define drmmode_fb_reference(fd, old, new) \
|
||||
drmmode_fb_reference_loc(fd, old, new, __func__, __LINE__)
|
||||
|
||||
|
||||
extern int drmmode_page_flip_target_absolute(RADEONEntPtr pRADEONEnt,
|
||||
drmmode_crtc_private_ptr drmmode_crtc,
|
||||
int fb_id, uint32_t flags,
|
||||
uintptr_t drm_queue_seq,
|
||||
uint32_t target_msc);
|
||||
extern int drmmode_page_flip_target_relative(RADEONEntPtr pRADEONEnt,
|
||||
drmmode_crtc_private_ptr drmmode_crtc,
|
||||
int fb_id, uint32_t flags,
|
||||
uintptr_t drm_queue_seq,
|
||||
uint32_t target_msc);
|
||||
extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp);
|
||||
extern void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode);
|
||||
extern void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode);
|
||||
extern Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr);
|
||||
void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y);
|
||||
extern Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode,
|
||||
Bool set_hw);
|
||||
extern void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode);
|
||||
extern Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn);
|
||||
|
||||
extern void drmmode_crtc_scanout_destroy(drmmode_ptr drmmode,
|
||||
struct drmmode_scanout *scanout);
|
||||
void drmmode_crtc_scanout_free(xf86CrtcPtr crtc);
|
||||
PixmapPtr drmmode_crtc_scanout_create(xf86CrtcPtr crtc,
|
||||
struct drmmode_scanout *scanout,
|
||||
int width, int height);
|
||||
|
||||
extern void drmmode_uevent_init(ScrnInfoPtr scrn, drmmode_ptr drmmode);
|
||||
extern void drmmode_uevent_fini(ScrnInfoPtr scrn, drmmode_ptr drmmode);
|
||||
|
||||
Bool drmmode_set_mode(xf86CrtcPtr crtc, struct drmmode_fb *fb,
|
||||
DisplayModePtr mode, int x, int y);
|
||||
|
||||
extern int drmmode_get_crtc_id(xf86CrtcPtr crtc);
|
||||
extern int drmmode_get_height_align(ScrnInfoPtr scrn, uint32_t tiling);
|
||||
extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
|
||||
extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling);
|
||||
|
||||
Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr client,
|
||||
PixmapPtr new_front, uint64_t id, void *data,
|
||||
xf86CrtcPtr ref_crtc, radeon_drm_handler_proc handler,
|
||||
radeon_drm_abort_proc abort,
|
||||
enum drmmode_flip_sync flip_sync,
|
||||
uint32_t target_msc);
|
||||
int drmmode_crtc_get_ust_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc);
|
||||
int drmmode_get_current_ust(int drm_fd, CARD64 *ust);
|
||||
|
||||
Bool drmmode_wait_vblank(xf86CrtcPtr crtc, drmVBlankSeqType type,
|
||||
uint32_t target_seq, unsigned long signal,
|
||||
uint64_t *ust, uint32_t *result_seq);
|
||||
|
||||
|
||||
extern miPointerSpriteFuncRec drmmode_sprite_funcs;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
1492
src/evergreen_accel.c
Normal file
1492
src/evergreen_accel.c
Normal file
File diff suppressed because it is too large
Load diff
2130
src/evergreen_exa.c
Normal file
2130
src/evergreen_exa.c
Normal file
File diff suppressed because it is too large
Load diff
250
src/evergreen_reg.h
Normal file
250
src/evergreen_reg.h
Normal file
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* Evergeen Register documentation
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_REG_H_
|
||||
#define _EVERGREEN_REG_H_
|
||||
|
||||
/*
|
||||
* Register definitions
|
||||
*/
|
||||
|
||||
#include "evergreen_reg_auto.h"
|
||||
|
||||
enum {
|
||||
SHADER_TYPE_PS,
|
||||
SHADER_TYPE_VS,
|
||||
SHADER_TYPE_GS,
|
||||
SHADER_TYPE_HS,
|
||||
SHADER_TYPE_LS,
|
||||
SHADER_TYPE_CS,
|
||||
SHADER_TYPE_FS,
|
||||
};
|
||||
|
||||
|
||||
/* SET_*_REG offsets + ends */
|
||||
#define SET_CONFIG_REG_offset 0x00008000
|
||||
#define SET_CONFIG_REG_end 0x0000ac00
|
||||
#define SET_CONTEXT_REG_offset 0x00028000
|
||||
#define SET_CONTEXT_REG_end 0x00029000
|
||||
#define SET_RESOURCE_offset 0x00030000
|
||||
#define SET_RESOURCE_end 0x00038000
|
||||
#define SET_SAMPLER_offset 0x0003c000
|
||||
#define SET_SAMPLER_end 0x0003c600
|
||||
#define SET_CTL_CONST_offset 0x0003cff0
|
||||
#define SET_CTL_CONST_end 0x0003ff0c
|
||||
#define SET_LOOP_CONST_offset 0x0003a200
|
||||
#define SET_LOOP_CONST_end 0x0003a500
|
||||
#define SET_BOOL_CONST_offset 0x0003a500
|
||||
#define SET_BOOL_CONST_end 0x0003a518
|
||||
|
||||
|
||||
/* Packet3 commands */
|
||||
enum {
|
||||
IT_NOP = 0x10,
|
||||
IT_INDIRECT_BUFFER_END = 0x17,
|
||||
IT_SET_PREDICATION = 0x20,
|
||||
IT_COND_EXEC = 0x22,
|
||||
IT_PRED_EXEC = 0x23,
|
||||
IT_DRAW_INDEX_2 = 0x27,
|
||||
IT_CONTEXT_CONTROL = 0x28,
|
||||
IT_DRAW_INDEX_OFFSET = 0x29,
|
||||
IT_INDEX_TYPE = 0x2A,
|
||||
IT_DRAW_INDEX = 0x2B,
|
||||
IT_DRAW_INDEX_AUTO = 0x2D,
|
||||
IT_DRAW_INDEX_IMMD = 0x2E,
|
||||
IT_NUM_INSTANCES = 0x2F,
|
||||
IT_INDIRECT_BUFFER = 0x32,
|
||||
IT_STRMOUT_BUFFER_UPDATE = 0x34,
|
||||
IT_MEM_SEMAPHORE = 0x39,
|
||||
IT_MPEG_INDEX = 0x3A,
|
||||
IT_WAIT_REG_MEM = 0x3C,
|
||||
IT_MEM_WRITE = 0x3D,
|
||||
IT_SURFACE_SYNC = 0x43,
|
||||
IT_ME_INITIALIZE = 0x44,
|
||||
IT_COND_WRITE = 0x45,
|
||||
IT_EVENT_WRITE = 0x46,
|
||||
IT_EVENT_WRITE_EOP = 0x47,
|
||||
IT_EVENT_WRITE_EOS = 0x48,
|
||||
IT_SET_CONFIG_REG = 0x68,
|
||||
IT_SET_CONTEXT_REG = 0x69,
|
||||
IT_SET_ALU_CONST = 0x6A,
|
||||
IT_SET_BOOL_CONST = 0x6B,
|
||||
IT_SET_LOOP_CONST = 0x6C,
|
||||
IT_SET_RESOURCE = 0x6D,
|
||||
IT_SET_SAMPLER = 0x6E,
|
||||
IT_SET_CTL_CONST = 0x6F,
|
||||
};
|
||||
|
||||
/* IT_WAIT_REG_MEM operation encoding */
|
||||
|
||||
#define IT_WAIT_ALWAYS (0 << 0)
|
||||
#define IT_WAIT_LT (1 << 0)
|
||||
#define IT_WAIT_LE (2 << 0)
|
||||
#define IT_WAIT_EQ (3 << 0)
|
||||
#define IT_WAIT_NE (4 << 0)
|
||||
#define IT_WAIT_GE (5 << 0)
|
||||
#define IT_WAIT_GT (6 << 0)
|
||||
#define IT_WAIT_REG (0 << 4)
|
||||
#define IT_WAIT_MEM (1 << 4)
|
||||
|
||||
#define IT_WAIT_ADDR(x) ((x) >> 2)
|
||||
|
||||
/* IT_INDEX_TYPE */
|
||||
#define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2)
|
||||
|
||||
enum {
|
||||
|
||||
SQ_LDS_ALLOC_PS = 0x288ec,
|
||||
SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838,
|
||||
SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c,
|
||||
SQ_LDS_RESOURCE_MGMT = 0x8e2c,
|
||||
|
||||
WAIT_UNTIL = 0x8040,
|
||||
WAIT_CP_DMA_IDLE_bit = 1 << 8,
|
||||
WAIT_CMDFIFO_bit = 1 << 10,
|
||||
WAIT_3D_IDLE_bit = 1 << 15,
|
||||
WAIT_3D_IDLECLEAN_bit = 1 << 17,
|
||||
WAIT_EXTERN_SIG_bit = 1 << 19,
|
||||
CMDFIFO_ENTRIES_mask = 0xf << 20,
|
||||
CMDFIFO_ENTRIES_shift = 20,
|
||||
|
||||
CP_COHER_CNTL = 0x85f0,
|
||||
DEST_BASE_0_ENA_bit = 1 << 0,
|
||||
DEST_BASE_1_ENA_bit = 1 << 1,
|
||||
SO0_DEST_BASE_ENA_bit = 1 << 2,
|
||||
SO1_DEST_BASE_ENA_bit = 1 << 3,
|
||||
SO2_DEST_BASE_ENA_bit = 1 << 4,
|
||||
SO3_DEST_BASE_ENA_bit = 1 << 5,
|
||||
CB0_DEST_BASE_ENA_bit = 1 << 6,
|
||||
CB1_DEST_BASE_ENA_bit = 1 << 7,
|
||||
CB2_DEST_BASE_ENA_bit = 1 << 8,
|
||||
CB3_DEST_BASE_ENA_bit = 1 << 9,
|
||||
CB4_DEST_BASE_ENA_bit = 1 << 10,
|
||||
CB5_DEST_BASE_ENA_bit = 1 << 11,
|
||||
CB6_DEST_BASE_ENA_bit = 1 << 12,
|
||||
CB7_DEST_BASE_ENA_bit = 1 << 13,
|
||||
DB_DEST_BASE_ENA_bit = 1 << 14,
|
||||
CB8_DEST_BASE_ENA_bit = 1 << 15,
|
||||
CB9_DEST_BASE_ENA_bit = 1 << 16,
|
||||
CB10_DEST_BASE_ENA_bit = 1 << 17,
|
||||
CB11_DEST_BASE_ENA_bit = 1 << 18,
|
||||
FULL_CACHE_ENA_bit = 1 << 20,
|
||||
TC_ACTION_ENA_bit = 1 << 23,
|
||||
VC_ACTION_ENA_bit = 1 << 24,
|
||||
CB_ACTION_ENA_bit = 1 << 25,
|
||||
DB_ACTION_ENA_bit = 1 << 26,
|
||||
SH_ACTION_ENA_bit = 1 << 27,
|
||||
SX_ACTION_ENA_bit = 1 << 28,
|
||||
CP_COHER_SIZE = 0x85f4,
|
||||
CP_COHER_BASE = 0x85f8,
|
||||
CP_COHER_STATUS = 0x85fc,
|
||||
MATCHING_GFX_CNTX_mask = 0xff << 0,
|
||||
MATCHING_GFX_CNTX_shift = 0,
|
||||
STATUS_bit = 1 << 31,
|
||||
|
||||
// SQ_VTX_CONSTANT_WORD2_0 = 0x00030008,
|
||||
// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
|
||||
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
|
||||
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
|
||||
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
|
||||
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
|
||||
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
|
||||
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
|
||||
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
|
||||
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
|
||||
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
|
||||
FMT_1 = 37, FMT_GB_GR=39,
|
||||
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
|
||||
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
|
||||
FMT_32_32_32_FLOAT=48,
|
||||
|
||||
// High level register file lengths
|
||||
SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0,
|
||||
SQ_FETCH_RESOURCE_ps_num = 176,
|
||||
SQ_FETCH_RESOURCE_vs_num = 160,
|
||||
SQ_FETCH_RESOURCE_gs_num = 160,
|
||||
SQ_FETCH_RESOURCE_hs_num = 160,
|
||||
SQ_FETCH_RESOURCE_ls_num = 160,
|
||||
SQ_FETCH_RESOURCE_cs_num = 176,
|
||||
SQ_FETCH_RESOURCE_fs_num = 32,
|
||||
SQ_FETCH_RESOURCE_all_num = 1024,
|
||||
SQ_FETCH_RESOURCE_offset = 32,
|
||||
SQ_FETCH_RESOURCE_ps = 0, // 0...175
|
||||
SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335
|
||||
SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495
|
||||
SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655
|
||||
SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815
|
||||
SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991
|
||||
SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023
|
||||
|
||||
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0,
|
||||
SQ_TEX_SAMPLER_WORD_ps_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_vs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_gs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_hs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_ls_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_cs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_all_num = 108,
|
||||
SQ_TEX_SAMPLER_WORD_offset = 12,
|
||||
SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17
|
||||
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35
|
||||
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53
|
||||
SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71
|
||||
SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89
|
||||
SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107
|
||||
|
||||
SQ_LOOP_CONST = SQ_LOOP_CONST_0,
|
||||
SQ_LOOP_CONST_ps_num = 32,
|
||||
SQ_LOOP_CONST_vs_num = 32,
|
||||
SQ_LOOP_CONST_gs_num = 32,
|
||||
SQ_LOOP_CONST_hs_num = 32,
|
||||
SQ_LOOP_CONST_ls_num = 32,
|
||||
SQ_LOOP_CONST_cs_num = 32,
|
||||
SQ_LOOP_CONST_all_num = 192,
|
||||
SQ_LOOP_CONST_offset = 4,
|
||||
SQ_LOOP_CONST_ps = 0, // 0...31
|
||||
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63
|
||||
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95
|
||||
SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127
|
||||
SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159
|
||||
SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191
|
||||
|
||||
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */
|
||||
SQ_BOOL_CONST_ps_num = 1,
|
||||
SQ_BOOL_CONST_vs_num = 1,
|
||||
SQ_BOOL_CONST_gs_num = 1,
|
||||
SQ_BOOL_CONST_hs_num = 1,
|
||||
SQ_BOOL_CONST_ls_num = 1,
|
||||
SQ_BOOL_CONST_cs_num = 1,
|
||||
SQ_BOOL_CONST_all_num = 6,
|
||||
SQ_BOOL_CONST_offset = 4,
|
||||
SQ_BOOL_CONST_ps = 0,
|
||||
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
|
||||
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num,
|
||||
SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num,
|
||||
SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num,
|
||||
SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num,
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
4039
src/evergreen_reg_auto.h
Normal file
4039
src/evergreen_reg_auto.h
Normal file
File diff suppressed because it is too large
Load diff
3297
src/evergreen_shader.c
Normal file
3297
src/evergreen_shader.c
Normal file
File diff suppressed because it is too large
Load diff
292
src/evergreen_shader.h
Normal file
292
src/evergreen_shader.h
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* Evergreen shaders
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Shader macros
|
||||
*/
|
||||
|
||||
#ifndef __SHADER_H__
|
||||
#define __SHADER_H__
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
|
||||
|
||||
|
||||
// CF insts
|
||||
// addr
|
||||
#define ADDR(x) (x)
|
||||
// jumptable
|
||||
#define JUMPTABLE_SEL(x) (x)
|
||||
// pc
|
||||
#define POP_COUNT(x) (x)
|
||||
// const
|
||||
#define CF_CONST(x) (x)
|
||||
// cond
|
||||
#define COND(x) (x) // SQ_COND_*
|
||||
// count
|
||||
#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
|
||||
// vpm
|
||||
#define VALID_PIXEL_MODE(x) (x)
|
||||
// eop
|
||||
#define END_OF_PROGRAM(x) (x)
|
||||
// cf inst
|
||||
#define CF_INST(x) (x) // SQ_CF_INST_*
|
||||
// wqm
|
||||
#define WHOLE_QUAD_MODE(x) (x)
|
||||
// barrier
|
||||
#define BARRIER(x) (x)
|
||||
//kb0
|
||||
#define KCACHE_BANK0(x) (x)
|
||||
//kb1
|
||||
#define KCACHE_BANK1(x) (x)
|
||||
// km0/1
|
||||
#define KCACHE_MODE0(x) (x)
|
||||
#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_*
|
||||
//
|
||||
#define KCACHE_ADDR0(x) (x)
|
||||
#define KCACHE_ADDR1(x) (x)
|
||||
|
||||
#define ALT_CONST(x) (x)
|
||||
|
||||
#define ARRAY_BASE(x) (x)
|
||||
// export pixel
|
||||
#define CF_PIXEL_MRT0 0
|
||||
#define CF_PIXEL_MRT1 1
|
||||
#define CF_PIXEL_MRT2 2
|
||||
#define CF_PIXEL_MRT3 3
|
||||
#define CF_PIXEL_MRT4 4
|
||||
#define CF_PIXEL_MRT5 5
|
||||
#define CF_PIXEL_MRT6 6
|
||||
#define CF_PIXEL_MRT7 7
|
||||
// computed Z
|
||||
#define CF_COMPUTED_Z 61
|
||||
// export pos
|
||||
#define CF_POS0 60
|
||||
#define CF_POS1 61
|
||||
#define CF_POS2 62
|
||||
#define CF_POS3 63
|
||||
// export param
|
||||
// 0...31
|
||||
#define TYPE(x) (x) // SQ_EXPORT_*
|
||||
#define RW_GPR(x) (x)
|
||||
#define RW_REL(x) (x)
|
||||
#define ABSOLUTE 0
|
||||
#define RELATIVE 1
|
||||
#define INDEX_GPR(x) (x)
|
||||
#define ELEM_SIZE(x) (x ? (x - 1) : 0)
|
||||
#define BURST_COUNT(x) (x ? (x - 1) : 0)
|
||||
#define MARK(x) (x)
|
||||
|
||||
// swiz
|
||||
#define SRC_SEL_X(x) (x) // SQ_SEL_* each
|
||||
#define SRC_SEL_Y(x) (x)
|
||||
#define SRC_SEL_Z(x) (x)
|
||||
#define SRC_SEL_W(x) (x)
|
||||
|
||||
#define CF_DWORD0(addr, jmptbl) cpu_to_le32(((addr) | ((jmptbl) << 24)))
|
||||
#define CF_DWORD1(pc, cf_const, cond, count, vpm, eop, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \
|
||||
((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | ((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
#define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)))
|
||||
#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
|
||||
((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
|
||||
cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \
|
||||
((index_gpr) << 23) | ((es) << 30)))
|
||||
#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, eop, cf_inst, m, b) \
|
||||
cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \
|
||||
((bc) << 16) | ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | \
|
||||
((m) << 30) | ((b) << 31)))
|
||||
|
||||
// ALU clause insts
|
||||
#define SRC0_SEL(x) (x)
|
||||
#define SRC1_SEL(x) (x)
|
||||
#define SRC2_SEL(x) (x)
|
||||
// src[0-2]_sel
|
||||
// 0-127 GPR
|
||||
// 128-159 kcache constants bank 0
|
||||
// 160-191 kcache constants bank 1
|
||||
// 192-255 inline const values
|
||||
// 256-287 kcache constants bank 2
|
||||
// 288-319 kcache constants bank 3
|
||||
// 219-255 special SQ_ALU_SRC_* (0, 1, etc.)
|
||||
// 488-520 src param space
|
||||
#define ALU_SRC_GPR_BASE 0
|
||||
#define ALU_SRC_KCACHE0_BASE 128
|
||||
#define ALU_SRC_KCACHE1_BASE 160
|
||||
#define ALU_SRC_INLINE_K_BASE 192
|
||||
#define ALU_SRC_KCACHE2_BASE 256
|
||||
#define ALU_SRC_KCACHE3_BASE 288
|
||||
#define ALU_SRC_PARAM_BASE 448
|
||||
|
||||
#define SRC0_REL(x) (x)
|
||||
#define SRC1_REL(x) (x)
|
||||
#define SRC2_REL(x) (x)
|
||||
// elem
|
||||
#define SRC0_ELEM(x) (x)
|
||||
#define SRC1_ELEM(x) (x)
|
||||
#define SRC2_ELEM(x) (x)
|
||||
#define ELEM_X 0
|
||||
#define ELEM_Y 1
|
||||
#define ELEM_Z 2
|
||||
#define ELEM_W 3
|
||||
// neg
|
||||
#define SRC0_NEG(x) (x)
|
||||
#define SRC1_NEG(x) (x)
|
||||
#define SRC2_NEG(x) (x)
|
||||
// im
|
||||
#define INDEX_MODE(x) (x) // SQ_INDEX_*
|
||||
// ps
|
||||
#define PRED_SEL(x) (x) // SQ_PRED_SEL_*
|
||||
// last
|
||||
#define LAST(x) (x)
|
||||
// abs
|
||||
#define SRC0_ABS(x) (x)
|
||||
#define SRC1_ABS(x) (x)
|
||||
// uem
|
||||
#define UPDATE_EXECUTE_MASK(x) (x)
|
||||
// up
|
||||
#define UPDATE_PRED(x) (x)
|
||||
// wm
|
||||
#define WRITE_MASK(x) (x)
|
||||
// omod
|
||||
#define OMOD(x) (x) // SQ_ALU_OMOD_*
|
||||
// alu inst
|
||||
#define ALU_INST(x) (x) // SQ_ALU_INST_*
|
||||
//bs
|
||||
#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_*
|
||||
#define DST_GPR(x) (x)
|
||||
#define DST_REL(x) (x)
|
||||
#define DST_ELEM(x) (x)
|
||||
#define CLAMP(x) (x)
|
||||
|
||||
#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
|
||||
cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
|
||||
((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
|
||||
((im) << 26) | ((ps) << 29) | ((last) << 31)))
|
||||
|
||||
#define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
|
||||
((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
|
||||
((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
|
||||
|
||||
#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
|
||||
((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
|
||||
((de) << 29) | ((clamp) << 31)))
|
||||
|
||||
// VTX clause insts
|
||||
// vxt insts
|
||||
#define VTX_INST(x) (x) // SQ_VTX_INST_*
|
||||
|
||||
// fetch type
|
||||
#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_*
|
||||
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define BUFFER_ID(x) (x)
|
||||
#define SRC_GPR(x) (x)
|
||||
#define SRC_REL(x) (x)
|
||||
#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
|
||||
|
||||
#define DST_SEL_X(x) (x)
|
||||
#define DST_SEL_Y(x) (x)
|
||||
#define DST_SEL_Z(x) (x)
|
||||
#define DST_SEL_W(x) (x)
|
||||
#define USE_CONST_FIELDS(x) (x)
|
||||
#define DATA_FORMAT(x) (x)
|
||||
// num format
|
||||
#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_*
|
||||
// format comp
|
||||
#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_*
|
||||
// sma
|
||||
#define SRF_MODE_ALL(x) (x)
|
||||
#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
|
||||
#define SRF_MODE_NO_ZERO 1
|
||||
#define OFFSET(x) (x)
|
||||
// endian swap
|
||||
#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_*
|
||||
#define CONST_BUF_NO_STRIDE(x) (x)
|
||||
// mf
|
||||
#define MEGA_FETCH(x) (x)
|
||||
#define BUFFER_INDEX_MODE(x) (x)
|
||||
|
||||
#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
|
||||
cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)))
|
||||
#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
|
||||
#define VTX_DWORD2(offset, es, cbns, mf, alt_const, bim) \
|
||||
cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19) | ((alt_const) << 20) | ((bim) << 21)))
|
||||
#define VTX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
// TEX clause insts
|
||||
// tex insts
|
||||
#define TEX_INST(x) (x) // SQ_TEX_INST_*
|
||||
#define INST_MOD(x) (x)
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define RESOURCE_ID(x) (x)
|
||||
#define RESOURCE_INDEX_MODE(x) (x)
|
||||
#define SAMPLER_INDEX_MODE(x) (x)
|
||||
|
||||
#define LOD_BIAS(x) (x)
|
||||
//ct
|
||||
#define COORD_TYPE_X(x) (x)
|
||||
#define COORD_TYPE_Y(x) (x)
|
||||
#define COORD_TYPE_Z(x) (x)
|
||||
#define COORD_TYPE_W(x) (x)
|
||||
#define TEX_UNNORMALIZED 0
|
||||
#define TEX_NORMALIZED 1
|
||||
#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
|
||||
#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
|
||||
#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
|
||||
#define SAMPLER_ID(x) (x)
|
||||
|
||||
#define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \
|
||||
cpu_to_le32((((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27)))
|
||||
#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)))
|
||||
#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
|
||||
cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
|
||||
((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)))
|
||||
#define TEX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
extern int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int evergreen_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
extern int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int evergreen_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
extern int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader);
|
||||
extern int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader);
|
||||
|
||||
extern int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
#endif
|
||||
356
src/evergreen_state.h
Normal file
356
src/evergreen_state.h
Normal file
|
|
@ -0,0 +1,356 @@
|
|||
/*
|
||||
* Copyright 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors: Alex Deucher <alexander.deucher@amd.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __EVERGREEN_STATE_H__
|
||||
#define __EVERGREEN_STATE_H__
|
||||
|
||||
typedef int bool_t;
|
||||
|
||||
#define CLEAR(x) memset (&x, 0, sizeof(x))
|
||||
|
||||
/* Sequencer / thread handling */
|
||||
typedef struct {
|
||||
int ps_prio;
|
||||
int vs_prio;
|
||||
int gs_prio;
|
||||
int es_prio;
|
||||
int hs_prio;
|
||||
int ls_prio;
|
||||
int cs_prio;
|
||||
int num_ps_gprs;
|
||||
int num_vs_gprs;
|
||||
int num_gs_gprs;
|
||||
int num_es_gprs;
|
||||
int num_hs_gprs;
|
||||
int num_ls_gprs;
|
||||
int num_cs_gprs;
|
||||
int num_temp_gprs;
|
||||
int num_ps_threads;
|
||||
int num_vs_threads;
|
||||
int num_gs_threads;
|
||||
int num_es_threads;
|
||||
int num_hs_threads;
|
||||
int num_ls_threads;
|
||||
int num_ps_stack_entries;
|
||||
int num_vs_stack_entries;
|
||||
int num_gs_stack_entries;
|
||||
int num_es_stack_entries;
|
||||
int num_hs_stack_entries;
|
||||
int num_ls_stack_entries;
|
||||
} sq_config_t;
|
||||
|
||||
/* Color buffer / render target */
|
||||
typedef struct {
|
||||
int id;
|
||||
int w;
|
||||
int h;
|
||||
uint64_t base;
|
||||
int format;
|
||||
int endian;
|
||||
int array_mode; // tiling
|
||||
int non_disp_tiling;
|
||||
int number_type;
|
||||
int read_size;
|
||||
int comp_swap;
|
||||
int tile_mode;
|
||||
int blend_clamp;
|
||||
int clear_color;
|
||||
int blend_bypass;
|
||||
int simple_float;
|
||||
int round_mode;
|
||||
int tile_compact;
|
||||
int source_format;
|
||||
int resource_type;
|
||||
int fast_clear;
|
||||
int compression;
|
||||
int rat;
|
||||
/* 2D related CB state */
|
||||
uint32_t pmask;
|
||||
int rop;
|
||||
int blend_enable;
|
||||
uint32_t blendcntl;
|
||||
struct radeon_bo *bo;
|
||||
struct radeon_surface *surface;
|
||||
} cb_config_t;
|
||||
|
||||
/* Shader */
|
||||
typedef struct {
|
||||
uint64_t shader_addr;
|
||||
uint32_t shader_size;
|
||||
int num_gprs;
|
||||
int stack_size;
|
||||
int dx10_clamp;
|
||||
int clamp_consts;
|
||||
int export_mode;
|
||||
int uncached_first_inst;
|
||||
int single_round;
|
||||
int double_round;
|
||||
int allow_sdi;
|
||||
int allow_sd0;
|
||||
int allow_ddi;
|
||||
int allow_ddo;
|
||||
struct radeon_bo *bo;
|
||||
} shader_config_t;
|
||||
|
||||
/* Shader consts */
|
||||
typedef struct {
|
||||
int type;
|
||||
int size_bytes;
|
||||
uint64_t const_addr;
|
||||
struct radeon_bo *bo;
|
||||
uint32_t *cpu_ptr;
|
||||
} const_config_t;
|
||||
|
||||
/* Vertex buffer / vtx resource */
|
||||
typedef struct {
|
||||
int id;
|
||||
uint64_t vb_addr;
|
||||
uint32_t vtx_num_entries;
|
||||
uint32_t vtx_size_dw;
|
||||
int clamp_x;
|
||||
int format;
|
||||
int num_format_all;
|
||||
int format_comp_all;
|
||||
int srf_mode_all;
|
||||
int endian;
|
||||
int mem_req_size;
|
||||
int dst_sel_x;
|
||||
int dst_sel_y;
|
||||
int dst_sel_z;
|
||||
int dst_sel_w;
|
||||
int uncached;
|
||||
struct radeon_bo *bo;
|
||||
} vtx_resource_t;
|
||||
|
||||
/* Texture resource */
|
||||
typedef struct {
|
||||
int id;
|
||||
int w;
|
||||
int h;
|
||||
int pitch;
|
||||
int depth;
|
||||
int dim;
|
||||
int array_mode;
|
||||
int tile_type;
|
||||
int format;
|
||||
uint64_t base;
|
||||
uint64_t mip_base;
|
||||
uint32_t size;
|
||||
int format_comp_x;
|
||||
int format_comp_y;
|
||||
int format_comp_z;
|
||||
int format_comp_w;
|
||||
int num_format_all;
|
||||
int srf_mode_all;
|
||||
int force_degamma;
|
||||
int endian;
|
||||
int dst_sel_x;
|
||||
int dst_sel_y;
|
||||
int dst_sel_z;
|
||||
int dst_sel_w;
|
||||
int base_level;
|
||||
int last_level;
|
||||
int base_array;
|
||||
int last_array;
|
||||
int perf_modulation;
|
||||
int interlaced;
|
||||
int min_lod;
|
||||
struct radeon_bo *bo;
|
||||
struct radeon_bo *mip_bo;
|
||||
struct radeon_surface *surface;
|
||||
} tex_resource_t;
|
||||
|
||||
/* Texture sampler */
|
||||
typedef struct {
|
||||
int id;
|
||||
/* Clamping */
|
||||
int clamp_x, clamp_y, clamp_z;
|
||||
int border_color;
|
||||
/* Filtering */
|
||||
int xy_mag_filter, xy_min_filter;
|
||||
int z_filter;
|
||||
int mip_filter;
|
||||
bool_t high_precision_filter; /* ? */
|
||||
int perf_mip; /* ? 0-7 */
|
||||
int perf_z; /* ? 3 */
|
||||
/* LoD selection */
|
||||
int min_lod, max_lod; /* 0-0x3ff */
|
||||
int lod_bias; /* 0-0xfff (signed?) */
|
||||
int lod_bias2; /* ? 0-0xfff (signed?) */
|
||||
bool_t lod_uses_minor_axis; /* ? */
|
||||
/* Other stuff */
|
||||
bool_t point_sampling_clamp; /* ? */
|
||||
bool_t tex_array_override; /* ? */
|
||||
bool_t mc_coord_truncate; /* ? */
|
||||
bool_t force_degamma; /* ? */
|
||||
bool_t fetch_4; /* ? */
|
||||
bool_t sample_is_pcf; /* ? */
|
||||
bool_t type; /* ? */
|
||||
int depth_compare; /* only depth textures? */
|
||||
int chroma_key;
|
||||
int truncate_coord;
|
||||
bool_t disable_cube_wrap;
|
||||
} tex_sampler_t;
|
||||
|
||||
/* Draw command */
|
||||
typedef struct {
|
||||
uint32_t prim_type;
|
||||
uint32_t vgt_draw_initiator;
|
||||
uint32_t index_type;
|
||||
uint32_t num_instances;
|
||||
uint32_t num_indices;
|
||||
} draw_config_t;
|
||||
|
||||
#define BEGIN_BATCH(n) \
|
||||
do { \
|
||||
radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define END_BATCH() \
|
||||
do { \
|
||||
radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define RELOC_BATCH(bo, rd, wd) \
|
||||
do { \
|
||||
int _ret; \
|
||||
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
|
||||
if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define E32(dword) \
|
||||
do { \
|
||||
radeon_cs_write_dword(info->cs, (dword)); \
|
||||
} while (0)
|
||||
|
||||
#define EFLOAT(val) \
|
||||
do { \
|
||||
union { float f; uint32_t d; } a; \
|
||||
a.f = (val); \
|
||||
E32(a.d); \
|
||||
} while (0)
|
||||
|
||||
#define PACK3(cmd, num) \
|
||||
do { \
|
||||
E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
|
||||
} while (0)
|
||||
|
||||
/* write num registers, start at reg */
|
||||
/* If register falls in a special area, special commands are issued */
|
||||
#define PACK0(reg, num) \
|
||||
do { \
|
||||
if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
|
||||
PACK3(IT_SET_CONFIG_REG, (num) + 1); \
|
||||
E32(((reg) - SET_CONFIG_REG_offset) >> 2); \
|
||||
} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
|
||||
PACK3(IT_SET_CONTEXT_REG, (num) + 1); \
|
||||
E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \
|
||||
} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
|
||||
PACK3(IT_SET_RESOURCE, num + 1); \
|
||||
E32(((reg) - SET_RESOURCE_offset) >> 2); \
|
||||
} else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
|
||||
PACK3(IT_SET_SAMPLER, (num) + 1); \
|
||||
E32((reg - SET_SAMPLER_offset) >> 2); \
|
||||
} else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
|
||||
PACK3(IT_SET_CTL_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_CTL_CONST_offset) >> 2); \
|
||||
} else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
|
||||
PACK3(IT_SET_LOOP_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_LOOP_CONST_offset) >> 2); \
|
||||
} else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
|
||||
PACK3(IT_SET_BOOL_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_BOOL_CONST_offset) >> 2); \
|
||||
} else { \
|
||||
E32(CP_PACKET0 ((reg), (num) - 1)); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* write a single register */
|
||||
#define EREG(reg, val) \
|
||||
do { \
|
||||
PACK0((reg), 1); \
|
||||
E32((val)); \
|
||||
} while (0)
|
||||
|
||||
void
|
||||
evergreen_start_3d(ScrnInfoPtr pScrn);
|
||||
void
|
||||
evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
|
||||
void
|
||||
evergreen_set_blend_color(ScrnInfoPtr pScrn, float *color);
|
||||
void
|
||||
evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
|
||||
void
|
||||
evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
|
||||
void
|
||||
evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
|
||||
void
|
||||
evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
|
||||
void
|
||||
evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
|
||||
void
|
||||
evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
|
||||
void
|
||||
evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
|
||||
void
|
||||
evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
|
||||
void
|
||||
evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
|
||||
void
|
||||
evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
evergreen_set_default_state(ScrnInfoPtr pScrn);
|
||||
void
|
||||
cayman_set_default_state(ScrnInfoPtr pScrn);
|
||||
void
|
||||
evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
|
||||
|
||||
void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
|
||||
|
||||
extern Bool
|
||||
R600SetAccelState(ScrnInfoPtr pScrn,
|
||||
struct r600_accel_object *src0,
|
||||
struct r600_accel_object *src1,
|
||||
struct r600_accel_object *dst,
|
||||
uint32_t vs_offset, uint32_t ps_offset,
|
||||
int rop, Pixel planemask);
|
||||
|
||||
extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
|
||||
extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
|
||||
extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
|
||||
int depth, int usage_hint, int bitsPerPixel,
|
||||
int *new_pitch);
|
||||
extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
|
||||
extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
|
||||
extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr secondary, void **handle_p);
|
||||
extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);
|
||||
|
||||
#endif
|
||||
515
src/evergreen_textured_videofuncs.c
Normal file
515
src/evergreen_textured_videofuncs.c
Normal file
|
|
@ -0,0 +1,515 @@
|
|||
/*
|
||||
* Copyright 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Author: Alex Deucher <alexander.deucher@amd.com>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
#include "exa.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "evergreen_shader.h"
|
||||
#include "evergreen_reg.h"
|
||||
#include "evergreen_state.h"
|
||||
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include <X11/extensions/Xv.h>
|
||||
#include "fourcc.h"
|
||||
|
||||
#include "damage.h"
|
||||
|
||||
#include "radeon_exa_shared.h"
|
||||
#include "radeon_vbo.h"
|
||||
|
||||
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
|
||||
note the difference to the parameters used in overlay are due
|
||||
to 10bit vs. float calcs */
|
||||
static REF_TRANSFORM trans[2] =
|
||||
{
|
||||
{1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */
|
||||
{1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */
|
||||
};
|
||||
|
||||
void
|
||||
EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
PixmapPtr pPixmap = pPriv->pPixmap;
|
||||
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
|
||||
int nBox = REGION_NUM_RECTS(&pPriv->clip);
|
||||
int dstxoff, dstyoff;
|
||||
struct r600_accel_object src_obj, dst_obj;
|
||||
cb_config_t cb_conf;
|
||||
tex_resource_t tex_res;
|
||||
tex_sampler_t tex_samp;
|
||||
shader_config_t vs_conf, ps_conf;
|
||||
/*
|
||||
* y' = y - .0625
|
||||
* u' = u - .5
|
||||
* v' = v - .5;
|
||||
*
|
||||
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
|
||||
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
|
||||
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
|
||||
*
|
||||
* DP3 might look like the straightforward solution
|
||||
* but we'd need to move the texture yuv values in
|
||||
* the same reg for this to work. Therefore use MADs.
|
||||
* Brightness just adds to the off constant.
|
||||
* Contrast is multiplication of luminance.
|
||||
* Saturation and hue change the u and v coeffs.
|
||||
* Default values (before adjustments - depend on colorspace):
|
||||
* yco = 1.1643
|
||||
* uco = 0, -0.39173, 2.017
|
||||
* vco = 1.5958, -0.8129, 0
|
||||
* off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r],
|
||||
* -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g],
|
||||
* -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b],
|
||||
*
|
||||
* temp = MAD(yco, yuv.yyyy, off)
|
||||
* temp = MAD(uco, yuv.uuuu, temp)
|
||||
* result = MAD(vco, yuv.vvvv, temp)
|
||||
*/
|
||||
/* TODO: calc consts in the shader */
|
||||
const float Loff = -0.0627;
|
||||
const float Coff = -0.502;
|
||||
float uvcosf, uvsinf;
|
||||
float yco;
|
||||
float uco[3], vco[3], off[3];
|
||||
float bright, cont, gamma;
|
||||
int ref = pPriv->transform_index;
|
||||
float *ps_alu_consts;
|
||||
const_config_t ps_const_conf;
|
||||
float *vs_alu_consts;
|
||||
const_config_t vs_const_conf;
|
||||
|
||||
cont = RTFContrast(pPriv->contrast);
|
||||
bright = RTFBrightness(pPriv->brightness);
|
||||
gamma = (float)pPriv->gamma / 1000.0;
|
||||
uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue));
|
||||
uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue));
|
||||
/* overlay video also does pre-gamma contrast/sat adjust, should we? */
|
||||
|
||||
yco = trans[ref].RefLuma * cont;
|
||||
uco[0] = -trans[ref].RefRCr * uvsinf;
|
||||
uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf;
|
||||
uco[2] = trans[ref].RefBCb * uvcosf;
|
||||
vco[0] = trans[ref].RefRCr * uvcosf;
|
||||
vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf;
|
||||
vco[2] = trans[ref].RefBCb * uvsinf;
|
||||
off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright;
|
||||
off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright;
|
||||
off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright;
|
||||
|
||||
// XXX
|
||||
gamma = 1.0;
|
||||
|
||||
CLEAR (cb_conf);
|
||||
CLEAR (tex_res);
|
||||
CLEAR (tex_samp);
|
||||
CLEAR (vs_conf);
|
||||
CLEAR (ps_conf);
|
||||
CLEAR (vs_const_conf);
|
||||
CLEAR (ps_const_conf);
|
||||
|
||||
dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
|
||||
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
|
||||
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
|
||||
|
||||
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
|
||||
|
||||
src_obj.pitch = pPriv->src_pitch;
|
||||
src_obj.width = pPriv->w;
|
||||
src_obj.height = pPriv->h;
|
||||
src_obj.bpp = 16;
|
||||
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
|
||||
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
|
||||
src_obj.tiling_flags = 0;
|
||||
src_obj.surface = NULL;
|
||||
|
||||
dst_obj.width = pPixmap->drawable.width;
|
||||
dst_obj.height = pPixmap->drawable.height;
|
||||
dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
|
||||
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
|
||||
|
||||
if (!R600SetAccelState(pScrn,
|
||||
&src_obj,
|
||||
NULL,
|
||||
&dst_obj,
|
||||
accel_state->xv_vs_offset, accel_state->xv_ps_offset,
|
||||
3, 0xffffffff))
|
||||
return;
|
||||
|
||||
#ifdef COMPOSITE
|
||||
dstxoff = -pPixmap->screen_x + pPixmap->drawable.x;
|
||||
dstyoff = -pPixmap->screen_y + pPixmap->drawable.y;
|
||||
#else
|
||||
dstxoff = 0;
|
||||
dstyoff = 0;
|
||||
#endif
|
||||
|
||||
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
|
||||
radeon_vbo_check(pScrn, &accel_state->cbuf, 512);
|
||||
radeon_cp_start(pScrn);
|
||||
|
||||
evergreen_set_default_state(pScrn);
|
||||
|
||||
evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
|
||||
/* PS bool constant */
|
||||
switch(pPriv->id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0));
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0));
|
||||
break;
|
||||
}
|
||||
|
||||
/* Shader */
|
||||
vs_conf.shader_addr = accel_state->vs_mc_addr;
|
||||
vs_conf.shader_size = accel_state->vs_size;
|
||||
vs_conf.num_gprs = 2;
|
||||
vs_conf.stack_size = 0;
|
||||
vs_conf.bo = accel_state->shaders_bo;
|
||||
evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
ps_conf.shader_addr = accel_state->ps_mc_addr;
|
||||
ps_conf.shader_size = accel_state->ps_size;
|
||||
ps_conf.num_gprs = 3;
|
||||
ps_conf.stack_size = 1;
|
||||
ps_conf.clamp_consts = 0;
|
||||
ps_conf.export_mode = 2;
|
||||
ps_conf.bo = accel_state->shaders_bo;
|
||||
evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
/* Texture */
|
||||
switch(pPriv->id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
|
||||
|
||||
/* Y texture */
|
||||
tex_res.id = 0;
|
||||
tex_res.w = accel_state->src_obj[0].width;
|
||||
tex_res.h = accel_state->src_obj[0].height;
|
||||
tex_res.pitch = accel_state->src_obj[0].pitch;
|
||||
tex_res.depth = 0;
|
||||
tex_res.dim = SQ_TEX_DIM_2D;
|
||||
tex_res.base = 0;
|
||||
tex_res.mip_base = 0;
|
||||
tex_res.size = accel_state->src_size[0];
|
||||
tex_res.bo = accel_state->src_obj[0].bo;
|
||||
tex_res.mip_bo = accel_state->src_obj[0].bo;
|
||||
tex_res.surface = NULL;
|
||||
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* Y sampler */
|
||||
tex_samp.id = 0;
|
||||
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_z = SQ_TEX_WRAP;
|
||||
|
||||
/* xxx: switch to bicubic */
|
||||
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
|
||||
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
|
||||
tex_samp.mip_filter = 0; /* no mipmap */
|
||||
evergreen_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
/* U or V texture */
|
||||
tex_res.id = 1;
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.w = accel_state->src_obj[0].width >> 1;
|
||||
tex_res.h = accel_state->src_obj[0].height >> 1;
|
||||
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
tex_res.interlaced = 0;
|
||||
|
||||
tex_res.base = pPriv->planev_offset;
|
||||
tex_res.mip_base = pPriv->planev_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* U or V sampler */
|
||||
tex_samp.id = 1;
|
||||
evergreen_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
/* U or V texture */
|
||||
tex_res.id = 2;
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.w = accel_state->src_obj[0].width >> 1;
|
||||
tex_res.h = accel_state->src_obj[0].height >> 1;
|
||||
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
tex_res.interlaced = 0;
|
||||
|
||||
tex_res.base = pPriv->planeu_offset;
|
||||
tex_res.mip_base = pPriv->planeu_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* UV sampler */
|
||||
tex_samp.id = 2;
|
||||
evergreen_set_tex_sampler(pScrn, &tex_samp);
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
|
||||
|
||||
/* YUV texture */
|
||||
tex_res.id = 0;
|
||||
tex_res.w = accel_state->src_obj[0].width;
|
||||
tex_res.h = accel_state->src_obj[0].height;
|
||||
tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
|
||||
tex_res.depth = 0;
|
||||
tex_res.dim = SQ_TEX_DIM_2D;
|
||||
tex_res.base = 0;
|
||||
tex_res.mip_base = 0;
|
||||
tex_res.size = accel_state->src_size[0];
|
||||
tex_res.bo = accel_state->src_obj[0].bo;
|
||||
tex_res.mip_bo = accel_state->src_obj[0].bo;
|
||||
tex_res.surface = NULL;
|
||||
|
||||
if (pPriv->id == FOURCC_UYVY)
|
||||
tex_res.format = FMT_GB_GR;
|
||||
else
|
||||
tex_res.format = FMT_BG_RG;
|
||||
tex_res.dst_sel_x = SQ_SEL_Y;
|
||||
tex_res.dst_sel_y = SQ_SEL_X;
|
||||
tex_res.dst_sel_z = SQ_SEL_Z;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* YUV sampler */
|
||||
tex_samp.id = 0;
|
||||
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_z = SQ_TEX_WRAP;
|
||||
|
||||
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
|
||||
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
|
||||
tex_samp.mip_filter = 0; /* no mipmap */
|
||||
evergreen_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
cb_conf.id = 0;
|
||||
cb_conf.w = accel_state->dst_obj.pitch;
|
||||
cb_conf.h = accel_state->dst_obj.height;
|
||||
cb_conf.base = 0;
|
||||
cb_conf.bo = accel_state->dst_obj.bo;
|
||||
cb_conf.surface = accel_state->dst_obj.surface;
|
||||
|
||||
switch (accel_state->dst_obj.bpp) {
|
||||
case 16:
|
||||
if (pPixmap->drawable.depth == 15) {
|
||||
cb_conf.format = COLOR_1_5_5_5;
|
||||
cb_conf.comp_swap = 1; /* ARGB */
|
||||
} else {
|
||||
cb_conf.format = COLOR_5_6_5;
|
||||
cb_conf.comp_swap = 2; /* RGB */
|
||||
}
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
cb_conf.endian = ENDIAN_8IN16;
|
||||
#endif
|
||||
break;
|
||||
case 32:
|
||||
cb_conf.format = COLOR_8_8_8_8;
|
||||
cb_conf.comp_swap = 1; /* ARGB */
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
cb_conf.endian = ENDIAN_8IN32;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
cb_conf.source_format = EXPORT_4C_16BPC;
|
||||
cb_conf.blend_clamp = 1;
|
||||
cb_conf.pmask = 0xf;
|
||||
cb_conf.rop = 3;
|
||||
if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR) {
|
||||
cb_conf.array_mode = 1;
|
||||
cb_conf.non_disp_tiling = 1;
|
||||
}
|
||||
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
|
||||
|
||||
evergreen_set_spi(pScrn, (1 - 1), 1);
|
||||
|
||||
/* PS alu constants */
|
||||
ps_const_conf.size_bytes = 256;
|
||||
ps_const_conf.type = SHADER_TYPE_PS;
|
||||
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
|
||||
ps_const_conf.bo = accel_state->cbuf.vb_bo;
|
||||
ps_const_conf.const_addr = accel_state->cbuf.vb_offset;
|
||||
ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts;
|
||||
|
||||
ps_alu_consts[0] = off[0];
|
||||
ps_alu_consts[1] = off[1];
|
||||
ps_alu_consts[2] = off[2];
|
||||
ps_alu_consts[3] = yco;
|
||||
|
||||
ps_alu_consts[4] = uco[0];
|
||||
ps_alu_consts[5] = uco[1];
|
||||
ps_alu_consts[6] = uco[2];
|
||||
ps_alu_consts[7] = gamma;
|
||||
|
||||
ps_alu_consts[8] = vco[0];
|
||||
ps_alu_consts[9] = vco[1];
|
||||
ps_alu_consts[10] = vco[2];
|
||||
ps_alu_consts[11] = 0.0;
|
||||
|
||||
radeon_vbo_commit(pScrn, &accel_state->cbuf);
|
||||
evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
|
||||
|
||||
/* VS alu constants */
|
||||
vs_const_conf.size_bytes = 256;
|
||||
vs_const_conf.type = SHADER_TYPE_VS;
|
||||
vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
|
||||
vs_const_conf.bo = accel_state->cbuf.vb_bo;
|
||||
vs_const_conf.const_addr = accel_state->cbuf.vb_offset;
|
||||
vs_const_conf.cpu_ptr = (uint32_t *)(char *)vs_alu_consts;
|
||||
|
||||
vs_alu_consts[0] = 1.0 / pPriv->w;
|
||||
vs_alu_consts[1] = 1.0 / pPriv->h;
|
||||
vs_alu_consts[2] = 0.0;
|
||||
vs_alu_consts[3] = 0.0;
|
||||
|
||||
radeon_vbo_commit(pScrn, &accel_state->cbuf);
|
||||
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
|
||||
|
||||
if (pPriv->vsync) {
|
||||
xf86CrtcPtr crtc;
|
||||
if (pPriv->desired_crtc)
|
||||
crtc = pPriv->desired_crtc;
|
||||
else
|
||||
crtc = radeon_pick_best_crtc(pScrn, FALSE,
|
||||
pPriv->drw_x,
|
||||
pPriv->drw_x + pPriv->dst_w,
|
||||
pPriv->drw_y,
|
||||
pPriv->drw_y + pPriv->dst_h);
|
||||
if (crtc)
|
||||
evergreen_cp_wait_vline_sync(pScrn, pPixmap,
|
||||
crtc,
|
||||
pPriv->drw_y - crtc->y,
|
||||
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
|
||||
}
|
||||
|
||||
while (nBox--) {
|
||||
float srcX, srcY, srcw, srch;
|
||||
int dstX, dstY, dstw, dsth;
|
||||
float *vb;
|
||||
|
||||
|
||||
dstX = pBox->x1 + dstxoff;
|
||||
dstY = pBox->y1 + dstyoff;
|
||||
dstw = pBox->x2 - pBox->x1;
|
||||
dsth = pBox->y2 - pBox->y1;
|
||||
|
||||
srcX = pPriv->src_x;
|
||||
srcX += ((pBox->x1 - pPriv->drw_x) *
|
||||
pPriv->src_w) / (float)pPriv->dst_w;
|
||||
srcY = pPriv->src_y;
|
||||
srcY += ((pBox->y1 - pPriv->drw_y) *
|
||||
pPriv->src_h) / (float)pPriv->dst_h;
|
||||
|
||||
srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
|
||||
srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
|
||||
|
||||
vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
|
||||
|
||||
vb[0] = (float)dstX;
|
||||
vb[1] = (float)dstY;
|
||||
vb[2] = (float)srcX;
|
||||
vb[3] = (float)srcY;
|
||||
|
||||
vb[4] = (float)dstX;
|
||||
vb[5] = (float)(dstY + dsth);
|
||||
vb[6] = (float)srcX;
|
||||
vb[7] = (float)(srcY + srch);
|
||||
|
||||
vb[8] = (float)(dstX + dstw);
|
||||
vb[9] = (float)(dstY + dsth);
|
||||
vb[10] = (float)(srcX + srcw);
|
||||
vb[11] = (float)(srcY + srch);
|
||||
|
||||
radeon_vbo_commit(pScrn, &accel_state->vbo);
|
||||
|
||||
pBox++;
|
||||
}
|
||||
|
||||
evergreen_finish_op(pScrn, 16);
|
||||
|
||||
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
|
||||
}
|
||||
783
src/pcidb/ati_pciids.csv
Normal file
783
src/pcidb/ati_pciids.csv
Normal file
|
|
@ -0,0 +1,783 @@
|
|||
"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name"
|
||||
"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24)"
|
||||
"0x3151","RV380_3151","RV380",,,,,,"ATI FireMV 2400"
|
||||
"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24)"
|
||||
"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL"
|
||||
"0x3155","RV380_3155","RV380",1,,,,,"ATI FireMV 2400"
|
||||
"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380)"
|
||||
"0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380)"
|
||||
"0x4136","RS100_4136","RS100",,1,,,1,"ATI Radeon IGP320 (A3)"
|
||||
"0x4137","RS200_4137","RS200",,1,,,1,"ATI Radeon IGP330/340/350 (A4)"
|
||||
"0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500"
|
||||
"0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500"
|
||||
"0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX"
|
||||
"0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1"
|
||||
"0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE"
|
||||
"0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800"
|
||||
"0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800"
|
||||
"0x414B","R350_AK","R350",,,,,,"ATI FireGL X2"
|
||||
"0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600"
|
||||
"0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE"
|
||||
"0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT"
|
||||
"0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600"
|
||||
"0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2"
|
||||
"0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650"
|
||||
"0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360"
|
||||
"0x4158","MACH32","MACH32",,,,,,
|
||||
"0x4237","RS250_4237","RS200",,1,,,1,"ATI Radeon 7000 IGP (A4+)"
|
||||
"0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW"
|
||||
"0x4336","RS100_4336","RS100",1,1,,,1,"ATI Radeon IGP320M (U1)"
|
||||
"0x4337","RS200_4337","RS200",1,1,,,1,"ATI Radeon IGP330M/340M/350M (U2)"
|
||||
"0x4354","MACH64CT","MACH64",,,,,,
|
||||
"0x4358","MACH64CX","MACH64",,,,,,
|
||||
"0x4437","RS250_4437","RS200",1,1,,,1,"ATI Radeon Mobility 7000 IGP"
|
||||
"0x4554","MACH64ET","MACH64",,,,,,
|
||||
"0x4742","MACH64GB","MACH64",,,,,,
|
||||
"0x4744","MACH64GD","MACH64",,,,,,
|
||||
"0x4749","MACH64GI","MACH64",,,,,,
|
||||
"0x474C","MACH64GL","MACH64",,,,,,
|
||||
"0x474D","MACH64GM","MACH64",,,,,,
|
||||
"0x474E","MACH64GN","MACH64",,,,,,
|
||||
"0x474F","MACH64GO","MACH64",,,,,,
|
||||
"0x4750","MACH64GP","MACH64",,,,,,
|
||||
"0x4751","MACH64GQ","MACH64",,,,,,
|
||||
"0x4752","MACH64GR","MACH64",,,,,,
|
||||
"0x4753","MACH64GS","MACH64",,,,,,
|
||||
"0x4754","MACH64GT","MACH64",,,,,,
|
||||
"0x4755","MACH64GU","MACH64",,,,,,
|
||||
"0x4756","MACH64GV","MACH64",,,,,,
|
||||
"0x4757","MACH64GW","MACH64",,,,,,
|
||||
"0x4758","MACH64GX","MACH64",,,,,,
|
||||
"0x4759","MACH64GY","MACH64",,,,,,
|
||||
"0x475A","MACH64GZ","MACH64",,,,,,
|
||||
"0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO"
|
||||
"0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000"
|
||||
"0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420)"
|
||||
"0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420)"
|
||||
"0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420)"
|
||||
"0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420)"
|
||||
"0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420)"
|
||||
"0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420)"
|
||||
"0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18)"
|
||||
"0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420)"
|
||||
"0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420)"
|
||||
"0x4A54","R420_JT","R420",,,,,,"ATI Radeon X800 VE (R420)"
|
||||
"0x4B48","R481_4B48","R420",,,,,,"ATI Radeon X850 (R480)"
|
||||
"0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480)"
|
||||
"0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480)"
|
||||
"0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480)"
|
||||
"0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480)"
|
||||
"0x4C42","MACH64LB","MACH64",,,,,,
|
||||
"0x4C44","MACH64LD","MACH64",,,,,,
|
||||
"0x4C45","RAGE128LE","R128",,,,,,
|
||||
"0x4C46","RAGE128LF","R128",,,,,,
|
||||
"0x4C47","MACH64LG","MACH64",,,,,,
|
||||
"0x4C49","MACH64LI","MACH64",,,,,,
|
||||
"0x4C4D","MACH64LM","MACH64",,,,,,
|
||||
"0x4C4E","MACH64LN","MACH64",,,,,,
|
||||
"0x4C50","MACH64LP","MACH64",,,,,,
|
||||
"0x4C51","MACH64LQ","MACH64",,,,,,
|
||||
"0x4C52","MACH64LR","MACH64",,,,,,
|
||||
"0x4C53","MACH64LS","MACH64",,,,,,
|
||||
"0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7"
|
||||
"0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7"
|
||||
"0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6"
|
||||
"0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6"
|
||||
"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9)"
|
||||
"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9)"
|
||||
"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9)"
|
||||
"0x4C6E","RV280_4C6E","RV280",1,,,,,"ATI FireMV 2400"
|
||||
"0x4D46","RAGE128MF","R128",,,,,,
|
||||
"0x4D4C","RAGE128ML","R128",,,,,,
|
||||
"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro"
|
||||
"0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro"
|
||||
"0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX"
|
||||
"0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1"
|
||||
"0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO"
|
||||
"0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800"
|
||||
"0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2"
|
||||
"0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT"
|
||||
"0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11)"
|
||||
"0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10)"
|
||||
"0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11)"
|
||||
"0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10)"
|
||||
"0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10)"
|
||||
"0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11)"
|
||||
"0x5041","RAGE128PA","R128",,,,,,
|
||||
"0x5042","RAGE128PB","R128",,,,,,
|
||||
"0x5043","RAGE128PC","R128",,,,,,
|
||||
"0x5044","RAGE128PD","R128",,,,,,
|
||||
"0x5045","RAGE128PE","R128",,,,,,
|
||||
"0x5046","RAGE128PF","R128",,,,,,
|
||||
"0x5047","RAGE128PG","R128",,,,,,
|
||||
"0x5048","RAGE128PH","R128",,,,,,
|
||||
"0x5049","RAGE128PI","R128",,,,,,
|
||||
"0x504A","RAGE128PJ","R128",,,,,,
|
||||
"0x504B","RAGE128PK","R128",,,,,,
|
||||
"0x504C","RAGE128PL","R128",,,,,,
|
||||
"0x504D","RAGE128PM","R128",,,,,,
|
||||
"0x504E","RAGE128PN","R128",,,,,,
|
||||
"0x504F","RAGE128PO","R128",,,,,,
|
||||
"0x5050","RAGE128PP","R128",,,,,,
|
||||
"0x5051","RAGE128PQ","R128",,,,,,
|
||||
"0x5052","RAGE128PR","R128",,,,,,
|
||||
"0x5053","RAGE128PS","R128",,,,,,
|
||||
"0x5054","RAGE128PT","R128",,,,,,
|
||||
"0x5055","RAGE128PU","R128",,,,,,
|
||||
"0x5056","RAGE128PV","R128",,,,,,
|
||||
"0x5057","RAGE128PW","R128",,,,,,
|
||||
"0x5058","RAGE128PX","R128",,,,,,
|
||||
"0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon"
|
||||
"0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon"
|
||||
"0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon"
|
||||
"0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon"
|
||||
"0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800"
|
||||
"0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500"
|
||||
"0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100"
|
||||
"0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500"
|
||||
"0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500"
|
||||
"0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000"
|
||||
"0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000"
|
||||
"0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000"
|
||||
"0x5245","RAGE128RE","R128",,,,,,
|
||||
"0x5246","RAGE128RF","R128",,,,,,
|
||||
"0x5247","RAGE128RG","R128",,,,,,
|
||||
"0x524B","RAGE128RK","R128",,,,,,
|
||||
"0x524C","RAGE128RL","R128",,,,,,
|
||||
"0x5345","RAGE128SE","R128",,,,,,
|
||||
"0x5346","RAGE128SF","R128",,,,,,
|
||||
"0x5347","RAGE128SG","R128",,,,,,
|
||||
"0x5348","RAGE128SH","R128",,,,,,
|
||||
"0x534B","RAGE128SK","R128",,,,,,
|
||||
"0x534C","RAGE128SL","R128",,,,,,
|
||||
"0x534D","RAGE128SM","R128",,,,,,
|
||||
"0x534E","RAGE128SN","R128",,,,,,
|
||||
"0x5446","RAGE128TF","R128",,,,,,
|
||||
"0x544C","RAGE128TL","R128",,,,,,
|
||||
"0x5452","RAGE128TR","R128",,,,,,
|
||||
"0x5453","RAGE128TS","R128",,,,,,
|
||||
"0x5454","RAGE128TT","R128",,,,,,
|
||||
"0x5455","RAGE128TU","R128",,,,,,
|
||||
"0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22)"
|
||||
"0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C)"
|
||||
"0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL"
|
||||
"0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423)"
|
||||
"0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423)"
|
||||
"0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423)"
|
||||
"0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423)"
|
||||
"0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430)"
|
||||
"0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430)"
|
||||
"0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430)"
|
||||
"0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430)"
|
||||
"0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423)"
|
||||
"0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423)"
|
||||
"0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423)"
|
||||
"0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423)"
|
||||
"0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26)"
|
||||
"0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26)"
|
||||
"0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26)"
|
||||
"0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26)"
|
||||
"0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26)"
|
||||
"0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX"
|
||||
"0x5654","MACH64VT","MACH64",,,,,,
|
||||
"0x5655","MACH64VU","MACH64",,,,,,
|
||||
"0x5656","MACH64VV","MACH64",,,,,,
|
||||
"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5)"
|
||||
"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3)"
|
||||
"0x5954","RS480_5954","RS480",,1,,,1,"ATI Radeon XPRESS 200"
|
||||
"0x5955","RS480_5955","RS480",1,1,,,1,"ATI Radeon XPRESS 200M"
|
||||
"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250"
|
||||
"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200"
|
||||
"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200"
|
||||
"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE"
|
||||
"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200"
|
||||
"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000"
|
||||
"0x5974","RS482_5974","RS480",1,1,,,1,"ATI Radeon XPRESS 200"
|
||||
"0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M"
|
||||
"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200"
|
||||
"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M"
|
||||
"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200"
|
||||
"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M"
|
||||
"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370)"
|
||||
"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370)"
|
||||
"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370)"
|
||||
"0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370)"
|
||||
"0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370)"
|
||||
"0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+)"
|
||||
"0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+)"
|
||||
"0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28)"
|
||||
"0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28)"
|
||||
"0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28)"
|
||||
"0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850"
|
||||
"0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480)"
|
||||
"0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480)"
|
||||
"0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480)"
|
||||
"0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480)"
|
||||
"0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480)"
|
||||
"0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423)"
|
||||
"0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410)"
|
||||
"0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410)"
|
||||
"0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410)"
|
||||
"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410)"
|
||||
"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410)"
|
||||
"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410)"
|
||||
"0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT"
|
||||
"0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800"
|
||||
"0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200"
|
||||
"0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200"
|
||||
"0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300"
|
||||
"0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100"
|
||||
"0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800"
|
||||
"0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300"
|
||||
"0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350"
|
||||
"0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600"
|
||||
"0x7141","RV515_7141","RV515",,,,,,"ATI RV505"
|
||||
"0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550"
|
||||
"0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550"
|
||||
"0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL"
|
||||
"0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400"
|
||||
"0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550"
|
||||
"0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit"
|
||||
"0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300"
|
||||
"0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300"
|
||||
"0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300"
|
||||
"0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300"
|
||||
"0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300"
|
||||
"0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300"
|
||||
"0x714F","RV515_714F","RV515",,,,,,"ATI RV505"
|
||||
"0x7151","RV515_7151","RV515",,,,,,"ATI RV505"
|
||||
"0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300"
|
||||
"0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350"
|
||||
"0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300"
|
||||
"0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit"
|
||||
"0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550"
|
||||
"0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600"
|
||||
"0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550"
|
||||
"0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450"
|
||||
"0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550"
|
||||
"0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300"
|
||||
"0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300"
|
||||
"0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350"
|
||||
"0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350"
|
||||
"0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450"
|
||||
"0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300"
|
||||
"0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550"
|
||||
"0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350"
|
||||
"0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250"
|
||||
"0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit"
|
||||
"0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600"
|
||||
"0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650"
|
||||
"0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600"
|
||||
"0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600"
|
||||
"0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200"
|
||||
"0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600"
|
||||
"0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650"
|
||||
"0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650"
|
||||
"0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600"
|
||||
"0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro"
|
||||
"0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400"
|
||||
"0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250"
|
||||
"0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700"
|
||||
"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT"
|
||||
"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200"
|
||||
"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700"
|
||||
"0x7200","RV515_7200","RV515",,,,,,"ATI Radeon X2300HD"
|
||||
"0x7210","RV515_7210","RV515",1,,,,,"ATI Mobility Radeon HD 2300"
|
||||
"0x7211","RV515_7211","RV515",1,,,,,"ATI Mobility Radeon HD 2300"
|
||||
"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950"
|
||||
"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950"
|
||||
"0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor"
|
||||
"0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900"
|
||||
"0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950"
|
||||
"0x7281","RV560_7281","RV560",,,,,,"ATI RV560"
|
||||
"0x7283","RV560_7283","RV560",,,,,,"ATI RV560"
|
||||
"0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900"
|
||||
"0x7287","RV560_7287","RV560",,,,,,"ATI RV560"
|
||||
"0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT"
|
||||
"0x7289","RV570_7289","RV570",,,,,,"ATI RV570"
|
||||
"0x728B","RV570_728B","RV570",,,,,,"ATI RV570"
|
||||
"0x728C","RV570_728C","RV570",,,,,,"ATI FireGL V7400"
|
||||
"0x7290","RV560_7290","RV560",,,,,,"ATI RV560"
|
||||
"0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650"
|
||||
"0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650"
|
||||
"0x7297","RV560_7297","RV560",,,,,,"ATI RV560"
|
||||
"0x7834","RS350_7834","RS300",,1,,,1,"ATI Radeon 9100 PRO IGP"
|
||||
"0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP"
|
||||
"0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200"
|
||||
"0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200"
|
||||
"0x793F","RS600_793F","RS600",,1,,,1,"ATI Radeon X1200"
|
||||
"0x7941","RS600_7941","RS600",,1,,,1,"ATI Radeon X1200"
|
||||
"0x7942","RS600_7942","RS600",,1,,,1,"ATI Radeon X1200"
|
||||
"0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740"
|
||||
"0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M"
|
||||
"0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740"
|
||||
"0x796F","RS740_796F","RS740",,1,,,1,"ATI RS740M"
|
||||
"0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT"
|
||||
"0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT"
|
||||
"0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT"
|
||||
"0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro"
|
||||
"0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT"
|
||||
"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650"
|
||||
"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600"
|
||||
"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600"
|
||||
"0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series"
|
||||
"0x9441","RV770_9441","RV770",,,,,,"ATI Radeon HD 4870 x2"
|
||||
"0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series"
|
||||
"0x9443","RV770_9443","RV770",,,,,,"ATI Radeon HD 4850 x2"
|
||||
"0x9444","RV770_9444","RV770",,,,,,"ATI FirePro V8750 (FireGL)"
|
||||
"0x9446","RV770_9446","RV770",,,,,,"ATI FirePro V7760 (FireGL)"
|
||||
"0x944A","RV770_944A","RV770",1,,,,,"ATI Mobility RADEON HD 4850"
|
||||
"0x944B","RV770_944B","RV770",1,,,,,"ATI Mobility RADEON HD 4850 X2"
|
||||
"0x944C","RV770_944C","RV770",,,,,,"ATI Radeon 4800 Series"
|
||||
"0x944E","RV770_944E","RV770",,,,,,"ATI FirePro RV770"
|
||||
"0x9450","RV770_9450","RV770",,,,,,"AMD FireStream 9270"
|
||||
"0x9452","RV770_9452","RV770",,,,,,"AMD FireStream 9250"
|
||||
"0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)"
|
||||
"0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870"
|
||||
"0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98"
|
||||
"0x945E","RV770_945E","RV770",1,,,,,"ATI Mobility RADEON HD 4870"
|
||||
"0x9460","RV790_9460","RV770",,,,,,"ATI Radeon 4800 Series"
|
||||
"0x9462","RV790_9462","RV770",,,,,,"ATI Radeon 4800 Series"
|
||||
"0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750"
|
||||
"0x946B","RV770_946B","RV770",1,,,,,"ATI M98"
|
||||
"0x947A","RV770_947A","RV770",1,,,,,"ATI M98"
|
||||
"0x947B","RV770_947B","RV770",1,,,,,"ATI M98"
|
||||
"0x9480","RV730_9480","RV730",1,,,,,"ATI Mobility Radeon HD 4650"
|
||||
"0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)"
|
||||
"0x9488","RV730_9488","RV730",1,,,,,"ATI Mobility Radeon HD 4670"
|
||||
"0x9489","RV730_9489","RV730",1,,,,,"ATI FirePro M5750"
|
||||
"0x948A","RV730_948A","RV730",1,,,,,"ATI Mobility Radeon HD 4670"
|
||||
"0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)"
|
||||
"0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]"
|
||||
"0x9491","RV730_9491","RV730",,,,,,"ATI RADEON E4600"
|
||||
"0x9495","RV730_9495","RV730",,,,,,"ATI Radeon HD 4600 Series"
|
||||
"0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]"
|
||||
"0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)"
|
||||
"0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)"
|
||||
"0x949F","RV730_949F","RV730",,,,,,"ATI FirePro V3750 (FireGL)"
|
||||
"0x94A0","RV740_94A0","RV740",1,,,,,"ATI Mobility Radeon HD 4830"
|
||||
"0x94A1","RV740_94A1","RV740",1,,,,,"ATI Mobility Radeon HD 4850"
|
||||
"0x94A3","RV740_94A3","RV740",1,,,,,"ATI FirePro M7740"
|
||||
"0x94B1","RV740_94B1","RV740",,,,,,"ATI RV740"
|
||||
"0x94B3","RV740_94B3","RV740",,,,,,"ATI Radeon HD 4770"
|
||||
"0x94B4","RV740_94B4","RV740",,,,,,"ATI Radeon HD 4700 Series"
|
||||
"0x94B5","RV740_94B5","RV740",,,,,,"ATI Radeon HD 4770"
|
||||
"0x94B9","RV740_94B9","RV740",1,,,,,"ATI FirePro M5750"
|
||||
"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610"
|
||||
"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT"
|
||||
"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro"
|
||||
"0x94C4","RV610_94C4","RV610",,,,,,"ATI Radeon HD 2400 PRO AGP"
|
||||
"0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000"
|
||||
"0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610"
|
||||
"0x94C7","RV610_94C7","RV610",,,,,,"ATI Radeon HD 2350"
|
||||
"0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT"
|
||||
"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400"
|
||||
"0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400"
|
||||
"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610"
|
||||
"0x94CD","RV610_94CD","RV610",,,,,,"ATI FireMV 2260"
|
||||
"0x9500","RV670_9500","RV670",,,,,,"ATI RV670"
|
||||
"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870"
|
||||
"0x9504","RV670_9504","RV670",1,,,,,"ATI Mobility Radeon HD 3850"
|
||||
"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850"
|
||||
"0x9506","RV670_9506","RV670",1,,,,,"ATI Mobility Radeon HD 3850 X2"
|
||||
"0x9507","RV670_9507","RV670",,,,,,"ATI RV670"
|
||||
"0x9508","RV670_9508","RV670",1,,,,,"ATI Mobility Radeon HD 3870"
|
||||
"0x9509","RV670_9509","RV670",1,,,,,"ATI Mobility Radeon HD 3870 X2"
|
||||
"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2"
|
||||
"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700"
|
||||
"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850"
|
||||
"0x9517","RV670_9517","RV670",,,,,,"ATI Radeon HD3690"
|
||||
"0x9519","RV670_9519","RV670",,,,,,"AMD Firestream 9170"
|
||||
"0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550"
|
||||
"0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710"
|
||||
"0x9542","RV710_9542","RV710",,,,,,"ATI Radeon RV710"
|
||||
"0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710"
|
||||
"0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350"
|
||||
"0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series"
|
||||
"0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
|
||||
"0x9555","RV710_9555","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
|
||||
"0x9557","RV710_9557","RV710",1,,,,,"ATI FirePro RG220"
|
||||
"0x955F","RV710_955F","RV710",1,,,,,"ATI Mobility Radeon 4330"
|
||||
"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
|
||||
"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
|
||||
"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
|
||||
"0x9586","RV630_9586","RV630",,,,,,"ATI Radeon HD 2600 XT AGP"
|
||||
"0x9587","RV630_9587","RV630",,,,,,"ATI Radeon HD 2600 Pro AGP"
|
||||
"0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT"
|
||||
"0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro"
|
||||
"0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630"
|
||||
"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini Mobility Radeon HD 2600 XT"
|
||||
"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
|
||||
"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
|
||||
"0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE"
|
||||
"0x958F","RV630_958F","RV630",1,,,,,"ATI Mobility FireGL Graphics Processor"
|
||||
"0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470"
|
||||
"0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430"
|
||||
"0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series"
|
||||
"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450"
|
||||
"0x95C6","RV620_95C6","RV620",,,,,,"ATI Radeon HD 3450"
|
||||
"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430"
|
||||
"0x95C9","RV620_95C9","RV620",,,,,,"ATI Radeon HD 3450"
|
||||
"0x95CC","RV620_95CC","RV620",,,,,,"ATI FirePro V3700"
|
||||
"0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450"
|
||||
"0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260"
|
||||
"0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260"
|
||||
"0x9590","RV635_9590","RV635",,,,,,"ATI Radeon HD 3600 Series"
|
||||
"0x9596","RV635_9596","RV635",,,,,,"ATI Radeon HD 3650 AGP"
|
||||
"0x9597","RV635_9597","RV635",,,,,,"ATI Radeon HD 3600 PRO"
|
||||
"0x9598","RV635_9598","RV635",,,,,,"ATI Radeon HD 3600 XT"
|
||||
"0x9599","RV635_9599","RV635",,,,,,"ATI Radeon HD 3600 PRO"
|
||||
"0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650"
|
||||
"0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670"
|
||||
"0x9595","RV635_9595","RV635",1,,,,,"ATI Mobility FireGL V5700"
|
||||
"0x959B","RV635_959B","RV635",1,,,,,"ATI Mobility FireGL V5725"
|
||||
"0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
|
||||
"0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
|
||||
"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
|
||||
"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
|
||||
"0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics"
|
||||
"0x9615","RS780_9615","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
|
||||
"0x9616","RS780_9616","RS780",,1,,,1,"ATI Radeon 3000 Graphics"
|
||||
"0x9640","SUMO_9640","SUMO",,1,,,1,"SUMO"
|
||||
"0x9641","SUMO_9641","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9642","SUMO2_9642","SUMO2",,1,,,1,"SUMO2"
|
||||
"0x9643","SUMO2_9643","SUMO2",1,1,,,1,"SUMO2"
|
||||
"0x9644","SUMO2_9644","SUMO2",,1,,,1,"SUMO2"
|
||||
"0x9645","SUMO2_9645","SUMO2",1,1,,,1,"SUMO2"
|
||||
"0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9649","SUMO2_9649","SUMO2",1,1,,,1,"SUMO2"
|
||||
"0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO"
|
||||
"0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO"
|
||||
"0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO"
|
||||
"0x964E","SUMO_964E","SUMO",1,1,,,1,"SUMO"
|
||||
"0x964F","SUMO_964F","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD 4200"
|
||||
"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon 4100"
|
||||
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
|
||||
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
|
||||
"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290"
|
||||
"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4250"
|
||||
"0x9802","PALM_9802","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
|
||||
"0x9803","PALM_9803","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
|
||||
"0x9804","PALM_9804","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
|
||||
"0x9805","PALM_9805","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
|
||||
"0x9806","PALM_9806","PALM",,1,,,1,"AMD Radeon HD 6300 Series Graphics"
|
||||
"0x9807","PALM_9807","PALM",,1,,,1,"AMD Radeon HD 6200 Series Graphics"
|
||||
"0x9808","PALM_9808","PALM",,1,,,1,"PALM"
|
||||
"0x9809","PALM_9809","PALM",,1,,,1,"PALM"
|
||||
"0x980A","PALM_980A","PALM",,1,,,1,"PALM"
|
||||
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
|
||||
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x688A","CYPRESS_688A","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x688C","CYPRESS_688C","CYPRESS",,,,,,"AMD Firestream 9370"
|
||||
"0x688D","CYPRESS_688D","CYPRESS",,,,,,"AMD Firestream 9350"
|
||||
"0x6898","CYPRESS_6898","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
|
||||
"0x6899","CYPRESS_6899","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
|
||||
"0x689B","CYPRESS_689B","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
|
||||
"0x689E","CYPRESS_689E","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
|
||||
"0x689C","HEMLOCK_689C","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
|
||||
"0x689D","HEMLOCK_689D","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
|
||||
"0x68A0","JUNIPER_68A0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
|
||||
"0x68A1","JUNIPER_68A1","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
|
||||
"0x68A8","JUNIPER_68A8","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68A9","JUNIPER_68A9","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68B0","JUNIPER_68B0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
|
||||
"0x68B8","JUNIPER_68B8","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
|
||||
"0x68B9","JUNIPER_68B9","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
|
||||
"0x68BA","JUNIPER_68BA","JUNIPER",,,,,,"ATI Radeon HD 6700 Series"
|
||||
"0x68BE","JUNIPER_68BE","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
|
||||
"0x68BF","JUNIPER_68BF","JUNIPER",,,,,,"ATI Radeon HD 6700 Series"
|
||||
"0x68C0","REDWOOD_68C0","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
|
||||
"0x68C1","REDWOOD_68C1","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
|
||||
"0x68C7","REDWOOD_68C7","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5570"
|
||||
"0x68C8","REDWOOD_68C8","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68C9","REDWOOD_68C9","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68D8","REDWOOD_68D8","REDWOOD",,,,,,"ATI Radeon HD 5670"
|
||||
"0x68D9","REDWOOD_68D9","REDWOOD",,,,,,"ATI Radeon HD 5570"
|
||||
"0x68DA","REDWOOD_68DA","REDWOOD",,,,,,"ATI Radeon HD 5500 Series"
|
||||
"0x68DE","REDWOOD_68DE","REDWOOD",,,,,,"REDWOOD"
|
||||
"0x68E0","CEDAR_68E0","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
|
||||
"0x68E1","CEDAR_68E1","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
|
||||
"0x68E4","CEDAR_68E4","CEDAR",1,,,,,"ATI Mobility Radeon Graphics"
|
||||
"0x68E5","CEDAR_68E5","CEDAR",1,,,,,"ATI Mobility Radeon Graphics"
|
||||
"0x68E8","CEDAR_68E8","CEDAR",,,,,,"CEDAR"
|
||||
"0x68E9","CEDAR_68E9","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68F1","CEDAR_68F1","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
|
||||
"0x68F2","CEDAR_68F2","CEDAR",,,,,,"ATI FirePro 2270"
|
||||
"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
|
||||
"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
|
||||
"0x68FA","CEDAR_68FA","CEDAR",,,,,,"CEDAR"
|
||||
"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
|
||||
"0x6700","CAYMAN_6700","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6701","CAYMAN_6701","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6702","CAYMAN_6702","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6703","CAYMAN_6703","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6704","CAYMAN_6704","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6705","CAYMAN_6705","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6706","CAYMAN_6706","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6707","CAYMAN_6707","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6708","CAYMAN_6708","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6709","CAYMAN_6709","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6718","CAYMAN_6718","CAYMAN",,,,,,"AMD Radeon HD 6900 Series"
|
||||
"0x6719","CAYMAN_6719","CAYMAN",,,,,,"AMD Radeon HD 6900 Series"
|
||||
"0x671C","CAYMAN_671C","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x671D","CAYMAN_671D","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x671F","CAYMAN_671F","CAYMAN",,,,,,"CAYMAN"
|
||||
"0x6720","BARTS_6720","BARTS",1,,,,,"AMD Radeon HD 6900M Series"
|
||||
"0x6721","BARTS_6721","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
|
||||
"0x6722","BARTS_6722","BARTS",,,,,,"BARTS"
|
||||
"0x6723","BARTS_6723","BARTS",,,,,,"BARTS"
|
||||
"0x6724","BARTS_6724","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
|
||||
"0x6725","BARTS_6725","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
|
||||
"0x6726","BARTS_6726","BARTS",,,,,,"BARTS"
|
||||
"0x6727","BARTS_6727","BARTS",,,,,,"BARTS"
|
||||
"0x6728","BARTS_6728","BARTS",,,,,,"BARTS"
|
||||
"0x6729","BARTS_6729","BARTS",,,,,,"BARTS"
|
||||
"0x6738","BARTS_6738","BARTS",,,,,,"AMD Radeon HD 6800 Series"
|
||||
"0x6739","BARTS_6739","BARTS",,,,,,"AMD Radeon HD 6800 Series"
|
||||
"0x673E","BARTS_673E","BARTS",,,,,,"AMD Radeon HD 6700 Series"
|
||||
"0x6740","TURKS_6740","TURKS",1,,,,,"TURKS"
|
||||
"0x6741","TURKS_6741","TURKS",1,,,,,"TURKS"
|
||||
"0x6742","TURKS_6742","TURKS",1,,,,,"TURKS"
|
||||
"0x6743","TURKS_6743","TURKS",1,,,,,"TURKS"
|
||||
"0x6744","TURKS_6744","TURKS",1,,,,,"TURKS"
|
||||
"0x6745","TURKS_6745","TURKS",1,,,,,"TURKS"
|
||||
"0x6746","TURKS_6746","TURKS",,,,,,"TURKS"
|
||||
"0x6747","TURKS_6747","TURKS",,,,,,"TURKS"
|
||||
"0x6748","TURKS_6748","TURKS",,,,,,"TURKS"
|
||||
"0x6749","TURKS_6749","TURKS",,,,,,"TURKS"
|
||||
"0x674A","TURKS_674A","TURKS",,,,,,"TURKS"
|
||||
"0x6750","TURKS_6750","TURKS",,,,,,"TURKS"
|
||||
"0x6751","TURKS_6751","TURKS",,,,,,"TURKS"
|
||||
"0x6758","TURKS_6758","TURKS",,,,,,"TURKS"
|
||||
"0x6759","TURKS_6759","TURKS",,,,,,"TURKS"
|
||||
"0x675B","TURKS_675B","TURKS",,,,,,"TURKS"
|
||||
"0x675D","TURKS_675D","TURKS",,,,,,"TURKS"
|
||||
"0x675F","TURKS_675F","TURKS",,,,,,"TURKS"
|
||||
"0x6840","TURKS_6840","TURKS",1,,,,,"TURKS"
|
||||
"0x6841","TURKS_6841","TURKS",1,,,,,"TURKS"
|
||||
"0x6842","TURKS_6842","TURKS",1,,,,,"TURKS"
|
||||
"0x6843","TURKS_6843","TURKS",1,,,,,"TURKS"
|
||||
"0x6849","TURKS_6849","TURKS",,,,,,"TURKS"
|
||||
"0x6850","TURKS_6850","TURKS",,,,,,"TURKS"
|
||||
"0x6858","TURKS_6858","TURKS",,,,,,"TURKS"
|
||||
"0x6859","TURKS_6859","TURKS",,,,,,"TURKS"
|
||||
"0x6760","CAICOS_6760","CAICOS",1,,,,,"CAICOS"
|
||||
"0x6761","CAICOS_6761","CAICOS",1,,,,,"CAICOS"
|
||||
"0x6762","CAICOS_6762","CAICOS",,,,,,"CAICOS"
|
||||
"0x6763","CAICOS_6763","CAICOS",,,,,,"CAICOS"
|
||||
"0x6764","CAICOS_6764","CAICOS",1,,,,,"CAICOS"
|
||||
"0x6765","CAICOS_6765","CAICOS",1,,,,,"CAICOS"
|
||||
"0x6766","CAICOS_6766","CAICOS",,,,,,"CAICOS"
|
||||
"0x6767","CAICOS_6767","CAICOS",,,,,,"CAICOS"
|
||||
"0x6768","CAICOS_6768","CAICOS",,,,,,"CAICOS"
|
||||
"0x6770","CAICOS_6770","CAICOS",,,,,,"CAICOS"
|
||||
"0x6771","CAICOS_6771","CAICOS",,,,,,"CAICOS"
|
||||
"0x6772","CAICOS_6772","CAICOS",,,,,,"CAICOS"
|
||||
"0x6778","CAICOS_6778","CAICOS",,,,,,"CAICOS"
|
||||
"0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS"
|
||||
"0x677B","CAICOS_677B","CAICOS",,,,,,"CAICOS"
|
||||
"0x9900","ARUBA_9900","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9901","ARUBA_9901","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9903","ARUBA_9903","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9904","ARUBA_9904","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9905","ARUBA_9905","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9906","ARUBA_9906","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9907","ARUBA_9907","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9908","ARUBA_9908","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9909","ARUBA_9909","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x990A","ARUBA_990A","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x990B","ARUBA_990B","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x990C","ARUBA_990C","ARUBA",,1,,,,"ARUBA"
|
||||
"0x990D","ARUBA_990D","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x990E","ARUBA_990E","ARUBA",,1,,,,"ARUBA"
|
||||
"0x990F","ARUBA_990F","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9910","ARUBA_9910","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9913","ARUBA_9913","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9917","ARUBA_9917","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9918","ARUBA_9918","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9919","ARUBA_9919","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9990","ARUBA_9990","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9991","ARUBA_9991","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9992","ARUBA_9992","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9993","ARUBA_9993","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9994","ARUBA_9994","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9995","ARUBA_9995","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9996","ARUBA_9996","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9997","ARUBA_9997","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x9998","ARUBA_9998","ARUBA",,1,,,,"ARUBA"
|
||||
"0x9999","ARUBA_9999","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x999A","ARUBA_999A","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x999B","ARUBA_999B","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x999C","ARUBA_999C","ARUBA",,1,,,,"ARUBA"
|
||||
"0x999D","ARUBA_999D","ARUBA",,1,,,,"ARUBA"
|
||||
"0x99A0","ARUBA_99A0","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x99A2","ARUBA_99A2","ARUBA",1,1,,,,"ARUBA"
|
||||
"0x99A4","ARUBA_99A4","ARUBA",,1,,,,"ARUBA"
|
||||
"0x6780","TAHITI_6780","TAHITI",,,,,,"TAHITI"
|
||||
"0x6784","TAHITI_6784","TAHITI",,,,,,"TAHITI"
|
||||
"0x6788","TAHITI_6788","TAHITI",,,,,,"TAHITI"
|
||||
"0x678A","TAHITI_678A","TAHITI",,,,,,"TAHITI"
|
||||
"0x6790","TAHITI_6790","TAHITI",,,,,,"TAHITI"
|
||||
"0x6791","TAHITI_6791","TAHITI",,,,,,"TAHITI"
|
||||
"0x6792","TAHITI_6792","TAHITI",,,,,,"TAHITI"
|
||||
"0x6798","TAHITI_6798","TAHITI",,,,,,"TAHITI"
|
||||
"0x6799","TAHITI_6799","TAHITI",,,,,,"TAHITI"
|
||||
"0x679A","TAHITI_679A","TAHITI",,,,,,"TAHITI"
|
||||
"0x679B","TAHITI_679B","TAHITI",,,,,,"TAHITI"
|
||||
"0x679E","TAHITI_679E","TAHITI",,,,,,"TAHITI"
|
||||
"0x679F","TAHITI_679F","TAHITI",,,,,,"TAHITI"
|
||||
"0x6800","PITCAIRN_6800","PITCAIRN",1,,,,,"PITCAIRN"
|
||||
"0x6801","PITCAIRN_6801","PITCAIRN",1,,,,,"PITCAIRN"
|
||||
"0x6802","PITCAIRN_6802","PITCAIRN",1,,,,,"PITCAIRN"
|
||||
"0x6806","PITCAIRN_6806","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6808","PITCAIRN_6808","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6809","PITCAIRN_6809","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6810","PITCAIRN_6810","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6811","PITCAIRN_6811","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6816","PITCAIRN_6816","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6817","PITCAIRN_6817","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6818","PITCAIRN_6818","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6819","PITCAIRN_6819","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x684C","PITCAIRN_684C","PITCAIRN",,,,,,"PITCAIRN"
|
||||
"0x6820","VERDE_6820","VERDE",1,,,,,"VERDE"
|
||||
"0x6821","VERDE_6821","VERDE",1,,,,,"VERDE"
|
||||
"0x6822","VERDE_6822","VERDE",1,,,,,"VERDE"
|
||||
"0x6823","VERDE_6823","VERDE",1,,,,,"VERDE"
|
||||
"0x6824","VERDE_6824","VERDE",1,,,,,"VERDE"
|
||||
"0x6825","VERDE_6825","VERDE",1,,,,,"VERDE"
|
||||
"0x6826","VERDE_6826","VERDE",1,,,,,"VERDE"
|
||||
"0x6827","VERDE_6827","VERDE",1,,,,,"VERDE"
|
||||
"0x6828","VERDE_6828","VERDE",,,,,,"VERDE"
|
||||
"0x6829","VERDE_6829","VERDE",,,,,,"VERDE"
|
||||
"0x682A","VERDE_682A","VERDE",1,,,,,"VERDE"
|
||||
"0x682B","VERDE_682B","VERDE",1,,,,,"VERDE"
|
||||
"0x682C","VERDE_682C","VERDE",,,,,,"VERDE"
|
||||
"0x682D","VERDE_682D","VERDE",1,,,,,"VERDE"
|
||||
"0x682F","VERDE_682F","VERDE",1,,,,,"VERDE"
|
||||
"0x6830","VERDE_6830","VERDE",1,,,,,"VERDE"
|
||||
"0x6831","VERDE_6831","VERDE",1,,,,,"VERDE"
|
||||
"0x6835","VERDE_6835","VERDE",,,,,,"VERDE"
|
||||
"0x6837","VERDE_6837","VERDE",,,,,,"VERDE"
|
||||
"0x6838","VERDE_6838","VERDE",,,,,,"VERDE"
|
||||
"0x6839","VERDE_6839","VERDE",,,,,,"VERDE"
|
||||
"0x683B","VERDE_683B","VERDE",,,,,,"VERDE"
|
||||
"0x683D","VERDE_683D","VERDE",,,,,,"VERDE"
|
||||
"0x683F","VERDE_683F","VERDE",,,,,,"VERDE"
|
||||
"0x6600","OLAND_6600","OLAND",1,,,,,"OLAND"
|
||||
"0x6601","OLAND_6601","OLAND",1,,,,,"OLAND"
|
||||
"0x6602","OLAND_6602","OLAND",1,,,,,"OLAND"
|
||||
"0x6603","OLAND_6603","OLAND",1,,,,,"OLAND"
|
||||
"0x6604","OLAND_6604","OLAND",1,,,,,"OLAND"
|
||||
"0x6605","OLAND_6605","OLAND",1,,,,,"OLAND"
|
||||
"0x6606","OLAND_6606","OLAND",1,,,,,"OLAND"
|
||||
"0x6607","OLAND_6607","OLAND",1,,,,,"OLAND"
|
||||
"0x6608","OLAND_6608","OLAND",,,,,,"OLAND"
|
||||
"0x6610","OLAND_6610","OLAND",,,,,,"OLAND"
|
||||
"0x6611","OLAND_6611","OLAND",,,,,,"OLAND"
|
||||
"0x6613","OLAND_6613","OLAND",,,,,,"OLAND"
|
||||
"0x6617","OLAND_6617","OLAND",1,,,,,"OLAND"
|
||||
"0x6620","OLAND_6620","OLAND",1,,,,,"OLAND"
|
||||
"0x6621","OLAND_6621","OLAND",1,,,,,"OLAND"
|
||||
"0x6623","OLAND_6623","OLAND",1,,,,,"OLAND"
|
||||
"0x6631","OLAND_6631","OLAND",,,,,,"OLAND"
|
||||
"0x6660","HAINAN_6660","HAINAN",1,,,,,"HAINAN"
|
||||
"0x6663","HAINAN_6663","HAINAN",1,,,,,"HAINAN"
|
||||
"0x6664","HAINAN_6664","HAINAN",1,,,,,"HAINAN"
|
||||
"0x6665","HAINAN_6665","HAINAN",1,,,,,"HAINAN"
|
||||
"0x6667","HAINAN_6667","HAINAN",1,,,,,"HAINAN"
|
||||
"0x666F","HAINAN_666F","HAINAN",1,,,,,"HAINAN"
|
||||
"0x6640","BONAIRE_6640","BONAIRE",1,,,,,"BONAIRE"
|
||||
"0x6641","BONAIRE_6641","BONAIRE",1,,,,,"BONAIRE"
|
||||
"0x6646","BONAIRE_6646","BONAIRE",1,,,,,"BONAIRE"
|
||||
"0x6647","BONAIRE_6647","BONAIRE",1,,,,,"BONAIRE"
|
||||
"0x6649","BONAIRE_6649","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x6650","BONAIRE_6650","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x6651","BONAIRE_6651","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x6658","BONAIRE_6658","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x665C","BONAIRE_665C","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x665D","BONAIRE_665D","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x665F","BONAIRE_665F","BONAIRE",,,,,,"BONAIRE"
|
||||
"0x9830","KABINI_9830","KABINI",1,1,,,1,"KABINI"
|
||||
"0x9831","KABINI_9831","KABINI",,1,,,1,"KABINI"
|
||||
"0x9832","KABINI_9832","KABINI",1,1,,,1,"KABINI"
|
||||
"0x9833","KABINI_9833","KABINI",,1,,,1,"KABINI"
|
||||
"0x9834","KABINI_9834","KABINI",1,1,,,1,"KABINI"
|
||||
"0x9835","KABINI_9835","KABINI",,1,,,1,"KABINI"
|
||||
"0x9836","KABINI_9836","KABINI",1,1,,,1,"KABINI"
|
||||
"0x9837","KABINI_9837","KABINI",,1,,,1,"KABINI"
|
||||
"0x9838","KABINI_9838","KABINI",1,1,,,1,"KABINI"
|
||||
"0x9839","KABINI_9839","KABINI",1,1,,,1,"KABINI"
|
||||
"0x983A","KABINI_983A","KABINI",,1,,,1,"KABINI"
|
||||
"0x983B","KABINI_983B","KABINI",1,1,,,1,"KABINI"
|
||||
"0x983C","KABINI_983C","KABINI",,1,,,1,"KABINI"
|
||||
"0x983D","KABINI_983D","KABINI",,1,,,1,"KABINI"
|
||||
"0x983E","KABINI_983E","KABINI",,1,,,1,"KABINI"
|
||||
"0x983F","KABINI_983F","KABINI",,1,,,1,"KABINI"
|
||||
"0x9850","MULLINS_9850","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9851","MULLINS_9851","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9852","MULLINS_9852","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9853","MULLINS_9853","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9854","MULLINS_9854","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9855","MULLINS_9855","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9856","MULLINS_9856","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9857","MULLINS_9857","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9858","MULLINS_9858","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x9859","MULLINS_9859","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985A","MULLINS_985A","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985B","MULLINS_985B","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985C","MULLINS_985C","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985D","MULLINS_985D","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985E","MULLINS_985E","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x985F","MULLINS_985F","MULLINS",1,1,,,1,"MULLINS"
|
||||
"0x1304","KAVERI_1304","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x1305","KAVERI_1305","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1306","KAVERI_1306","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x1307","KAVERI_1307","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1309","KAVERI_1309","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130A","KAVERI_130A","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130B","KAVERI_130B","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130C","KAVERI_130C","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130D","KAVERI_130D","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130E","KAVERI_130E","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130F","KAVERI_130F","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1310","KAVERI_1310","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1311","KAVERI_1311","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1312","KAVERI_1312","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1313","KAVERI_1313","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1315","KAVERI_1315","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1316","KAVERI_1316","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1317","KAVERI_1317","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x1318","KAVERI_1318","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x131B","KAVERI_131B","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x131C","KAVERI_131C","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x131D","KAVERI_131D","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x67A0","HAWAII_67A0","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A1","HAWAII_67A1","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A2","HAWAII_67A2","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A8","HAWAII_67A8","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A9","HAWAII_67A9","HAWAII",,,,,,"HAWAII"
|
||||
"0x67AA","HAWAII_67AA","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B0","HAWAII_67B0","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B1","HAWAII_67B1","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B8","HAWAII_67B8","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B9","HAWAII_67B9","HAWAII",,,,,,"HAWAII"
|
||||
"0x67BA","HAWAII_67BA","HAWAII",,,,,,"HAWAII"
|
||||
"0x67BE","HAWAII_67BE","HAWAII",,,,,,"HAWAII"
|
||||
|
114
src/pcidb/parse_pci_ids.pl
Executable file
114
src/pcidb/parse_pci_ids.pl
Executable file
|
|
@ -0,0 +1,114 @@
|
|||
#!/usr/bin/perl
|
||||
#
|
||||
# Copyright 2007 Red Hat Inc.
|
||||
# This crappy script written by Dave Airlie to avoid hassle of adding
|
||||
# ids in every place.
|
||||
#
|
||||
use strict;
|
||||
use warnings;
|
||||
use Text::CSV_XS;
|
||||
|
||||
my $file = $ARGV[0];
|
||||
|
||||
my $atioutfile = 'ati_pciids_gen.h';
|
||||
my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h';
|
||||
my $radeonpcidevicematchfile = 'radeon_pci_device_match_gen.h';
|
||||
my $radeonchipsetfile = 'radeon_chipset_gen.h';
|
||||
my $radeonchipinfofile = 'radeon_chipinfo_gen.h';
|
||||
|
||||
my %uniquechipsets;
|
||||
my @uniquearray;
|
||||
my $numunique = 0;
|
||||
|
||||
my $csv = Text::CSV_XS->new();
|
||||
|
||||
open (CSV, "<", $file) or die $!;
|
||||
|
||||
open (ATIOUT, ">", $atioutfile) or die;
|
||||
open (PCICHIPSET, ">", $radeonpcichipsetfile) or die;
|
||||
open (PCIDEVICEMATCH, ">", $radeonpcidevicematchfile) or die;
|
||||
open (RADEONCHIPSET, ">", $radeonchipsetfile) or die;
|
||||
open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die;
|
||||
|
||||
print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n";
|
||||
print RADEONCHIPSET "SymTabRec RADEONChipsets[] = {\n";
|
||||
print PCICHIPSET "/* This file is autogenerated please do not edit */\n";
|
||||
print PCICHIPSET "static PciChipsets RADEONPciChipsets[] = {\n";
|
||||
print PCIDEVICEMATCH "/* This file is autogenerated please do not edit */\n";
|
||||
print PCIDEVICEMATCH "static const struct pci_id_match radeon_device_match[] = {\n";
|
||||
print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n";
|
||||
print RADEONCHIPINFO "static RADEONCardInfo RADEONCards[] = {\n";
|
||||
while (<CSV>) {
|
||||
if ($csv->parse($_)) {
|
||||
my @columns = $csv->fields();
|
||||
|
||||
if ((substr($columns[0], 0, 1) ne "#")) {
|
||||
|
||||
print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n";
|
||||
|
||||
if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) {
|
||||
print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n";
|
||||
|
||||
print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n";
|
||||
|
||||
print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n";
|
||||
if (!$uniquechipsets{$columns[8]}) {
|
||||
$uniquearray[$numunique] = $columns[8];
|
||||
$uniquechipsets{$columns[8]} = $numunique++;
|
||||
}
|
||||
|
||||
print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], ";
|
||||
|
||||
if ($columns[3] eq "1") {
|
||||
print RADEONCHIPINFO "1, ";
|
||||
} else {
|
||||
print RADEONCHIPINFO "0, ";
|
||||
}
|
||||
|
||||
if ($columns[4] eq "1") {
|
||||
print RADEONCHIPINFO "1, ";
|
||||
} else {
|
||||
print RADEONCHIPINFO "0, ";
|
||||
}
|
||||
|
||||
if ($columns[5] eq "1") {
|
||||
print RADEONCHIPINFO "1, ";
|
||||
} else {
|
||||
print RADEONCHIPINFO "0, ";
|
||||
}
|
||||
|
||||
if ($columns[6] eq "1") {
|
||||
print RADEONCHIPINFO "1, ";
|
||||
} else {
|
||||
print RADEONCHIPINFO "0, ";
|
||||
}
|
||||
|
||||
if ($columns[7] eq "1") {
|
||||
print RADEONCHIPINFO "1 ";
|
||||
} else {
|
||||
print RADEONCHIPINFO "0 ";
|
||||
}
|
||||
|
||||
print RADEONCHIPINFO "},\n";
|
||||
}
|
||||
}
|
||||
} else {
|
||||
my $err = $csv->error_input;
|
||||
print "Failed to parse line: $err";
|
||||
}
|
||||
}
|
||||
|
||||
print RADEONCHIPINFO "};\n";
|
||||
print RADEONCHIPSET " { -1, NULL }\n};\n\nSymTabRec RADEONUniqueChipsets[] = {\n";
|
||||
foreach (@uniquearray) {
|
||||
print RADEONCHIPSET " { 0, \"$_\" },\n";
|
||||
}
|
||||
print RADEONCHIPSET " { -1, NULL }\n};\n";
|
||||
print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n";
|
||||
print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n";
|
||||
close CSV;
|
||||
close ATIOUT;
|
||||
close PCICHIPSET;
|
||||
close PCIDEVICEMATCH;
|
||||
close RADEONCHIPSET;
|
||||
close RADEONCHIPINFO;
|
||||
2102
src/r600_exa.c
Normal file
2102
src/r600_exa.c
Normal file
File diff suppressed because it is too large
Load diff
134
src/r600_reg.h
Normal file
134
src/r600_reg.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* RadeonHD R6xx, R7xx Register documentation
|
||||
*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2009 Matthias Hopf
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _R600_REG_H_
|
||||
#define _R600_REG_H_
|
||||
|
||||
/*
|
||||
* Register definitions
|
||||
*/
|
||||
|
||||
#include "r600_reg_auto_r6xx.h"
|
||||
#include "r600_reg_r6xx.h"
|
||||
#include "r600_reg_r7xx.h"
|
||||
|
||||
|
||||
/* SET_*_REG offsets + ends */
|
||||
#define SET_CONFIG_REG_offset 0x00008000
|
||||
#define SET_CONFIG_REG_end 0x0000ac00
|
||||
#define SET_CONTEXT_REG_offset 0x00028000
|
||||
#define SET_CONTEXT_REG_end 0x00029000
|
||||
#define SET_ALU_CONST_offset 0x00030000
|
||||
#define SET_ALU_CONST_end 0x00032000
|
||||
#define SET_RESOURCE_offset 0x00038000
|
||||
#define SET_RESOURCE_end 0x0003c000
|
||||
#define SET_SAMPLER_offset 0x0003c000
|
||||
#define SET_SAMPLER_end 0x0003cff0
|
||||
#define SET_CTL_CONST_offset 0x0003cff0
|
||||
#define SET_CTL_CONST_end 0x0003e200
|
||||
#define SET_LOOP_CONST_offset 0x0003e200
|
||||
#define SET_LOOP_CONST_end 0x0003e380
|
||||
#define SET_BOOL_CONST_offset 0x0003e380
|
||||
#define SET_BOOL_CONST_end 0x0003e38c
|
||||
|
||||
|
||||
/* packet3 IT_SURFACE_BASE_UPDATE bits */
|
||||
enum {
|
||||
DEPTH_BASE = (1 << 0),
|
||||
COLOR0_BASE = (1 << 1),
|
||||
COLOR1_BASE = (1 << 2),
|
||||
COLOR2_BASE = (1 << 3),
|
||||
COLOR3_BASE = (1 << 4),
|
||||
COLOR4_BASE = (1 << 5),
|
||||
COLOR5_BASE = (1 << 6),
|
||||
COLOR6_BASE = (1 << 7),
|
||||
COLOR7_BASE = (1 << 8),
|
||||
STRMOUT_BASE0 = (1 << 9),
|
||||
STRMOUT_BASE1 = (1 << 10),
|
||||
STRMOUT_BASE2 = (1 << 11),
|
||||
STRMOUT_BASE3 = (1 << 12),
|
||||
COHER_BASE0 = (1 << 13),
|
||||
COHER_BASE1 = (1 << 14),
|
||||
};
|
||||
|
||||
/* Packet3 commands */
|
||||
enum {
|
||||
IT_NOP = 0x10,
|
||||
IT_INDIRECT_BUFFER_END = 0x17,
|
||||
IT_SET_PREDICATION = 0x20,
|
||||
IT_REG_RMW = 0x21,
|
||||
IT_COND_EXEC = 0x22,
|
||||
IT_PRED_EXEC = 0x23,
|
||||
IT_START_3D_CMDBUF = 0x24,
|
||||
IT_DRAW_INDEX_2 = 0x27,
|
||||
IT_CONTEXT_CONTROL = 0x28,
|
||||
IT_DRAW_INDEX_IMMD_BE = 0x29,
|
||||
IT_INDEX_TYPE = 0x2A,
|
||||
IT_DRAW_INDEX = 0x2B,
|
||||
IT_DRAW_INDEX_AUTO = 0x2D,
|
||||
IT_DRAW_INDEX_IMMD = 0x2E,
|
||||
IT_NUM_INSTANCES = 0x2F,
|
||||
IT_STRMOUT_BUFFER_UPDATE = 0x34,
|
||||
IT_INDIRECT_BUFFER_MP = 0x38,
|
||||
IT_MEM_SEMAPHORE = 0x39,
|
||||
IT_MPEG_INDEX = 0x3A,
|
||||
IT_WAIT_REG_MEM = 0x3C,
|
||||
IT_MEM_WRITE = 0x3D,
|
||||
IT_INDIRECT_BUFFER = 0x32,
|
||||
IT_CP_INTERRUPT = 0x40,
|
||||
IT_SURFACE_SYNC = 0x43,
|
||||
IT_ME_INITIALIZE = 0x44,
|
||||
IT_COND_WRITE = 0x45,
|
||||
IT_EVENT_WRITE = 0x46,
|
||||
IT_EVENT_WRITE_EOP = 0x47,
|
||||
IT_ONE_REG_WRITE = 0x57,
|
||||
IT_SET_CONFIG_REG = 0x68,
|
||||
IT_SET_CONTEXT_REG = 0x69,
|
||||
IT_SET_ALU_CONST = 0x6A,
|
||||
IT_SET_BOOL_CONST = 0x6B,
|
||||
IT_SET_LOOP_CONST = 0x6C,
|
||||
IT_SET_RESOURCE = 0x6D,
|
||||
IT_SET_SAMPLER = 0x6E,
|
||||
IT_SET_CTL_CONST = 0x6F,
|
||||
IT_SURFACE_BASE_UPDATE = 0x73,
|
||||
} ;
|
||||
|
||||
/* IT_WAIT_REG_MEM operation encoding */
|
||||
|
||||
#define IT_WAIT_ALWAYS (0 << 0)
|
||||
#define IT_WAIT_LT (1 << 0)
|
||||
#define IT_WAIT_LE (2 << 0)
|
||||
#define IT_WAIT_EQ (3 << 0)
|
||||
#define IT_WAIT_NE (4 << 0)
|
||||
#define IT_WAIT_GE (5 << 0)
|
||||
#define IT_WAIT_GT (6 << 0)
|
||||
#define IT_WAIT_REG (0 << 4)
|
||||
#define IT_WAIT_MEM (1 << 4)
|
||||
|
||||
#define IT_WAIT_ADDR(x) ((x) >> 2)
|
||||
|
||||
/* IT_INDEX_TYPE */
|
||||
#define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2)
|
||||
|
||||
#endif
|
||||
3087
src/r600_reg_auto_r6xx.h
Normal file
3087
src/r600_reg_auto_r6xx.h
Normal file
File diff suppressed because it is too large
Load diff
503
src/r600_reg_r6xx.h
Normal file
503
src/r600_reg_r6xx.h
Normal file
|
|
@ -0,0 +1,503 @@
|
|||
/*
|
||||
* RadeonHD R6xx, R7xx Register documentation
|
||||
*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2009 Matthias Hopf
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _R600_REG_R6xx_H_
|
||||
#define _R600_REG_R6xx_H_
|
||||
|
||||
/*
|
||||
* Registers for R6xx chips that are not documented yet
|
||||
*/
|
||||
|
||||
enum {
|
||||
|
||||
MM_INDEX = 0x0000,
|
||||
MM_DATA = 0x0004,
|
||||
|
||||
SRBM_STATUS = 0x0e50,
|
||||
RLC_RQ_PENDING_bit = 1 << 3,
|
||||
RCU_RQ_PENDING_bit = 1 << 4,
|
||||
GRBM_RQ_PENDING_bit = 1 << 5,
|
||||
HI_RQ_PENDING_bit = 1 << 6,
|
||||
IO_EXTERN_SIGNAL_bit = 1 << 7,
|
||||
VMC_BUSY_bit = 1 << 8,
|
||||
MCB_BUSY_bit = 1 << 9,
|
||||
MCDZ_BUSY_bit = 1 << 10,
|
||||
MCDY_BUSY_bit = 1 << 11,
|
||||
MCDX_BUSY_bit = 1 << 12,
|
||||
MCDW_BUSY_bit = 1 << 13,
|
||||
SEM_BUSY_bit = 1 << 14,
|
||||
SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
|
||||
PDMA_BUSY_bit = 1 << 16,
|
||||
IH_BUSY_bit = 1 << 17,
|
||||
CSC_BUSY_bit = 1 << 20,
|
||||
CMC7_BUSY_bit = 1 << 21,
|
||||
CMC6_BUSY_bit = 1 << 22,
|
||||
CMC5_BUSY_bit = 1 << 23,
|
||||
CMC4_BUSY_bit = 1 << 24,
|
||||
CMC3_BUSY_bit = 1 << 25,
|
||||
CMC2_BUSY_bit = 1 << 26,
|
||||
CMC1_BUSY_bit = 1 << 27,
|
||||
CMC0_BUSY_bit = 1 << 28,
|
||||
BIF_BUSY_bit = 1 << 29,
|
||||
IDCT_BUSY_bit = 1 << 30,
|
||||
|
||||
SRBM_READ_ERROR = 0x0e98,
|
||||
READ_ADDRESS_mask = 0xffff << 2,
|
||||
READ_ADDRESS_shift = 2,
|
||||
READ_REQUESTER_HI_bit = 1 << 24,
|
||||
READ_REQUESTER_GRBM_bit = 1 << 25,
|
||||
READ_REQUESTER_RCU_bit = 1 << 26,
|
||||
READ_REQUESTER_RLC_bit = 1 << 27,
|
||||
READ_ERROR_bit = 1 << 31,
|
||||
|
||||
SRBM_INT_STATUS = 0x0ea4,
|
||||
RDERR_INT_STAT_bit = 1 << 0,
|
||||
GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
|
||||
SRBM_INT_ACK = 0x0ea8,
|
||||
RDERR_INT_ACK_bit = 1 << 0,
|
||||
GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
|
||||
|
||||
R6XX_MC_VM_FB_LOCATION = 0x2180,
|
||||
|
||||
VENDOR_DEVICE_ID = 0x4000,
|
||||
|
||||
HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480,
|
||||
|
||||
D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
|
||||
D1GRPH_PITCH = 0x6120,
|
||||
D1GRPH_Y_END = 0x6138,
|
||||
|
||||
GRBM_STATUS = 0x8010,
|
||||
CMDFIFO_AVAIL_mask = 0x1f << 0,
|
||||
CMDFIFO_AVAIL_shift = 0,
|
||||
SRBM_RQ_PENDING_bit = 1 << 5,
|
||||
CP_RQ_PENDING_bit = 1 << 6,
|
||||
CF_RQ_PENDING_bit = 1 << 7,
|
||||
PF_RQ_PENDING_bit = 1 << 8,
|
||||
GRBM_EE_BUSY_bit = 1 << 10,
|
||||
GRBM_STATUS__VC_BUSY_bit = 1 << 11,
|
||||
DB03_CLEAN_bit = 1 << 12,
|
||||
CB03_CLEAN_bit = 1 << 13,
|
||||
VGT_BUSY_NO_DMA_bit = 1 << 16,
|
||||
GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
|
||||
TA03_BUSY_bit = 1 << 18,
|
||||
GRBM_STATUS__TC_BUSY_bit = 1 << 19,
|
||||
SX_BUSY_bit = 1 << 20,
|
||||
SH_BUSY_bit = 1 << 21,
|
||||
SPI03_BUSY_bit = 1 << 22,
|
||||
SMX_BUSY_bit = 1 << 23,
|
||||
SC_BUSY_bit = 1 << 24,
|
||||
PA_BUSY_bit = 1 << 25,
|
||||
DB03_BUSY_bit = 1 << 26,
|
||||
CR_BUSY_bit = 1 << 27,
|
||||
CP_COHERENCY_BUSY_bit = 1 << 28,
|
||||
GRBM_STATUS__CP_BUSY_bit = 1 << 29,
|
||||
CB03_BUSY_bit = 1 << 30,
|
||||
GUI_ACTIVE_bit = 1 << 31,
|
||||
GRBM_STATUS2 = 0x8014,
|
||||
CR_CLEAN_bit = 1 << 0,
|
||||
SMX_CLEAN_bit = 1 << 1,
|
||||
SPI0_BUSY_bit = 1 << 8,
|
||||
SPI1_BUSY_bit = 1 << 9,
|
||||
SPI2_BUSY_bit = 1 << 10,
|
||||
SPI3_BUSY_bit = 1 << 11,
|
||||
TA0_BUSY_bit = 1 << 12,
|
||||
TA1_BUSY_bit = 1 << 13,
|
||||
TA2_BUSY_bit = 1 << 14,
|
||||
TA3_BUSY_bit = 1 << 15,
|
||||
DB0_BUSY_bit = 1 << 16,
|
||||
DB1_BUSY_bit = 1 << 17,
|
||||
DB2_BUSY_bit = 1 << 18,
|
||||
DB3_BUSY_bit = 1 << 19,
|
||||
CB0_BUSY_bit = 1 << 20,
|
||||
CB1_BUSY_bit = 1 << 21,
|
||||
CB2_BUSY_bit = 1 << 22,
|
||||
CB3_BUSY_bit = 1 << 23,
|
||||
GRBM_SOFT_RESET = 0x8020,
|
||||
SOFT_RESET_CP_bit = 1 << 0,
|
||||
SOFT_RESET_CB_bit = 1 << 1,
|
||||
SOFT_RESET_CR_bit = 1 << 2,
|
||||
SOFT_RESET_DB_bit = 1 << 3,
|
||||
SOFT_RESET_PA_bit = 1 << 5,
|
||||
SOFT_RESET_SC_bit = 1 << 6,
|
||||
SOFT_RESET_SMX_bit = 1 << 7,
|
||||
SOFT_RESET_SPI_bit = 1 << 8,
|
||||
SOFT_RESET_SH_bit = 1 << 9,
|
||||
SOFT_RESET_SX_bit = 1 << 10,
|
||||
SOFT_RESET_TC_bit = 1 << 11,
|
||||
SOFT_RESET_TA_bit = 1 << 12,
|
||||
SOFT_RESET_VC_bit = 1 << 13,
|
||||
SOFT_RESET_VGT_bit = 1 << 14,
|
||||
SOFT_RESET_GRBM_GCA_bit = 1 << 15,
|
||||
|
||||
WAIT_UNTIL = 0x8040,
|
||||
WAIT_CP_DMA_IDLE_bit = 1 << 8,
|
||||
WAIT_CMDFIFO_bit = 1 << 10,
|
||||
WAIT_2D_IDLE_bit = 1 << 14,
|
||||
WAIT_3D_IDLE_bit = 1 << 15,
|
||||
WAIT_2D_IDLECLEAN_bit = 1 << 16,
|
||||
WAIT_3D_IDLECLEAN_bit = 1 << 17,
|
||||
WAIT_EXTERN_SIG_bit = 1 << 19,
|
||||
CMDFIFO_ENTRIES_mask = 0x1f << 20,
|
||||
CMDFIFO_ENTRIES_shift = 20,
|
||||
|
||||
GRBM_READ_ERROR = 0x8058,
|
||||
/* READ_ADDRESS_mask = 0xffff << 2, */
|
||||
/* READ_ADDRESS_shift = 2, */
|
||||
READ_REQUESTER_SRBM_bit = 1 << 28,
|
||||
READ_REQUESTER_CP_bit = 1 << 29,
|
||||
READ_REQUESTER_WU_POLL_bit = 1 << 30,
|
||||
/* READ_ERROR_bit = 1 << 31, */
|
||||
|
||||
SCRATCH_REG0 = 0x8500,
|
||||
SCRATCH_REG1 = 0x8504,
|
||||
SCRATCH_REG2 = 0x8508,
|
||||
SCRATCH_REG3 = 0x850c,
|
||||
SCRATCH_REG4 = 0x8510,
|
||||
SCRATCH_REG5 = 0x8514,
|
||||
SCRATCH_REG6 = 0x8518,
|
||||
SCRATCH_REG7 = 0x851c,
|
||||
SCRATCH_UMSK = 0x8540,
|
||||
SCRATCH_ADDR = 0x8544,
|
||||
|
||||
CP_COHER_CNTL = 0x85f0,
|
||||
DEST_BASE_0_ENA_bit = 1 << 0,
|
||||
DEST_BASE_1_ENA_bit = 1 << 1,
|
||||
SO0_DEST_BASE_ENA_bit = 1 << 2,
|
||||
SO1_DEST_BASE_ENA_bit = 1 << 3,
|
||||
SO2_DEST_BASE_ENA_bit = 1 << 4,
|
||||
SO3_DEST_BASE_ENA_bit = 1 << 5,
|
||||
CB0_DEST_BASE_ENA_bit = 1 << 6,
|
||||
CB1_DEST_BASE_ENA_bit = 1 << 7,
|
||||
CB2_DEST_BASE_ENA_bit = 1 << 8,
|
||||
CB3_DEST_BASE_ENA_bit = 1 << 9,
|
||||
CB4_DEST_BASE_ENA_bit = 1 << 10,
|
||||
CB5_DEST_BASE_ENA_bit = 1 << 11,
|
||||
CB6_DEST_BASE_ENA_bit = 1 << 12,
|
||||
CB7_DEST_BASE_ENA_bit = 1 << 13,
|
||||
DB_DEST_BASE_ENA_bit = 1 << 14,
|
||||
CR_DEST_BASE_ENA_bit = 1 << 15,
|
||||
TC_ACTION_ENA_bit = 1 << 23,
|
||||
VC_ACTION_ENA_bit = 1 << 24,
|
||||
CB_ACTION_ENA_bit = 1 << 25,
|
||||
DB_ACTION_ENA_bit = 1 << 26,
|
||||
SH_ACTION_ENA_bit = 1 << 27,
|
||||
SMX_ACTION_ENA_bit = 1 << 28,
|
||||
CR0_ACTION_ENA_bit = 1 << 29,
|
||||
CR1_ACTION_ENA_bit = 1 << 30,
|
||||
CR2_ACTION_ENA_bit = 1 << 31,
|
||||
CP_COHER_SIZE = 0x85f4,
|
||||
CP_COHER_BASE = 0x85f8,
|
||||
CP_COHER_STATUS = 0x85fc,
|
||||
MATCHING_GFX_CNTX_mask = 0xff << 0,
|
||||
MATCHING_GFX_CNTX_shift = 0,
|
||||
MATCHING_CR_CNTX_mask = 0xffff << 8,
|
||||
MATCHING_CR_CNTX_shift = 8,
|
||||
STATUS_bit = 1 << 31,
|
||||
|
||||
CP_STALLED_STAT1 = 0x8674,
|
||||
RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
|
||||
RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
|
||||
RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
|
||||
RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
|
||||
RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
|
||||
RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
|
||||
RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
|
||||
RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
|
||||
RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
|
||||
RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
|
||||
MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
|
||||
MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
|
||||
MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
|
||||
RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
|
||||
RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
|
||||
RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
|
||||
RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
|
||||
RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
|
||||
CP_STALLED_STAT2 = 0x8678,
|
||||
PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
|
||||
PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
|
||||
PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
|
||||
PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
|
||||
MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
|
||||
ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
|
||||
ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
|
||||
CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
|
||||
GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
|
||||
ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
|
||||
ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
|
||||
ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
|
||||
ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
|
||||
RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
|
||||
RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
|
||||
EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
|
||||
EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
|
||||
EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
|
||||
EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
|
||||
SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
|
||||
SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
|
||||
PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
|
||||
SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
|
||||
SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
|
||||
CP_BUSY_STAT = 0x867c,
|
||||
REG_BUS_FIFO_BUSY_bit = 1 << 0,
|
||||
RING_FETCHING_DATA_bit = 1 << 1,
|
||||
INDR1_FETCHING_DATA_bit = 1 << 2,
|
||||
INDR2_FETCHING_DATA_bit = 1 << 3,
|
||||
STATE_FETCHING_DATA_bit = 1 << 4,
|
||||
PRED_FETCHING_DATA_bit = 1 << 5,
|
||||
COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
|
||||
PFP_PARSING_PACKETS_bit = 1 << 7,
|
||||
ME_PARSING_PACKETS_bit = 1 << 8,
|
||||
RCIU_PFP_BUSY_bit = 1 << 9,
|
||||
RCIU_ME_BUSY_bit = 1 << 10,
|
||||
OUTSTANDING_READ_TAGS_bit = 1 << 11,
|
||||
SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
|
||||
SEM_FAILED_AND_HOLDING_bit = 1 << 13,
|
||||
SEM_POLLING_FOR_PASS_bit = 1 << 14,
|
||||
_3D_BUSY_bit = 1 << 15,
|
||||
_2D_BUSY_bit = 1 << 16,
|
||||
CP_STAT = 0x8680,
|
||||
CSF_RING_BUSY_bit = 1 << 0,
|
||||
CSF_WPTR_POLL_BUSY_bit = 1 << 1,
|
||||
CSF_INDIRECT1_BUSY_bit = 1 << 2,
|
||||
CSF_INDIRECT2_BUSY_bit = 1 << 3,
|
||||
CSF_STATE_BUSY_bit = 1 << 4,
|
||||
CSF_PREDICATE_BUSY_bit = 1 << 5,
|
||||
CSF_BUSY_bit = 1 << 6,
|
||||
MIU_RDREQ_BUSY_bit = 1 << 7,
|
||||
MIU_WRREQ_BUSY_bit = 1 << 8,
|
||||
ROQ_RING_BUSY_bit = 1 << 9,
|
||||
ROQ_INDIRECT1_BUSY_bit = 1 << 10,
|
||||
ROQ_INDIRECT2_BUSY_bit = 1 << 11,
|
||||
ROQ_STATE_BUSY_bit = 1 << 12,
|
||||
ROQ_PREDICATE_BUSY_bit = 1 << 13,
|
||||
ROQ_ALIGN_BUSY_bit = 1 << 14,
|
||||
PFP_BUSY_bit = 1 << 15,
|
||||
MEQ_BUSY_bit = 1 << 16,
|
||||
ME_BUSY_bit = 1 << 17,
|
||||
QUERY_BUSY_bit = 1 << 18,
|
||||
SEMAPHORE_BUSY_bit = 1 << 19,
|
||||
INTERRUPT_BUSY_bit = 1 << 20,
|
||||
SURFACE_SYNC_BUSY_bit = 1 << 21,
|
||||
DMA_BUSY_bit = 1 << 22,
|
||||
RCIU_BUSY_bit = 1 << 23,
|
||||
CP_STAT__CP_BUSY_bit = 1 << 31,
|
||||
|
||||
CP_ME_CNTL = 0x86d8,
|
||||
ME_STATMUX_mask = 0xff << 0,
|
||||
ME_STATMUX_shift = 0,
|
||||
ME_HALT_bit = 1 << 28,
|
||||
CP_ME_STATUS = 0x86dc,
|
||||
|
||||
CP_RB_RPTR = 0x8700,
|
||||
RB_RPTR_mask = 0xfffff << 0,
|
||||
RB_RPTR_shift = 0,
|
||||
CP_RB_WPTR_DELAY = 0x8704,
|
||||
PRE_WRITE_TIMER_mask = 0xfffffff << 0,
|
||||
PRE_WRITE_TIMER_shift = 0,
|
||||
PRE_WRITE_LIMIT_mask = 0x0f << 28,
|
||||
PRE_WRITE_LIMIT_shift = 28,
|
||||
|
||||
CP_ROQ_RB_STAT = 0x8780,
|
||||
ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
|
||||
ROQ_RPTR_PRIMARY_shift = 0,
|
||||
ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
|
||||
ROQ_WPTR_PRIMARY_shift = 16,
|
||||
CP_ROQ_IB1_STAT = 0x8784,
|
||||
ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
|
||||
ROQ_RPTR_INDIRECT1_shift = 0,
|
||||
ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
|
||||
ROQ_WPTR_INDIRECT1_shift = 16,
|
||||
CP_ROQ_IB2_STAT = 0x8788,
|
||||
ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
|
||||
ROQ_RPTR_INDIRECT2_shift = 0,
|
||||
ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
|
||||
ROQ_WPTR_INDIRECT2_shift = 16,
|
||||
|
||||
CP_MEQ_STAT = 0x8794,
|
||||
MEQ_RPTR_mask = 0x3ff << 0,
|
||||
MEQ_RPTR_shift = 0,
|
||||
MEQ_WPTR_mask = 0x3ff << 16,
|
||||
MEQ_WPTR_shift = 16,
|
||||
|
||||
CC_GC_SHADER_PIPE_CONFIG = 0x8950,
|
||||
INACTIVE_QD_PIPES_mask = 0xff << 8,
|
||||
INACTIVE_QD_PIPES_shift = 8,
|
||||
R6XX_MAX_QD_PIPES = 8,
|
||||
INACTIVE_SIMDS_mask = 0xff << 16,
|
||||
INACTIVE_SIMDS_shift = 16,
|
||||
R6XX_MAX_SIMDS = 8,
|
||||
GC_USER_SHADER_PIPE_CONFIG = 0x8954,
|
||||
|
||||
VC_ENHANCE = 0x9714,
|
||||
DB_DEBUG = 0x9830,
|
||||
PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
|
||||
|
||||
DB_WATERMARKS = 0x00009838,
|
||||
DEPTH_FREE_mask = 0x1f << 0,
|
||||
DEPTH_FREE_shift = 0,
|
||||
DEPTH_FLUSH_mask = 0x3f << 5,
|
||||
DEPTH_FLUSH_shift = 5,
|
||||
FORCE_SUMMARIZE_mask = 0x0f << 11,
|
||||
FORCE_SUMMARIZE_shift = 11,
|
||||
DEPTH_PENDING_FREE_mask = 0x1f << 15,
|
||||
DEPTH_PENDING_FREE_shift = 15,
|
||||
DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
|
||||
DEPTH_CACHELINE_FREE_shift = 20,
|
||||
EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
|
||||
LATE_Z_PANIC_DISABLE_bit = 1 << 26,
|
||||
RE_Z_PANIC_DISABLE_bit = 1 << 27,
|
||||
DB_EXTRA_DEBUG_mask = 0x0f << 28,
|
||||
DB_EXTRA_DEBUG_shift = 28,
|
||||
|
||||
CP_RB_BASE = 0xc100,
|
||||
CP_RB_CNTL = 0xc104,
|
||||
RB_BUFSZ_mask = 0x3f << 0,
|
||||
CP_RB_WPTR = 0xc114,
|
||||
RB_WPTR_mask = 0xfffff << 0,
|
||||
RB_WPTR_shift = 0,
|
||||
CP_RB_RPTR_WR = 0xc108,
|
||||
RB_RPTR_WR_mask = 0xfffff << 0,
|
||||
RB_RPTR_WR_shift = 0,
|
||||
|
||||
CP_INT_STATUS = 0xc128,
|
||||
DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
|
||||
ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
|
||||
SEM_SIGNAL_INT_STAT_bit = 1 << 18,
|
||||
CNTX_BUSY_INT_STAT_bit = 1 << 19,
|
||||
CNTX_EMPTY_INT_STAT_bit = 1 << 20,
|
||||
WAITMEM_SEM_INT_STAT_bit = 1 << 21,
|
||||
PRIV_INSTR_INT_STAT_bit = 1 << 22,
|
||||
PRIV_REG_INT_STAT_bit = 1 << 23,
|
||||
OPCODE_ERROR_INT_STAT_bit = 1 << 24,
|
||||
SCRATCH_INT_STAT_bit = 1 << 25,
|
||||
TIME_STAMP_INT_STAT_bit = 1 << 26,
|
||||
RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
|
||||
DMA_INT_STAT_bit = 1 << 28,
|
||||
IB2_INT_STAT_bit = 1 << 29,
|
||||
IB1_INT_STAT_bit = 1 << 30,
|
||||
RB_INT_STAT_bit = 1 << 31,
|
||||
|
||||
// SX_ALPHA_TEST_CONTROL = 0x00028410,
|
||||
ALPHA_FUNC__REF_NEVER = 0,
|
||||
ALPHA_FUNC__REF_ALWAYS = 7,
|
||||
// DB_SHADER_CONTROL = 0x0002880c,
|
||||
Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
|
||||
// PA_SU_SC_MODE_CNTL = 0x00028814,
|
||||
// POLY_MODE_mask = 0x03 << 3,
|
||||
POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
|
||||
// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5,
|
||||
POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
|
||||
PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
|
||||
DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
|
||||
// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c,
|
||||
DB_ALPHA_TO_MASK = 0x00028d44,
|
||||
ALPHA_TO_MASK_ENABLE = 1 << 0,
|
||||
ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
|
||||
ALPHA_TO_MASK_OFFSET0_shift = 8,
|
||||
ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10,
|
||||
ALPHA_TO_MASK_OFFSET1_shift = 10,
|
||||
ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12,
|
||||
ALPHA_TO_MASK_OFFSET2_shift = 12,
|
||||
ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14,
|
||||
ALPHA_TO_MASK_OFFSET3_shift = 14,
|
||||
|
||||
// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008,
|
||||
// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
|
||||
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
|
||||
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
|
||||
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
|
||||
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
|
||||
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
|
||||
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
|
||||
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
|
||||
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
|
||||
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
|
||||
FMT_1 = 37, FMT_GB_GR=39,
|
||||
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
|
||||
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
|
||||
FMT_32_32_32_FLOAT=48,
|
||||
|
||||
// High level register file lengths
|
||||
SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
|
||||
SQ_ALU_CONSTANT_ps_num = 256,
|
||||
SQ_ALU_CONSTANT_vs_num = 256,
|
||||
SQ_ALU_CONSTANT_all_num = 512,
|
||||
SQ_ALU_CONSTANT_offset = 16,
|
||||
SQ_ALU_CONSTANT_ps = 0,
|
||||
SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
|
||||
SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
|
||||
SQ_TEX_RESOURCE_ps_num = 160,
|
||||
SQ_TEX_RESOURCE_vs_num = 160,
|
||||
SQ_TEX_RESOURCE_fs_num = 16,
|
||||
SQ_TEX_RESOURCE_gs_num = 160,
|
||||
SQ_TEX_RESOURCE_all_num = 496,
|
||||
SQ_TEX_RESOURCE_offset = 28,
|
||||
SQ_TEX_RESOURCE_ps = 0,
|
||||
SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
|
||||
SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
|
||||
SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
|
||||
SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
|
||||
SQ_VTX_RESOURCE_ps_num = 160,
|
||||
SQ_VTX_RESOURCE_vs_num = 160,
|
||||
SQ_VTX_RESOURCE_fs_num = 16,
|
||||
SQ_VTX_RESOURCE_gs_num = 160,
|
||||
SQ_VTX_RESOURCE_all_num = 496,
|
||||
SQ_VTX_RESOURCE_offset = 28,
|
||||
SQ_VTX_RESOURCE_ps = 0,
|
||||
SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
|
||||
SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
|
||||
SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
|
||||
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
|
||||
SQ_TEX_SAMPLER_WORD_ps_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_vs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_gs_num = 18,
|
||||
SQ_TEX_SAMPLER_WORD_all_num = 54,
|
||||
SQ_TEX_SAMPLER_WORD_offset = 12,
|
||||
SQ_TEX_SAMPLER_WORD_ps = 0,
|
||||
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
|
||||
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
|
||||
SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
|
||||
SQ_LOOP_CONST_ps_num = 32,
|
||||
SQ_LOOP_CONST_vs_num = 32,
|
||||
SQ_LOOP_CONST_gs_num = 32,
|
||||
SQ_LOOP_CONST_all_num = 96,
|
||||
SQ_LOOP_CONST_offset = 4,
|
||||
SQ_LOOP_CONST_ps = 0,
|
||||
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
|
||||
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
|
||||
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */
|
||||
SQ_BOOL_CONST_ps_num = 1,
|
||||
SQ_BOOL_CONST_vs_num = 1,
|
||||
SQ_BOOL_CONST_gs_num = 1,
|
||||
SQ_BOOL_CONST_all_num = 3,
|
||||
SQ_BOOL_CONST_offset = 4,
|
||||
SQ_BOOL_CONST_ps = 0,
|
||||
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
|
||||
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num,
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
149
src/r600_reg_r7xx.h
Normal file
149
src/r600_reg_r7xx.h
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* RadeonHD R6xx, R7xx Register documentation
|
||||
*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008-2009 Matthias Hopf
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _R600_REG_R7xx_H_
|
||||
#define _R600_REG_R7xx_H_
|
||||
|
||||
/*
|
||||
* Register update for R7xx chips
|
||||
*/
|
||||
|
||||
enum {
|
||||
|
||||
R7XX_MC_VM_FB_LOCATION = 0x00002024,
|
||||
|
||||
// GRBM_STATUS = 0x00008010,
|
||||
R7XX_TA_BUSY_bit = 1 << 14,
|
||||
|
||||
R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
|
||||
RING0_OFFSET_mask = 0xff << 0,
|
||||
RING0_OFFSET_shift = 0,
|
||||
ISOLATE_ES_ENABLE_bit = 1 << 12,
|
||||
ISOLATE_GS_ENABLE_bit = 1 << 13,
|
||||
VS_PC_LIMIT_ENABLE_bit = 1 << 14,
|
||||
|
||||
// SQ_ALU_WORD0 = 0x00008dfc,
|
||||
// SRC0_SEL_mask = 0x1ff << 0,
|
||||
// SRC1_SEL_mask = 0x1ff << 13,
|
||||
R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
|
||||
R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
|
||||
R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
|
||||
R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
|
||||
// INDEX_MODE_mask = 0x07 << 26,
|
||||
R7xx_SQ_INDEX_GLOBAL = 0x05,
|
||||
R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
|
||||
R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
|
||||
R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
|
||||
R6xx_FOG_MERGE_bit = 1 << 5,
|
||||
R6xx_OMOD_mask = 0x03 << 6,
|
||||
R7xx_OMOD_mask = 0x03 << 5,
|
||||
R6xx_OMOD_shift = 6,
|
||||
R7xx_OMOD_shift = 5,
|
||||
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
|
||||
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
|
||||
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
|
||||
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
|
||||
R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
|
||||
R7xx_SQ_OP2_INST_ADD_64 = 0x17,
|
||||
R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
|
||||
R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
|
||||
R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
|
||||
R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
|
||||
R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
|
||||
R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
|
||||
R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
|
||||
R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
|
||||
// SQ_ALU_WORD1_OP3 = 0x00008dfc,
|
||||
// SRC2_SEL_mask = 0x1ff << 0,
|
||||
// R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
|
||||
// R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
|
||||
// R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
|
||||
// R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
|
||||
// SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
|
||||
R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
|
||||
R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
|
||||
R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
|
||||
R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
|
||||
// SQ_CF_ALU_WORD1 = 0x00008dfc,
|
||||
R6xx_USES_WATERFALL_bit = 1 << 25,
|
||||
R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
|
||||
// SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
|
||||
// ARRAY_BASE_mask = 0x1fff << 0,
|
||||
// TYPE_mask = 0x03 << 13,
|
||||
// SQ_EXPORT_PARAM = 0x02,
|
||||
// X_UNUSED_FOR_SX_EXPORTS = 0x03,
|
||||
// ELEM_SIZE_mask = 0x03 << 30,
|
||||
// SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
|
||||
// SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
|
||||
R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
|
||||
// SQ_CF_WORD1 = 0x00008dfc,
|
||||
// SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
|
||||
R7xx_COUNT_3_bit = 1 << 19,
|
||||
// SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
|
||||
R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
|
||||
R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
|
||||
R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
|
||||
R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
|
||||
R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
|
||||
// SQ_VTX_WORD0 = 0x00008dfc,
|
||||
// VTX_INST_mask = 0x1f << 0,
|
||||
R7xx_SQ_VTX_INST_MEM = 0x02,
|
||||
// SQ_VTX_WORD2 = 0x00008dfc,
|
||||
R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
|
||||
|
||||
// SQ_TEX_WORD0 = 0x00008dfc,
|
||||
// TEX_INST_mask = 0x1f << 0,
|
||||
R7xx_X_MEMORY_READ = 0x02,
|
||||
R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
|
||||
R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
|
||||
R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
|
||||
|
||||
R7xx_PA_SC_EDGERULE = 0x00028230,
|
||||
R7xx_SPI_THREAD_GROUPING = 0x000286c8,
|
||||
PS_GROUPING_mask = 0x1f << 0,
|
||||
PS_GROUPING_shift = 0,
|
||||
VS_GROUPING_mask = 0x1f << 8,
|
||||
VS_GROUPING_shift = 8,
|
||||
GS_GROUPING_mask = 0x1f << 16,
|
||||
GS_GROUPING_shift = 16,
|
||||
ES_GROUPING_mask = 0x1f << 24,
|
||||
ES_GROUPING_shift = 24,
|
||||
R7xx_CB_SHADER_CONTROL = 0x000287a0,
|
||||
RT0_ENABLE_bit = 1 << 0,
|
||||
RT1_ENABLE_bit = 1 << 1,
|
||||
RT2_ENABLE_bit = 1 << 2,
|
||||
RT3_ENABLE_bit = 1 << 3,
|
||||
RT4_ENABLE_bit = 1 << 4,
|
||||
RT5_ENABLE_bit = 1 << 5,
|
||||
RT6_ENABLE_bit = 1 << 6,
|
||||
RT7_ENABLE_bit = 1 << 7,
|
||||
// DB_ALPHA_TO_MASK = 0x00028d44,
|
||||
R7xx_OFFSET_ROUND_bit = 1 << 16,
|
||||
// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
|
||||
R7xx_TRUNCATE_COORD_bit = 1 << 9,
|
||||
R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
|
||||
|
||||
} ;
|
||||
|
||||
#endif /* _R600_REG_R7xx_H_ */
|
||||
2899
src/r600_shader.c
Normal file
2899
src/r600_shader.c
Normal file
File diff suppressed because it is too large
Load diff
362
src/r600_shader.h
Normal file
362
src/r600_shader.h
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/*
|
||||
* RadeonHD R6xx, R7xx DRI driver
|
||||
*
|
||||
* Copyright (C) 2008-2009 Alexander Deucher
|
||||
* Copyright (C) 2008-2009 Matthias Hopf
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Shader macros
|
||||
*/
|
||||
|
||||
#ifndef __SHADER_H__
|
||||
#define __SHADER_H__
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
/* Restrictions of ALU instructions
|
||||
* order of scalar ops is always x,y,z,w,t(rans), last to be indicated by last==1.
|
||||
* max of 3 different src GPRs per instr.
|
||||
* max of 4 different cfile constant components per instr.
|
||||
* max of 2 (different) constants (any type) for t.
|
||||
* bank swizzle (see below).
|
||||
* GPR write stalls read of same register. Auto-replaced by PV/PS, NOP needed if registers are relative to
|
||||
* different indices (gpr,loop,nothing).
|
||||
* may use constant registers or constant cache, but not both.
|
||||
*/
|
||||
|
||||
/* Bank_swizzle: (pp. 297ff)
|
||||
* Only one of each x,y,z,w GPR component can be loaded per cycle (3 cycles per instr, called 0-2).
|
||||
* per scalar instruction bank_swizzle can select which cycle each operand comes from. e.g.:
|
||||
* SRC0 SRC1 SRC2 SWIZZLE cycle0 cycle1 cycle2
|
||||
* 1.x 2.x 012 1.x 2.x -
|
||||
* 3.x 1.y 201 1.y - 3.x
|
||||
* 2.x 1.y 102 (1.y) (2.x) -
|
||||
* If data is read in a cycle, multiple scalar instructions can reference it.
|
||||
* Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1.
|
||||
* No restrictions for constants or PV/PS.
|
||||
* t can load multiple components in a single cycle slot, but has to share cycles with xyzw.
|
||||
* t with single constant may not load GPRs or PV/PS in cycle 0 (careful with ALU_TRANS_210).
|
||||
* t with two constants may only load GPRs or PV/PS in cycle 2.
|
||||
*/
|
||||
|
||||
|
||||
/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
|
||||
|
||||
|
||||
// CF insts
|
||||
// addr
|
||||
#define ADDR(x) (x)
|
||||
// pc
|
||||
#define POP_COUNT(x) (x)
|
||||
// const
|
||||
#define CF_CONST(x) (x)
|
||||
// cond
|
||||
#define COND(x) (x) // SQ_COND_*
|
||||
// count
|
||||
#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
|
||||
//r7xx
|
||||
#define COUNT_3(x) (x)
|
||||
// call count
|
||||
#define CALL_COUNT(x) (x)
|
||||
// eop
|
||||
#define END_OF_PROGRAM(x) (x)
|
||||
// vpm
|
||||
#define VALID_PIXEL_MODE(x) (x)
|
||||
// cf inst
|
||||
#define CF_INST(x) (x) // SQ_CF_INST_*
|
||||
|
||||
// wqm
|
||||
#define WHOLE_QUAD_MODE(x) (x)
|
||||
// barrier
|
||||
#define BARRIER(x) (x)
|
||||
//kb0
|
||||
#define KCACHE_BANK0(x) (x)
|
||||
//kb1
|
||||
#define KCACHE_BANK1(x) (x)
|
||||
// km0/1
|
||||
#define KCACHE_MODE0(x) (x)
|
||||
#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_*
|
||||
//
|
||||
#define KCACHE_ADDR0(x) (x)
|
||||
#define KCACHE_ADDR1(x) (x)
|
||||
// uw
|
||||
#define USES_WATERFALL(x) (x)
|
||||
|
||||
#define ARRAY_BASE(x) (x)
|
||||
// export pixel
|
||||
#define CF_PIXEL_MRT0 0
|
||||
#define CF_PIXEL_MRT1 1
|
||||
#define CF_PIXEL_MRT2 2
|
||||
#define CF_PIXEL_MRT3 3
|
||||
#define CF_PIXEL_MRT4 4
|
||||
#define CF_PIXEL_MRT5 5
|
||||
#define CF_PIXEL_MRT6 6
|
||||
#define CF_PIXEL_MRT7 7
|
||||
// *_FOG: r6xx only
|
||||
#define CF_PIXEL_MRT0_FOG 16
|
||||
#define CF_PIXEL_MRT1_FOG 17
|
||||
#define CF_PIXEL_MRT2_FOG 18
|
||||
#define CF_PIXEL_MRT3_FOG 19
|
||||
#define CF_PIXEL_MRT4_FOG 20
|
||||
#define CF_PIXEL_MRT5_FOG 21
|
||||
#define CF_PIXEL_MRT6_FOG 22
|
||||
#define CF_PIXEL_MRT7_FOG 23
|
||||
#define CF_PIXEL_Z 61
|
||||
// export pos
|
||||
#define CF_POS0 60
|
||||
#define CF_POS1 61
|
||||
#define CF_POS2 62
|
||||
#define CF_POS3 63
|
||||
// export param
|
||||
// 0...31
|
||||
#define TYPE(x) (x) // SQ_EXPORT_*
|
||||
#if 0
|
||||
// type export
|
||||
#define SQ_EXPORT_PIXEL 0
|
||||
#define SQ_EXPORT_POS 1
|
||||
#define SQ_EXPORT_PARAM 2
|
||||
// reserved 3
|
||||
// type mem
|
||||
#define SQ_EXPORT_WRITE 0
|
||||
#define SQ_EXPORT_WRITE_IND 1
|
||||
#define SQ_EXPORT_WRITE_ACK 2
|
||||
#define SQ_EXPORT_WRITE_IND_ACK 3
|
||||
#endif
|
||||
|
||||
#define RW_GPR(x) (x)
|
||||
#define RW_REL(x) (x)
|
||||
#define ABSOLUTE 0
|
||||
#define RELATIVE 1
|
||||
#define INDEX_GPR(x) (x)
|
||||
#define ELEM_SIZE(x) (x ? (x - 1) : 0)
|
||||
#define COMP_MASK(x) (x)
|
||||
#define R6xx_ELEM_LOOP(x) (x)
|
||||
#define BURST_COUNT(x) (x ? (x - 1) : 0)
|
||||
|
||||
// swiz
|
||||
#define SRC_SEL_X(x) (x) // SQ_SEL_* each
|
||||
#define SRC_SEL_Y(x) (x)
|
||||
#define SRC_SEL_Z(x) (x)
|
||||
#define SRC_SEL_W(x) (x)
|
||||
|
||||
#define CF_DWORD0(addr) cpu_to_le32((addr))
|
||||
// R7xx has another entry (COUNT3), but that is only used for adding a bit to count.
|
||||
// We allow one more bit for count in the argument of the macro on R7xx instead.
|
||||
// R6xx: [0,7] R7xx: [1,16]
|
||||
#define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \
|
||||
((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
#define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)))
|
||||
#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
|
||||
((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
|
||||
cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \
|
||||
((es) << 30)))
|
||||
// R7xx apparently doesn't have the ELEM_LOOP entry any more
|
||||
// We still expose it, but ELEM_LOOP is explicitly R6xx now.
|
||||
// TODO: is this just forgotten in the docs, or really not available any more?
|
||||
#define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \
|
||||
((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)))
|
||||
#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \
|
||||
cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \
|
||||
((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \
|
||||
((wqm) << 30) | ((b) << 31)))
|
||||
|
||||
// ALU clause insts
|
||||
#define SRC0_SEL(x) (x)
|
||||
#define SRC1_SEL(x) (x)
|
||||
#define SRC2_SEL(x) (x)
|
||||
// src[0-2]_sel
|
||||
// 0-127 GPR
|
||||
// 128-159 kcache constants bank 0
|
||||
// 160-191 kcache constants bank 1
|
||||
// 248-255 special SQ_ALU_SRC_* (0, 1, etc.)
|
||||
#define ALU_SRC_GPR_BASE 0
|
||||
#define ALU_SRC_KCACHE0_BASE 128
|
||||
#define ALU_SRC_KCACHE1_BASE 160
|
||||
#define ALU_SRC_CFILE_BASE 256
|
||||
|
||||
#define SRC0_REL(x) (x)
|
||||
#define SRC1_REL(x) (x)
|
||||
#define SRC2_REL(x) (x)
|
||||
// elem
|
||||
#define SRC0_ELEM(x) (x)
|
||||
#define SRC1_ELEM(x) (x)
|
||||
#define SRC2_ELEM(x) (x)
|
||||
#define ELEM_X 0
|
||||
#define ELEM_Y 1
|
||||
#define ELEM_Z 2
|
||||
#define ELEM_W 3
|
||||
// neg
|
||||
#define SRC0_NEG(x) (x)
|
||||
#define SRC1_NEG(x) (x)
|
||||
#define SRC2_NEG(x) (x)
|
||||
// im
|
||||
#define INDEX_MODE(x) (x) // SQ_INDEX_*
|
||||
// ps
|
||||
#define PRED_SEL(x) (x) // SQ_PRED_SEL_*
|
||||
// last
|
||||
#define LAST(x) (x)
|
||||
// abs
|
||||
#define SRC0_ABS(x) (x)
|
||||
#define SRC1_ABS(x) (x)
|
||||
// uem
|
||||
#define UPDATE_EXECUTE_MASK(x) (x)
|
||||
// up
|
||||
#define UPDATE_PRED(x) (x)
|
||||
// wm
|
||||
#define WRITE_MASK(x) (x)
|
||||
// fm
|
||||
#define FOG_MERGE(x) (x)
|
||||
// omod
|
||||
#define OMOD(x) (x) // SQ_ALU_OMOD_*
|
||||
// alu inst
|
||||
#define ALU_INST(x) (x) // SQ_ALU_INST_*
|
||||
//bs
|
||||
#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_*
|
||||
#define DST_GPR(x) (x)
|
||||
#define DST_REL(x) (x)
|
||||
#define DST_ELEM(x) (x)
|
||||
#define CLAMP(x) (x)
|
||||
|
||||
#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
|
||||
cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
|
||||
((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
|
||||
((im) << 26) | ((ps) << 29) | ((last) << 31)))
|
||||
// R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more)
|
||||
#define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
|
||||
((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \
|
||||
((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
|
||||
#define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
|
||||
((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
|
||||
((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
|
||||
// This is a general chipset macro, but due to selection by chipid typically not usable in static arrays
|
||||
// Fog is NOT USED on R7xx, even if specified.
|
||||
#define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
((chipfamily) < CHIP_FAMILY_RV770 ? \
|
||||
R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
|
||||
R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))
|
||||
#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
|
||||
cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
|
||||
((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
|
||||
((de) << 29) | ((clamp) << 31)))
|
||||
|
||||
// VTX clause insts
|
||||
// vxt insts
|
||||
#define VTX_INST(x) (x) // SQ_VTX_INST_*
|
||||
|
||||
// fetch type
|
||||
#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_*
|
||||
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define BUFFER_ID(x) (x)
|
||||
#define SRC_GPR(x) (x)
|
||||
#define SRC_REL(x) (x)
|
||||
#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
|
||||
|
||||
#define SEMANTIC_ID(x) (x)
|
||||
#define DST_SEL_X(x) (x)
|
||||
#define DST_SEL_Y(x) (x)
|
||||
#define DST_SEL_Z(x) (x)
|
||||
#define DST_SEL_W(x) (x)
|
||||
#define USE_CONST_FIELDS(x) (x)
|
||||
#define DATA_FORMAT(x) (x)
|
||||
// num format
|
||||
#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_*
|
||||
// format comp
|
||||
#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_*
|
||||
// sma
|
||||
#define SRF_MODE_ALL(x) (x)
|
||||
#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
|
||||
#define SRF_MODE_NO_ZERO 1
|
||||
#define OFFSET(x) (x)
|
||||
// endian swap
|
||||
#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_*
|
||||
#define CONST_BUF_NO_STRIDE(x) (x)
|
||||
// mf
|
||||
#define MEGA_FETCH(x) (x)
|
||||
|
||||
#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
|
||||
cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)))
|
||||
#define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
|
||||
cpu_to_le32((((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
|
||||
#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
|
||||
#define VTX_DWORD2(offset, es, cbns, mf) \
|
||||
cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)))
|
||||
#define VTX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
// TEX clause insts
|
||||
// tex insts
|
||||
#define TEX_INST(x) (x) // SQ_TEX_INST_*
|
||||
|
||||
#define BC_FRAC_MODE(x) (x)
|
||||
#define FETCH_WHOLE_QUAD(x) (x)
|
||||
#define RESOURCE_ID(x) (x)
|
||||
#define R7xx_ALT_CONST(x) (x)
|
||||
|
||||
#define LOD_BIAS(x) (x)
|
||||
//ct
|
||||
#define COORD_TYPE_X(x) (x)
|
||||
#define COORD_TYPE_Y(x) (x)
|
||||
#define COORD_TYPE_Z(x) (x)
|
||||
#define COORD_TYPE_W(x) (x)
|
||||
#define TEX_UNNORMALIZED 0
|
||||
#define TEX_NORMALIZED 1
|
||||
#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
|
||||
#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
|
||||
#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
|
||||
#define SAMPLER_ID(x) (x)
|
||||
|
||||
// R7xx has an additional parameter ALT_CONST. We always expose it, but ALT_CONST is R7xx only
|
||||
#define TEX_DWORD0(tex_inst, bfm, fwq, resource_id, src_gpr, sr, ac) \
|
||||
cpu_to_le32((((tex_inst) << 0) | ((bfm) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
|
||||
((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24)))
|
||||
#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
|
||||
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||||
((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)))
|
||||
#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
|
||||
cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
|
||||
((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)))
|
||||
#define TEX_DWORD_PAD cpu_to_le32(0x00000000)
|
||||
|
||||
extern int R600_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
extern int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
extern int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader);
|
||||
extern int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader);
|
||||
|
||||
extern int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs);
|
||||
extern int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps);
|
||||
|
||||
#endif
|
||||
326
src/r600_state.h
Normal file
326
src/r600_state.h
Normal file
|
|
@ -0,0 +1,326 @@
|
|||
#ifndef __R600_STATE_H__
|
||||
#define __R600_STATE_H__
|
||||
|
||||
|
||||
#include "xf86drm.h"
|
||||
|
||||
typedef int bool_t;
|
||||
|
||||
#define CLEAR(x) memset (&x, 0, sizeof(x))
|
||||
|
||||
/* Sequencer / thread handling */
|
||||
typedef struct {
|
||||
int ps_prio;
|
||||
int vs_prio;
|
||||
int gs_prio;
|
||||
int es_prio;
|
||||
int num_ps_gprs;
|
||||
int num_vs_gprs;
|
||||
int num_gs_gprs;
|
||||
int num_es_gprs;
|
||||
int num_temp_gprs;
|
||||
int num_ps_threads;
|
||||
int num_vs_threads;
|
||||
int num_gs_threads;
|
||||
int num_es_threads;
|
||||
int num_ps_stack_entries;
|
||||
int num_vs_stack_entries;
|
||||
int num_gs_stack_entries;
|
||||
int num_es_stack_entries;
|
||||
} sq_config_t;
|
||||
|
||||
/* Color buffer / render target */
|
||||
typedef struct {
|
||||
int id;
|
||||
int w;
|
||||
int h;
|
||||
uint64_t base;
|
||||
int format;
|
||||
int endian;
|
||||
int array_mode; // tiling
|
||||
int number_type;
|
||||
int read_size;
|
||||
int comp_swap;
|
||||
int tile_mode;
|
||||
int blend_clamp;
|
||||
int clear_color;
|
||||
int blend_bypass;
|
||||
int blend_float32;
|
||||
int simple_float;
|
||||
int round_mode;
|
||||
int tile_compact;
|
||||
int source_format;
|
||||
/* 2D related CB state */
|
||||
uint32_t pmask;
|
||||
int rop;
|
||||
int blend_enable;
|
||||
uint32_t blendcntl;
|
||||
struct radeon_bo *bo;
|
||||
struct radeon_surface *surface;
|
||||
} cb_config_t;
|
||||
|
||||
/* Depth buffer */
|
||||
typedef struct {
|
||||
int w;
|
||||
int h;
|
||||
uint64_t base;
|
||||
int format;
|
||||
int read_size;
|
||||
int array_mode; // tiling
|
||||
int tile_surface_en;
|
||||
int tile_compact;
|
||||
int zrange_precision;
|
||||
struct radeon_bo *bo;
|
||||
} db_config_t;
|
||||
|
||||
/* Shader */
|
||||
typedef struct {
|
||||
uint64_t shader_addr;
|
||||
uint32_t shader_size;
|
||||
int num_gprs;
|
||||
int stack_size;
|
||||
int dx10_clamp;
|
||||
int prime_cache_pgm_en;
|
||||
int prime_cache_on_draw;
|
||||
int fetch_cache_lines;
|
||||
int prime_cache_en;
|
||||
int prime_cache_on_const;
|
||||
int clamp_consts;
|
||||
int export_mode;
|
||||
int uncached_first_inst;
|
||||
struct radeon_bo *bo;
|
||||
} shader_config_t;
|
||||
|
||||
/* Vertex buffer / vtx resource */
|
||||
typedef struct {
|
||||
int id;
|
||||
uint64_t vb_addr;
|
||||
uint32_t vtx_num_entries;
|
||||
uint32_t vtx_size_dw;
|
||||
int clamp_x;
|
||||
int format;
|
||||
int num_format_all;
|
||||
int format_comp_all;
|
||||
int srf_mode_all;
|
||||
int endian;
|
||||
int mem_req_size;
|
||||
struct radeon_bo *bo;
|
||||
} vtx_resource_t;
|
||||
|
||||
/* Texture resource */
|
||||
typedef struct {
|
||||
int id;
|
||||
int w;
|
||||
int h;
|
||||
int pitch;
|
||||
int depth;
|
||||
int dim;
|
||||
int tile_mode;
|
||||
int tile_type;
|
||||
int format;
|
||||
uint64_t base;
|
||||
uint64_t mip_base;
|
||||
uint32_t size;
|
||||
int format_comp_x;
|
||||
int format_comp_y;
|
||||
int format_comp_z;
|
||||
int format_comp_w;
|
||||
int num_format_all;
|
||||
int srf_mode_all;
|
||||
int force_degamma;
|
||||
int endian;
|
||||
int request_size;
|
||||
int dst_sel_x;
|
||||
int dst_sel_y;
|
||||
int dst_sel_z;
|
||||
int dst_sel_w;
|
||||
int base_level;
|
||||
int last_level;
|
||||
int base_array;
|
||||
int last_array;
|
||||
int mpeg_clamp;
|
||||
int perf_modulation;
|
||||
int interlaced;
|
||||
struct radeon_bo *bo;
|
||||
struct radeon_bo *mip_bo;
|
||||
struct radeon_surface *surface;
|
||||
} tex_resource_t;
|
||||
|
||||
/* Texture sampler */
|
||||
typedef struct {
|
||||
int id;
|
||||
/* Clamping */
|
||||
int clamp_x, clamp_y, clamp_z;
|
||||
int border_color;
|
||||
/* Filtering */
|
||||
int xy_mag_filter, xy_min_filter;
|
||||
int z_filter;
|
||||
int mip_filter;
|
||||
bool_t high_precision_filter; /* ? */
|
||||
int perf_mip; /* ? 0-7 */
|
||||
int perf_z; /* ? 3 */
|
||||
/* LoD selection */
|
||||
int min_lod, max_lod; /* 0-0x3ff */
|
||||
int lod_bias; /* 0-0xfff (signed?) */
|
||||
int lod_bias2; /* ? 0-0xfff (signed?) */
|
||||
bool_t lod_uses_minor_axis; /* ? */
|
||||
/* Other stuff */
|
||||
bool_t point_sampling_clamp; /* ? */
|
||||
bool_t tex_array_override; /* ? */
|
||||
bool_t mc_coord_truncate; /* ? */
|
||||
bool_t force_degamma; /* ? */
|
||||
bool_t fetch_4; /* ? */
|
||||
bool_t sample_is_pcf; /* ? */
|
||||
bool_t type; /* ? */
|
||||
int depth_compare; /* only depth textures? */
|
||||
int chroma_key;
|
||||
} tex_sampler_t;
|
||||
|
||||
/* Draw command */
|
||||
typedef struct {
|
||||
uint32_t prim_type;
|
||||
uint32_t vgt_draw_initiator;
|
||||
uint32_t index_type;
|
||||
uint32_t num_instances;
|
||||
uint32_t num_indices;
|
||||
} draw_config_t;
|
||||
|
||||
#define BEGIN_BATCH(n) \
|
||||
do { \
|
||||
radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define END_BATCH() \
|
||||
do { \
|
||||
radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define RELOC_BATCH(bo, rd, wd) \
|
||||
do { \
|
||||
int _ret; \
|
||||
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
|
||||
if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
|
||||
} while(0)
|
||||
#define E32(dword) \
|
||||
do { \
|
||||
radeon_cs_write_dword(info->cs, (dword)); \
|
||||
} while (0)
|
||||
|
||||
#define EFLOAT(val) \
|
||||
do { \
|
||||
union { float f; uint32_t d; } a; \
|
||||
a.f = (val); \
|
||||
E32(a.d); \
|
||||
} while (0)
|
||||
|
||||
#define PACK3(cmd, num) \
|
||||
do { \
|
||||
E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
|
||||
} while (0)
|
||||
|
||||
/* write num registers, start at reg */
|
||||
/* If register falls in a special area, special commands are issued */
|
||||
#define PACK0(reg, num) \
|
||||
do { \
|
||||
if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
|
||||
PACK3(IT_SET_CONFIG_REG, (num) + 1); \
|
||||
E32(((reg) - SET_CONFIG_REG_offset) >> 2); \
|
||||
} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
|
||||
PACK3(IT_SET_CONTEXT_REG, (num) + 1); \
|
||||
E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \
|
||||
} else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
|
||||
PACK3(IT_SET_ALU_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_ALU_CONST_offset) >> 2); \
|
||||
} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
|
||||
PACK3(IT_SET_RESOURCE, num + 1); \
|
||||
E32(((reg) - SET_RESOURCE_offset) >> 2); \
|
||||
} else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
|
||||
PACK3(IT_SET_SAMPLER, (num) + 1); \
|
||||
E32((reg - SET_SAMPLER_offset) >> 2); \
|
||||
} else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
|
||||
PACK3(IT_SET_CTL_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_CTL_CONST_offset) >> 2); \
|
||||
} else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
|
||||
PACK3(IT_SET_LOOP_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_LOOP_CONST_offset) >> 2); \
|
||||
} else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
|
||||
PACK3(IT_SET_BOOL_CONST, (num) + 1); \
|
||||
E32(((reg) - SET_BOOL_CONST_offset) >> 2); \
|
||||
} else { \
|
||||
E32(CP_PACKET0 ((reg), (num) - 1)); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* write a single register */
|
||||
#define EREG(reg, val) \
|
||||
do { \
|
||||
PACK0((reg), 1); \
|
||||
E32((val)); \
|
||||
} while (0)
|
||||
|
||||
void R600CPFlushIndirect(ScrnInfoPtr pScrn);
|
||||
void R600IBDiscard(ScrnInfoPtr pScrn);
|
||||
|
||||
void
|
||||
r600_wait_3d_idle_clean(ScrnInfoPtr pScrn);
|
||||
void
|
||||
r600_wait_3d_idle(ScrnInfoPtr pScrn);
|
||||
void
|
||||
r600_start_3d(ScrnInfoPtr pScrn);
|
||||
void
|
||||
r600_set_blend_color(ScrnInfoPtr pScrn, float *color);
|
||||
void
|
||||
r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
|
||||
void
|
||||
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
|
||||
void
|
||||
r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
|
||||
void
|
||||
r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
|
||||
void
|
||||
r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
|
||||
void
|
||||
r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
|
||||
void
|
||||
r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf);
|
||||
void
|
||||
r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
|
||||
void
|
||||
r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
|
||||
void
|
||||
r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s);
|
||||
void
|
||||
r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
|
||||
void
|
||||
r600_set_default_state(ScrnInfoPtr pScrn);
|
||||
void
|
||||
r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices);
|
||||
void
|
||||
r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
|
||||
|
||||
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
|
||||
|
||||
Bool
|
||||
R600SetAccelState(ScrnInfoPtr pScrn,
|
||||
struct r600_accel_object *src0,
|
||||
struct r600_accel_object *src1,
|
||||
struct r600_accel_object *dst,
|
||||
uint32_t vs_offset, uint32_t ps_offset,
|
||||
int rop, Pixel planemask);
|
||||
|
||||
extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
|
||||
extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
|
||||
extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
|
||||
int depth, int usage_hint, int bitsPerPixel,
|
||||
int *new_pitch);
|
||||
extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
|
||||
extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
|
||||
extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr secondary, void **handle_p);
|
||||
extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);
|
||||
#endif
|
||||
493
src/r600_textured_videofuncs.c
Normal file
493
src/r600_textured_videofuncs.c
Normal file
|
|
@ -0,0 +1,493 @@
|
|||
/*
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Author: Alex Deucher <alexander.deucher@amd.com>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
#include "exa.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "r600_shader.h"
|
||||
#include "r600_reg.h"
|
||||
#include "r600_state.h"
|
||||
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include <X11/extensions/Xv.h>
|
||||
#include "fourcc.h"
|
||||
|
||||
#include "damage.h"
|
||||
|
||||
#include "radeon_exa_shared.h"
|
||||
#include "radeon_vbo.h"
|
||||
|
||||
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
|
||||
note the difference to the parameters used in overlay are due
|
||||
to 10bit vs. float calcs */
|
||||
static REF_TRANSFORM trans[2] =
|
||||
{
|
||||
{1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */
|
||||
{1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */
|
||||
};
|
||||
|
||||
void
|
||||
R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
PixmapPtr pPixmap = pPriv->pPixmap;
|
||||
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
|
||||
int nBox = REGION_NUM_RECTS(&pPriv->clip);
|
||||
int dstxoff, dstyoff;
|
||||
struct r600_accel_object src_obj, dst_obj;
|
||||
cb_config_t cb_conf;
|
||||
tex_resource_t tex_res;
|
||||
tex_sampler_t tex_samp;
|
||||
shader_config_t vs_conf, ps_conf;
|
||||
/*
|
||||
* y' = y - .0625
|
||||
* u' = u - .5
|
||||
* v' = v - .5;
|
||||
*
|
||||
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
|
||||
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
|
||||
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
|
||||
*
|
||||
* DP3 might look like the straightforward solution
|
||||
* but we'd need to move the texture yuv values in
|
||||
* the same reg for this to work. Therefore use MADs.
|
||||
* Brightness just adds to the off constant.
|
||||
* Contrast is multiplication of luminance.
|
||||
* Saturation and hue change the u and v coeffs.
|
||||
* Default values (before adjustments - depend on colorspace):
|
||||
* yco = 1.1643
|
||||
* uco = 0, -0.39173, 2.017
|
||||
* vco = 1.5958, -0.8129, 0
|
||||
* off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r],
|
||||
* -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g],
|
||||
* -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b],
|
||||
*
|
||||
* temp = MAD(yco, yuv.yyyy, off)
|
||||
* temp = MAD(uco, yuv.uuuu, temp)
|
||||
* result = MAD(vco, yuv.vvvv, temp)
|
||||
*/
|
||||
/* TODO: calc consts in the shader */
|
||||
const float Loff = -0.0627;
|
||||
const float Coff = -0.502;
|
||||
float uvcosf, uvsinf;
|
||||
float yco;
|
||||
float uco[3], vco[3], off[3];
|
||||
float bright, cont, gamma;
|
||||
int ref = pPriv->transform_index;
|
||||
float ps_alu_consts[12];
|
||||
float vs_alu_consts[4];
|
||||
|
||||
cont = RTFContrast(pPriv->contrast);
|
||||
bright = RTFBrightness(pPriv->brightness);
|
||||
gamma = (float)pPriv->gamma / 1000.0;
|
||||
uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue));
|
||||
uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue));
|
||||
/* overlay video also does pre-gamma contrast/sat adjust, should we? */
|
||||
|
||||
yco = trans[ref].RefLuma * cont;
|
||||
uco[0] = -trans[ref].RefRCr * uvsinf;
|
||||
uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf;
|
||||
uco[2] = trans[ref].RefBCb * uvcosf;
|
||||
vco[0] = trans[ref].RefRCr * uvcosf;
|
||||
vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf;
|
||||
vco[2] = trans[ref].RefBCb * uvsinf;
|
||||
off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright;
|
||||
off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright;
|
||||
off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright;
|
||||
|
||||
// XXX
|
||||
gamma = 1.0;
|
||||
|
||||
/* setup the ps consts */
|
||||
ps_alu_consts[0] = off[0];
|
||||
ps_alu_consts[1] = off[1];
|
||||
ps_alu_consts[2] = off[2];
|
||||
ps_alu_consts[3] = yco;
|
||||
|
||||
ps_alu_consts[4] = uco[0];
|
||||
ps_alu_consts[5] = uco[1];
|
||||
ps_alu_consts[6] = uco[2];
|
||||
ps_alu_consts[7] = gamma;
|
||||
|
||||
ps_alu_consts[8] = vco[0];
|
||||
ps_alu_consts[9] = vco[1];
|
||||
ps_alu_consts[10] = vco[2];
|
||||
ps_alu_consts[11] = 0.0;
|
||||
|
||||
CLEAR (cb_conf);
|
||||
CLEAR (tex_res);
|
||||
CLEAR (tex_samp);
|
||||
CLEAR (vs_conf);
|
||||
CLEAR (ps_conf);
|
||||
|
||||
dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
|
||||
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
|
||||
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
|
||||
|
||||
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
|
||||
|
||||
src_obj.pitch = pPriv->src_pitch;
|
||||
src_obj.width = pPriv->w;
|
||||
src_obj.height = pPriv->h;
|
||||
src_obj.bpp = 16;
|
||||
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
|
||||
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
|
||||
src_obj.tiling_flags = 0;
|
||||
src_obj.surface = NULL;
|
||||
|
||||
dst_obj.width = pPixmap->drawable.width;
|
||||
dst_obj.height = pPixmap->drawable.height;
|
||||
dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
|
||||
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
|
||||
|
||||
if (!R600SetAccelState(pScrn,
|
||||
&src_obj,
|
||||
NULL,
|
||||
&dst_obj,
|
||||
accel_state->xv_vs_offset, accel_state->xv_ps_offset,
|
||||
3, 0xffffffff))
|
||||
return;
|
||||
|
||||
#ifdef COMPOSITE
|
||||
dstxoff = -pPixmap->screen_x + pPixmap->drawable.x;
|
||||
dstyoff = -pPixmap->screen_y + pPixmap->drawable.y;
|
||||
#else
|
||||
dstxoff = 0;
|
||||
dstyoff = 0;
|
||||
#endif
|
||||
|
||||
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
|
||||
radeon_cp_start(pScrn);
|
||||
|
||||
r600_set_default_state(pScrn);
|
||||
|
||||
r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
|
||||
|
||||
/* PS bool constant */
|
||||
switch(pPriv->id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0));
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0));
|
||||
break;
|
||||
}
|
||||
|
||||
/* Shader */
|
||||
vs_conf.shader_addr = accel_state->vs_mc_addr;
|
||||
vs_conf.shader_size = accel_state->vs_size;
|
||||
vs_conf.num_gprs = 2;
|
||||
vs_conf.stack_size = 0;
|
||||
vs_conf.bo = accel_state->shaders_bo;
|
||||
r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
ps_conf.shader_addr = accel_state->ps_mc_addr;
|
||||
ps_conf.shader_size = accel_state->ps_size;
|
||||
ps_conf.num_gprs = 3;
|
||||
ps_conf.stack_size = 1;
|
||||
ps_conf.uncached_first_inst = 1;
|
||||
ps_conf.clamp_consts = 0;
|
||||
ps_conf.export_mode = 2;
|
||||
ps_conf.bo = accel_state->shaders_bo;
|
||||
r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
/* PS alu constants */
|
||||
r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps,
|
||||
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
|
||||
|
||||
/* Texture */
|
||||
switch(pPriv->id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
|
||||
|
||||
/* Y texture */
|
||||
tex_res.id = 0;
|
||||
tex_res.w = accel_state->src_obj[0].width;
|
||||
tex_res.h = accel_state->src_obj[0].height;
|
||||
tex_res.pitch = accel_state->src_obj[0].pitch;
|
||||
tex_res.depth = 0;
|
||||
tex_res.dim = SQ_TEX_DIM_2D;
|
||||
tex_res.base = 0;
|
||||
tex_res.mip_base = 0;
|
||||
tex_res.size = accel_state->src_size[0];
|
||||
tex_res.bo = accel_state->src_obj[0].bo;
|
||||
tex_res.mip_bo = accel_state->src_obj[0].bo;
|
||||
tex_res.surface = NULL;
|
||||
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
|
||||
tex_res.request_size = 1;
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
tex_res.tile_mode = 1;
|
||||
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* Y sampler */
|
||||
tex_samp.id = 0;
|
||||
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_z = SQ_TEX_WRAP;
|
||||
|
||||
/* xxx: switch to bicubic */
|
||||
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
|
||||
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
|
||||
tex_samp.mip_filter = 0; /* no mipmap */
|
||||
r600_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
/* U or V texture */
|
||||
tex_res.id = 1;
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.w = accel_state->src_obj[0].width >> 1;
|
||||
tex_res.h = accel_state->src_obj[0].height >> 1;
|
||||
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
tex_res.interlaced = 0;
|
||||
|
||||
tex_res.base = pPriv->planev_offset;
|
||||
tex_res.mip_base = pPriv->planev_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
tex_res.tile_mode = 1;
|
||||
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* U or V sampler */
|
||||
tex_samp.id = 1;
|
||||
r600_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
/* U or V texture */
|
||||
tex_res.id = 2;
|
||||
tex_res.format = FMT_8;
|
||||
tex_res.w = accel_state->src_obj[0].width >> 1;
|
||||
tex_res.h = accel_state->src_obj[0].height >> 1;
|
||||
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
|
||||
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
|
||||
tex_res.dst_sel_y = SQ_SEL_1;
|
||||
tex_res.dst_sel_z = SQ_SEL_1;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
tex_res.interlaced = 0;
|
||||
|
||||
tex_res.base = pPriv->planeu_offset;
|
||||
tex_res.mip_base = pPriv->planeu_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
tex_res.tile_mode = 1;
|
||||
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* UV sampler */
|
||||
tex_samp.id = 2;
|
||||
r600_set_tex_sampler(pScrn, &tex_samp);
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
|
||||
|
||||
/* YUV texture */
|
||||
tex_res.id = 0;
|
||||
tex_res.w = accel_state->src_obj[0].width;
|
||||
tex_res.h = accel_state->src_obj[0].height;
|
||||
tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
|
||||
tex_res.depth = 0;
|
||||
tex_res.dim = SQ_TEX_DIM_2D;
|
||||
tex_res.base = 0;
|
||||
tex_res.mip_base = 0;
|
||||
tex_res.size = accel_state->src_size[0];
|
||||
tex_res.bo = accel_state->src_obj[0].bo;
|
||||
tex_res.mip_bo = accel_state->src_obj[0].bo;
|
||||
|
||||
if (pPriv->id == FOURCC_UYVY)
|
||||
tex_res.format = FMT_GB_GR;
|
||||
else
|
||||
tex_res.format = FMT_BG_RG;
|
||||
tex_res.dst_sel_x = SQ_SEL_Y;
|
||||
tex_res.dst_sel_y = SQ_SEL_X;
|
||||
tex_res.dst_sel_z = SQ_SEL_Z;
|
||||
tex_res.dst_sel_w = SQ_SEL_1;
|
||||
|
||||
tex_res.request_size = 1;
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
tex_res.tile_mode = 1;
|
||||
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
/* YUV sampler */
|
||||
tex_samp.id = 0;
|
||||
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
|
||||
tex_samp.clamp_z = SQ_TEX_WRAP;
|
||||
|
||||
/* xxx: switch to bicubic */
|
||||
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
|
||||
|
||||
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
|
||||
tex_samp.mip_filter = 0; /* no mipmap */
|
||||
r600_set_tex_sampler(pScrn, &tex_samp);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
cb_conf.id = 0;
|
||||
cb_conf.w = accel_state->dst_obj.pitch;
|
||||
cb_conf.h = accel_state->dst_obj.height;
|
||||
cb_conf.base = 0;
|
||||
cb_conf.bo = accel_state->dst_obj.bo;
|
||||
cb_conf.surface = accel_state->dst_obj.surface;
|
||||
|
||||
switch (accel_state->dst_obj.bpp) {
|
||||
case 16:
|
||||
if (pPixmap->drawable.depth == 15) {
|
||||
cb_conf.format = COLOR_1_5_5_5;
|
||||
cb_conf.comp_swap = 1; /* ARGB */
|
||||
} else {
|
||||
cb_conf.format = COLOR_5_6_5;
|
||||
cb_conf.comp_swap = 2; /* RGB */
|
||||
}
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
cb_conf.endian = ENDIAN_8IN16;
|
||||
#endif
|
||||
break;
|
||||
case 32:
|
||||
cb_conf.format = COLOR_8_8_8_8;
|
||||
cb_conf.comp_swap = 1; /* ARGB */
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
cb_conf.endian = ENDIAN_8IN32;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
cb_conf.source_format = 1;
|
||||
cb_conf.blend_clamp = 1;
|
||||
cb_conf.pmask = 0xf;
|
||||
cb_conf.rop = 3;
|
||||
if (accel_state->dst_obj.tiling_flags == 0)
|
||||
cb_conf.array_mode = 1;
|
||||
r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
|
||||
|
||||
r600_set_spi(pScrn, (1 - 1), 1);
|
||||
|
||||
vs_alu_consts[0] = 1.0 / pPriv->w;
|
||||
vs_alu_consts[1] = 1.0 / pPriv->h;
|
||||
vs_alu_consts[2] = 0.0;
|
||||
vs_alu_consts[3] = 0.0;
|
||||
|
||||
/* VS alu constants */
|
||||
r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs,
|
||||
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
|
||||
|
||||
if (pPriv->vsync) {
|
||||
xf86CrtcPtr crtc;
|
||||
if (pPriv->desired_crtc)
|
||||
crtc = pPriv->desired_crtc;
|
||||
else
|
||||
crtc = radeon_pick_best_crtc(pScrn, FALSE,
|
||||
pPriv->drw_x,
|
||||
pPriv->drw_x + pPriv->dst_w,
|
||||
pPriv->drw_y,
|
||||
pPriv->drw_y + pPriv->dst_h);
|
||||
if (crtc)
|
||||
r600_cp_wait_vline_sync(pScrn, pPixmap,
|
||||
crtc,
|
||||
pPriv->drw_y - crtc->y,
|
||||
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
|
||||
}
|
||||
|
||||
while (nBox--) {
|
||||
float srcX, srcY, srcw, srch;
|
||||
int dstX, dstY, dstw, dsth;
|
||||
float *vb;
|
||||
|
||||
|
||||
dstX = pBox->x1 + dstxoff;
|
||||
dstY = pBox->y1 + dstyoff;
|
||||
dstw = pBox->x2 - pBox->x1;
|
||||
dsth = pBox->y2 - pBox->y1;
|
||||
|
||||
srcX = pPriv->src_x;
|
||||
srcX += ((pBox->x1 - pPriv->drw_x) *
|
||||
pPriv->src_w) / (float)pPriv->dst_w;
|
||||
srcY = pPriv->src_y;
|
||||
srcY += ((pBox->y1 - pPriv->drw_y) *
|
||||
pPriv->src_h) / (float)pPriv->dst_h;
|
||||
|
||||
srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
|
||||
srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
|
||||
|
||||
vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
|
||||
|
||||
vb[0] = (float)dstX;
|
||||
vb[1] = (float)dstY;
|
||||
vb[2] = (float)srcX;
|
||||
vb[3] = (float)srcY;
|
||||
|
||||
vb[4] = (float)dstX;
|
||||
vb[5] = (float)(dstY + dsth);
|
||||
vb[6] = (float)srcX;
|
||||
vb[7] = (float)(srcY + srch);
|
||||
|
||||
vb[8] = (float)(dstX + dstw);
|
||||
vb[9] = (float)(dstY + dsth);
|
||||
vb[10] = (float)(srcX + srcw);
|
||||
vb[11] = (float)(srcY + srch);
|
||||
|
||||
radeon_vbo_commit(pScrn, &accel_state->vbo);
|
||||
|
||||
pBox++;
|
||||
}
|
||||
|
||||
r600_finish_op(pScrn, 16);
|
||||
|
||||
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
|
||||
}
|
||||
1254
src/r6xx_accel.c
Normal file
1254
src/r6xx_accel.c
Normal file
File diff suppressed because it is too large
Load diff
1029
src/radeon.h
Normal file
1029
src/radeon.h
Normal file
File diff suppressed because it is too large
Load diff
999
src/radeon_accel.c
Normal file
999
src/radeon_accel.c
Normal file
|
|
@ -0,0 +1,999 @@
|
|||
/*
|
||||
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
|
||||
* VA Linux Systems Inc., Fremont, California.
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation on the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
|
||||
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@xfree86.org>
|
||||
* Rickard E. Faith <faith@valinux.com>
|
||||
* Alan Hourihane <alanh@fairlite.demon.co.uk>
|
||||
*
|
||||
* Credits:
|
||||
*
|
||||
* Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source
|
||||
* code to his Radeon driver. Portions of this file are based on the
|
||||
* initialization code for that driver.
|
||||
*
|
||||
* References:
|
||||
*
|
||||
* !!!! FIXME !!!!
|
||||
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
|
||||
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
|
||||
* 1999.
|
||||
*
|
||||
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
|
||||
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
|
||||
*
|
||||
* Notes on unimplemented XAA optimizations:
|
||||
*
|
||||
* SetClipping: This has been removed as XAA expects 16bit registers
|
||||
* for full clipping.
|
||||
* TwoPointLine: The Radeon supports this. Not Bresenham.
|
||||
* DashedLine with non-power-of-two pattern length: Apparently, there is
|
||||
* no way to set the length of the pattern -- it is always
|
||||
* assumed to be 8 or 32 (or 1024?).
|
||||
* ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference
|
||||
* Manual where it states that monochrome expansion of frame
|
||||
* buffer data is not supported.
|
||||
* CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid
|
||||
* direct/indirect method. If we had more data registers,
|
||||
* then we could do better. If XAA supported a trigger write
|
||||
* address, the code would be simpler.
|
||||
* Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8
|
||||
* pattern from frame buffer memory.
|
||||
* ImageWrites: Same as CPUToScreenColorExpandFill
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
/* Driver data structures */
|
||||
#include "radeon.h"
|
||||
#include "radeon_glamor.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "r600_reg.h"
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_version.h"
|
||||
|
||||
#include "ati_pciids_gen.h"
|
||||
|
||||
/* Line support */
|
||||
#include "miline.h"
|
||||
|
||||
/* X and server generic header files */
|
||||
#include "xf86.h"
|
||||
|
||||
static int RADEONDRMGetNumPipes(ScrnInfoPtr pScrn, int *num_pipes)
|
||||
{
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
|
||||
struct drm_radeon_info np2;
|
||||
np2.value = (unsigned long)num_pipes;
|
||||
np2.request = RADEON_INFO_NUM_GB_PIPES;
|
||||
return drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &np2, sizeof(np2));
|
||||
}
|
||||
|
||||
/* Initialize the acceleration hardware */
|
||||
void RADEONEngineInit(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
info->accel_state->num_gb_pipes = 0;
|
||||
|
||||
if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) {
|
||||
int num_pipes;
|
||||
|
||||
if(RADEONDRMGetNumPipes(pScrn, &num_pipes) < 0) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"Failed to determine num pipes from DRM, falling back to "
|
||||
"manual look-up!\n");
|
||||
info->accel_state->num_gb_pipes = 0;
|
||||
} else {
|
||||
info->accel_state->num_gb_pipes = num_pipes;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int radeon_cs_space_remaining(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
|
||||
return (info->cs->ndw - info->cs->cdw);
|
||||
}
|
||||
|
||||
void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap)
|
||||
{
|
||||
switch(swap) {
|
||||
case RADEON_HOST_DATA_SWAP_HDW:
|
||||
{
|
||||
unsigned int *d = (unsigned int *)dst;
|
||||
unsigned int *s = (unsigned int *)src;
|
||||
unsigned int nwords = size >> 2;
|
||||
|
||||
for (; nwords > 0; --nwords, ++d, ++s)
|
||||
*d = ((*s & 0xffff) << 16) | ((*s >> 16) & 0xffff);
|
||||
return;
|
||||
}
|
||||
case RADEON_HOST_DATA_SWAP_32BIT:
|
||||
if (((uintptr_t)dst & 1) || ((uintptr_t)src & 1)) {
|
||||
uint8_t *d = (uint8_t *)dst;
|
||||
uint8_t *s = (uint8_t *)src;
|
||||
unsigned int nwords = size >> 2;
|
||||
|
||||
for (; nwords > 0; --nwords, d+=4, s+=4) {
|
||||
d[0] = s[3];
|
||||
d[1] = s[2];
|
||||
d[2] = s[1];
|
||||
d[3] = s[0];
|
||||
}
|
||||
return;
|
||||
} else if (((uintptr_t)dst & 3) || ((uintptr_t)src & 3)) {
|
||||
/* copy 16bit wise */
|
||||
uint16_t *d = (uint16_t *)dst;
|
||||
uint16_t *s = (uint16_t *)src;
|
||||
unsigned int nwords = size >> 2;
|
||||
|
||||
for (; nwords > 0; --nwords, d+=2, s+=2) {
|
||||
d[0] = ((s[1] >> 8) & 0xff) | ((s[1] & 0xff) << 8);
|
||||
d[1] = ((s[0] >> 8) & 0xff) | ((s[0] & 0xff) << 8);
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
unsigned int *d = (unsigned int *)dst;
|
||||
unsigned int *s = (unsigned int *)src;
|
||||
unsigned int nwords = size >> 2;
|
||||
|
||||
for (; nwords > 0; --nwords, ++d, ++s)
|
||||
#ifdef __powerpc__
|
||||
asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d));
|
||||
#else
|
||||
*d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00)
|
||||
| ((*s & 0xff00) << 8) | ((*s & 0xff) << 24);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
case RADEON_HOST_DATA_SWAP_16BIT:
|
||||
{
|
||||
unsigned short *d = (unsigned short *)dst;
|
||||
unsigned short *s = (unsigned short *)src;
|
||||
unsigned int nwords = size >> 1;
|
||||
|
||||
for (; nwords > 0; --nwords, ++d, ++s)
|
||||
#ifdef __powerpc__
|
||||
asm volatile("sthbrx %0,0,%1" : : "r" (*s), "r" (d));
|
||||
#else
|
||||
*d = (*s >> 8) | (*s << 8);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (src != dst)
|
||||
memcpy(dst, src, size);
|
||||
}
|
||||
|
||||
|
||||
|
||||
Bool RADEONAccelInit(ScreenPtr pScreen)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
|
||||
if (info->directRenderingEnabled) {
|
||||
if (info->use_glamor) {
|
||||
if (!radeon_glamor_init(pScreen)) {
|
||||
info->use_glamor = FALSE;
|
||||
return FALSE;
|
||||
}
|
||||
} else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
|
||||
if (!EVERGREENDrawInit(pScreen))
|
||||
return FALSE;
|
||||
} else
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600) {
|
||||
if (!R600DrawInit(pScreen))
|
||||
return FALSE;
|
||||
} else {
|
||||
if (!RADEONDrawInit(pScreen))
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void RADEONInit3DEngineInternal(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
uint32_t vap_cntl;
|
||||
|
||||
info->accel_state->texW[0] = info->accel_state->texH[0] =
|
||||
info->accel_state->texW[1] = info->accel_state->texH[1] = 1;
|
||||
|
||||
if (IS_R300_3D || IS_R500_3D) {
|
||||
|
||||
BEGIN_RING(2*3);
|
||||
OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
|
||||
OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
|
||||
OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*3);
|
||||
OUT_RING_REG(R300_GB_AA_CONFIG, 0);
|
||||
OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
|
||||
OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*4);
|
||||
OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
|
||||
OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
|
||||
R300_COLOR_ROUND_NEAREST));
|
||||
OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
|
||||
R300_ALPHA0_SHADING_GOURAUD |
|
||||
R300_RGB1_SHADING_GOURAUD |
|
||||
R300_ALPHA1_SHADING_GOURAUD |
|
||||
R300_RGB2_SHADING_GOURAUD |
|
||||
R300_ALPHA2_SHADING_GOURAUD |
|
||||
R300_RGB3_SHADING_GOURAUD |
|
||||
R300_ALPHA3_SHADING_GOURAUD));
|
||||
OUT_RING_REG(R300_GA_OFFSET, 0);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*5);
|
||||
OUT_RING_REG(R300_SU_TEX_WRAP, 0);
|
||||
OUT_RING_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
|
||||
OUT_RING_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
|
||||
OUT_RING_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
|
||||
OUT_RING_REG(R300_SU_DEPTH_OFFSET, 0);
|
||||
ADVANCE_RING();
|
||||
|
||||
/* setup the VAP */
|
||||
if (info->accel_state->has_tcl)
|
||||
vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
|
||||
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
|
||||
(9 << R300_VF_MAX_VTX_NUM_SHIFT));
|
||||
else
|
||||
vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
|
||||
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
|
||||
(5 << R300_VF_MAX_VTX_NUM_SHIFT));
|
||||
|
||||
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_R350))
|
||||
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
|
||||
else if (info->ChipFamily == CHIP_FAMILY_RV530)
|
||||
vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
|
||||
else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_R420))
|
||||
vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
|
||||
else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_R580) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_RV560) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_RV570))
|
||||
vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
|
||||
else
|
||||
vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
|
||||
|
||||
if (info->accel_state->has_tcl)
|
||||
BEGIN_RING(2*15);
|
||||
else
|
||||
BEGIN_RING(2*9);
|
||||
OUT_RING_REG(R300_VAP_VTX_STATE_CNTL, 0);
|
||||
OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
|
||||
|
||||
if (info->accel_state->has_tcl)
|
||||
OUT_RING_REG(R300_VAP_CNTL_STATUS, 0);
|
||||
else
|
||||
OUT_RING_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
|
||||
OUT_RING_REG(R300_VAP_CNTL, vap_cntl);
|
||||
OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
|
||||
OUT_RING_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
|
||||
OUT_RING_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
|
||||
|
||||
OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
|
||||
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
|
||||
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
|
||||
<< R300_WRITE_ENA_0_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
|
||||
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
|
||||
<< R300_WRITE_ENA_1_SHIFT)));
|
||||
OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
|
||||
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
|
||||
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
|
||||
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
|
||||
<< R300_WRITE_ENA_2_SHIFT)));
|
||||
|
||||
if (info->accel_state->has_tcl) {
|
||||
OUT_RING_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
|
||||
OUT_RING_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
|
||||
OUT_RING_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
|
||||
OUT_RING_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
|
||||
OUT_RING_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
|
||||
OUT_RING_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
|
||||
}
|
||||
ADVANCE_RING();
|
||||
|
||||
/* pre-load the vertex shaders */
|
||||
if (info->accel_state->has_tcl) {
|
||||
BEGIN_RING(2*37);
|
||||
/* exa composite shader program */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0));
|
||||
/* PVS inst 0 - dst X,Y */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
|
||||
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 1 - src X */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_X));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 2 - src Y */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_Y));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(1) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 3 - src X / w */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(1) |
|
||||
R300_PVS_DST_WE_X));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 4 - src y / h */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(1) |
|
||||
R300_PVS_DST_WE_Y));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(1) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 5 - mask X */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_Z));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(2) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 6 - mask Y */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(3) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 7 - mask X / w */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(2) |
|
||||
R300_PVS_DST_WE_X));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(2) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 8 - mask y / h */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(2) |
|
||||
R300_PVS_DST_WE_Y));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
|
||||
R300_PVS_SRC_OFFSET(3) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
ADVANCE_RING();
|
||||
|
||||
/* Xv shader program */
|
||||
BEGIN_RING(2*9);
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9));
|
||||
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
|
||||
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(1) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
ADVANCE_RING();
|
||||
|
||||
/* Xv bicubic shader program */
|
||||
BEGIN_RING(2*13);
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11));
|
||||
/* PVS inst 0 */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(0) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
|
||||
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(0) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 1 */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(1) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
|
||||
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(6) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
|
||||
/* PVS inst 2 */
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
|
||||
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
|
||||
R300_PVS_DST_OFFSET(2) |
|
||||
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
|
||||
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
|
||||
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
|
||||
R300_PVS_SRC_OFFSET(7) |
|
||||
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
|
||||
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
/* pre-load the RS instructions */
|
||||
BEGIN_RING(2*4);
|
||||
if (IS_R300_3D) {
|
||||
/* rasterizer source table
|
||||
* R300_RS_TEX_PTR is the offset into the input RS stream
|
||||
* 0,1 are tex0
|
||||
* 2,3 are tex1
|
||||
*/
|
||||
OUT_RING_REG(R300_RS_IP_0,
|
||||
(R300_RS_TEX_PTR(0) |
|
||||
R300_RS_SEL_S(R300_RS_SEL_C0) |
|
||||
R300_RS_SEL_T(R300_RS_SEL_C1) |
|
||||
R300_RS_SEL_R(R300_RS_SEL_K0) |
|
||||
R300_RS_SEL_Q(R300_RS_SEL_K1)));
|
||||
OUT_RING_REG(R300_RS_IP_1,
|
||||
(R300_RS_TEX_PTR(2) |
|
||||
R300_RS_SEL_S(R300_RS_SEL_C0) |
|
||||
R300_RS_SEL_T(R300_RS_SEL_C1) |
|
||||
R300_RS_SEL_R(R300_RS_SEL_K0) |
|
||||
R300_RS_SEL_Q(R300_RS_SEL_K1)));
|
||||
/* src tex */
|
||||
/* R300_INST_TEX_ID - select the RS source table entry
|
||||
* R300_INST_TEX_ADDR - the FS temp register for the texture data
|
||||
*/
|
||||
OUT_RING_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
|
||||
R300_RS_INST_TEX_CN_WRITE |
|
||||
R300_INST_TEX_ADDR(0)));
|
||||
/* mask tex */
|
||||
OUT_RING_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
|
||||
R300_RS_INST_TEX_CN_WRITE |
|
||||
R300_INST_TEX_ADDR(1)));
|
||||
|
||||
} else {
|
||||
/* rasterizer source table
|
||||
* R300_RS_TEX_PTR is the offset into the input RS stream
|
||||
* 0,1 are tex0
|
||||
* 2,3 are tex1
|
||||
*/
|
||||
OUT_RING_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
|
||||
(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
|
||||
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
|
||||
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
|
||||
|
||||
OUT_RING_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
|
||||
(3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
|
||||
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
|
||||
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
|
||||
/* src tex */
|
||||
/* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
|
||||
* R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
|
||||
*/
|
||||
OUT_RING_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
|
||||
R500_RS_INST_TEX_CN_WRITE |
|
||||
(0 << R500_RS_INST_TEX_ADDR_SHIFT)));
|
||||
/* mask tex */
|
||||
OUT_RING_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
|
||||
R500_RS_INST_TEX_CN_WRITE |
|
||||
(1 << R500_RS_INST_TEX_ADDR_SHIFT)));
|
||||
}
|
||||
ADVANCE_RING();
|
||||
|
||||
if (IS_R300_3D)
|
||||
BEGIN_RING(2*4);
|
||||
else {
|
||||
BEGIN_RING(2*6);
|
||||
OUT_RING_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
|
||||
OUT_RING_REG(R500_US_FC_CTRL, 0);
|
||||
}
|
||||
OUT_RING_REG(R300_US_W_FMT, 0);
|
||||
OUT_RING_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
|
||||
R300_OUT_FMT_C0_SEL_BLUE |
|
||||
R300_OUT_FMT_C1_SEL_GREEN |
|
||||
R300_OUT_FMT_C2_SEL_RED |
|
||||
R300_OUT_FMT_C3_SEL_ALPHA));
|
||||
OUT_RING_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
|
||||
R300_OUT_FMT_C0_SEL_BLUE |
|
||||
R300_OUT_FMT_C1_SEL_GREEN |
|
||||
R300_OUT_FMT_C2_SEL_RED |
|
||||
R300_OUT_FMT_C3_SEL_ALPHA));
|
||||
OUT_RING_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
|
||||
R300_OUT_FMT_C0_SEL_BLUE |
|
||||
R300_OUT_FMT_C1_SEL_GREEN |
|
||||
R300_OUT_FMT_C2_SEL_RED |
|
||||
R300_OUT_FMT_C3_SEL_ALPHA));
|
||||
ADVANCE_RING();
|
||||
|
||||
|
||||
BEGIN_RING(2*3);
|
||||
OUT_RING_REG(R300_FG_DEPTH_SRC, 0);
|
||||
OUT_RING_REG(R300_FG_FOG_BLEND, 0);
|
||||
OUT_RING_REG(R300_FG_ALPHA_FUNC, 0);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*13);
|
||||
OUT_RING_REG(R300_RB3D_ABLENDCNTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_ZSTENCILCNTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
|
||||
OUT_RING_REG(R300_RB3D_BW_CNTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_ZCNTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_ZTOP, 0);
|
||||
OUT_RING_REG(R300_RB3D_ROPCNTL, 0);
|
||||
|
||||
OUT_RING_REG(R300_RB3D_AARESOLVE_CTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
|
||||
R300_GREEN_MASK_EN |
|
||||
R300_RED_MASK_EN |
|
||||
R300_ALPHA_MASK_EN));
|
||||
OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
|
||||
OUT_RING_REG(R300_RB3D_CCTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_DITHER_CTL, 0);
|
||||
OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*5);
|
||||
OUT_RING_REG(R300_SC_EDGERULE, 0xA5294A5);
|
||||
if (IS_R300_3D) {
|
||||
/* clip has offset 1440 */
|
||||
OUT_RING_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
|
||||
(1440 << R300_CLIP_Y_SHIFT)));
|
||||
OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
|
||||
(4080 << R300_CLIP_Y_SHIFT)));
|
||||
} else {
|
||||
OUT_RING_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
|
||||
(0 << R300_CLIP_Y_SHIFT)));
|
||||
OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
|
||||
(4080 << R300_CLIP_Y_SHIFT)));
|
||||
}
|
||||
OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
|
||||
OUT_RING_REG(R300_SC_SCREENDOOR, 0xffffff);
|
||||
ADVANCE_RING();
|
||||
} else if (IS_R200_3D) {
|
||||
|
||||
BEGIN_RING(2*6);
|
||||
if (info->ChipFamily == CHIP_FAMILY_RS300) {
|
||||
OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
|
||||
} else {
|
||||
OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, 0);
|
||||
}
|
||||
OUT_RING_REG(R200_PP_CNTL_X, 0);
|
||||
OUT_RING_REG(R200_PP_TXMULTI_CTL_0, 0);
|
||||
OUT_RING_REG(R200_SE_VTX_STATE_CNTL, 0);
|
||||
OUT_RING_REG(R200_SE_VTE_CNTL, 0);
|
||||
OUT_RING_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
|
||||
R200_VAP_VF_MAX_VTX_NUM);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*4);
|
||||
OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, 0);
|
||||
OUT_RING_REG(R200_RE_CNTL, 0);
|
||||
OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
|
||||
OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
|
||||
RADEON_BFACE_SOLID |
|
||||
RADEON_FFACE_SOLID |
|
||||
RADEON_VTX_PIX_CENTER_OGL |
|
||||
RADEON_ROUND_MODE_ROUND |
|
||||
RADEON_ROUND_PREC_4TH_PIX));
|
||||
ADVANCE_RING();
|
||||
} else {
|
||||
BEGIN_RING(2*2);
|
||||
if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
|
||||
(info->ChipFamily == CHIP_FAMILY_RV200))
|
||||
OUT_RING_REG(RADEON_SE_CNTL_STATUS, 0);
|
||||
else
|
||||
OUT_RING_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
|
||||
OUT_RING_REG(RADEON_SE_COORD_FMT,
|
||||
RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
|
||||
RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 |
|
||||
RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 |
|
||||
RADEON_TEX1_W_ROUTING_USE_W0);
|
||||
ADVANCE_RING();
|
||||
|
||||
BEGIN_RING(2*2);
|
||||
OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
|
||||
OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
|
||||
RADEON_BFACE_SOLID |
|
||||
RADEON_FFACE_SOLID |
|
||||
RADEON_VTX_PIX_CENTER_OGL |
|
||||
RADEON_ROUND_MODE_ROUND |
|
||||
RADEON_ROUND_PREC_4TH_PIX));
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* inserts a wait for vline in the command stream */
|
||||
void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix,
|
||||
xf86CrtcPtr crtc, int start, int stop)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
drmmode_crtc_private_ptr drmmode_crtc;
|
||||
|
||||
if (!crtc)
|
||||
return;
|
||||
|
||||
if (!crtc->enabled)
|
||||
return;
|
||||
|
||||
if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
|
||||
return;
|
||||
|
||||
start = max(start, crtc->y);
|
||||
stop = min(stop, crtc->y + crtc->mode.VDisplay);
|
||||
|
||||
if (start >= stop)
|
||||
return;
|
||||
|
||||
if (!IS_AVIVO_VARIANT) {
|
||||
/* on pre-r5xx vline starts at CRTC scanout */
|
||||
start -= crtc->y;
|
||||
stop -= crtc->y;
|
||||
}
|
||||
|
||||
drmmode_crtc = crtc->driver_private;
|
||||
|
||||
BEGIN_RING(2*3);
|
||||
if (IS_AVIVO_VARIANT) {
|
||||
OUT_RING_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
|
||||
((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
|
||||
(stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
|
||||
AVIVO_D1MODE_VLINE_INV));
|
||||
} else {
|
||||
OUT_RING_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
|
||||
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
|
||||
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
|
||||
RADEON_CRTC_GUI_TRIG_VLINE_INV |
|
||||
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
|
||||
}
|
||||
OUT_RING_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
|
||||
RADEON_ENG_DISPLAY_SELECT_CRTC0));
|
||||
|
||||
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
|
||||
OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
|
||||
void RADEONInit3DEngine(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR (pScrn);
|
||||
|
||||
if (info->directRenderingEnabled) {
|
||||
RADEONInit3DEngineInternal(pScrn);
|
||||
}
|
||||
info->accel_state->XInited3D = TRUE;
|
||||
}
|
||||
537
src/radeon_bo_helper.c
Normal file
537
src/radeon_bo_helper.c
Normal file
|
|
@ -0,0 +1,537 @@
|
|||
/*
|
||||
* Copyright 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_glamor.h"
|
||||
#include "radeon_bo_gem.h"
|
||||
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
|
||||
static uint32_t
|
||||
radeon_get_gbm_format(int depth, int bitsPerPixel)
|
||||
{
|
||||
switch (depth) {
|
||||
#ifdef GBM_FORMAT_R8
|
||||
case 8:
|
||||
return GBM_FORMAT_R8;
|
||||
#endif
|
||||
case 15:
|
||||
return GBM_FORMAT_ARGB1555;
|
||||
case 16:
|
||||
return GBM_FORMAT_RGB565;
|
||||
case 32:
|
||||
return GBM_FORMAT_ARGB8888;
|
||||
case 30:
|
||||
return GBM_FORMAT_XRGB2101010;
|
||||
case 24:
|
||||
if (bitsPerPixel == 32)
|
||||
return GBM_FORMAT_XRGB8888;
|
||||
/* fall through */
|
||||
default:
|
||||
ErrorF("%s: Unsupported depth/bpp %d/%d\n", __func__, depth,
|
||||
bitsPerPixel);
|
||||
return ~0U;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* USE_GLAMOR */
|
||||
|
||||
|
||||
static const unsigned MicroBlockTable[5][3][2] = {
|
||||
/*linear tiled square-tiled */
|
||||
{{32, 1}, {8, 4}, {0, 0}}, /* 8 bits per pixel */
|
||||
{{16, 1}, {8, 2}, {4, 4}}, /* 16 bits per pixel */
|
||||
{{ 8, 1}, {4, 2}, {0, 0}}, /* 32 bits per pixel */
|
||||
{{ 4, 1}, {0, 0}, {2, 2}}, /* 64 bits per pixel */
|
||||
{{ 2, 1}, {0, 0}, {0, 0}} /* 128 bits per pixel */
|
||||
};
|
||||
|
||||
/* Return true if macrotiling can be enabled */
|
||||
static Bool RADEONMacroSwitch(int width, int height, int bpp,
|
||||
uint32_t flags, Bool rv350_mode)
|
||||
{
|
||||
unsigned tilew, tileh, microtiled, logbpp;
|
||||
|
||||
logbpp = RADEONLog2(bpp / 8);
|
||||
if (logbpp > 4)
|
||||
return 0;
|
||||
|
||||
microtiled = !!(flags & RADEON_TILING_MICRO);
|
||||
tilew = MicroBlockTable[logbpp][microtiled][0] * 8;
|
||||
tileh = MicroBlockTable[logbpp][microtiled][1] * 8;
|
||||
|
||||
/* See TX_FILTER1_n.MACRO_SWITCH. */
|
||||
if (rv350_mode) {
|
||||
return width >= tilew && height >= tileh;
|
||||
} else {
|
||||
return width > tilew && height > tileh;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned eg_tile_split_opp(unsigned tile_split)
|
||||
{
|
||||
switch (tile_split) {
|
||||
case 0: tile_split = 64; break;
|
||||
case 1: tile_split = 128; break;
|
||||
case 2: tile_split = 256; break;
|
||||
case 3: tile_split = 512; break;
|
||||
default:
|
||||
case 4: tile_split = 1024; break;
|
||||
case 5: tile_split = 2048; break;
|
||||
case 6: tile_split = 4096; break;
|
||||
}
|
||||
return tile_split;
|
||||
}
|
||||
|
||||
Bool
|
||||
radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
|
||||
int width, int height, int cpp, uint32_t tiling_flags,
|
||||
int usage_hint)
|
||||
{
|
||||
memset(surface, 0, sizeof(struct radeon_surface));
|
||||
|
||||
surface->npix_x = width;
|
||||
/* need to align height to 8 for old kernel */
|
||||
surface->npix_y = RADEON_ALIGN(height, 8);
|
||||
surface->npix_z = 1;
|
||||
surface->blk_w = 1;
|
||||
surface->blk_h = 1;
|
||||
surface->blk_d = 1;
|
||||
surface->array_size = 1;
|
||||
surface->last_level = 0;
|
||||
surface->bpe = cpp;
|
||||
surface->nsamples = 1;
|
||||
if (height < 128) {
|
||||
/* disable 2d tiling for small surface to work around
|
||||
* the fact that ddx align height to 8 pixel for old
|
||||
* obscure reason i can't remember
|
||||
*/
|
||||
tiling_flags &= ~RADEON_TILING_MACRO;
|
||||
}
|
||||
|
||||
surface->flags = RADEON_SURF_SCANOUT | RADEON_SURF_HAS_TILE_MODE_INDEX |
|
||||
RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
|
||||
|
||||
if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
|
||||
surface->flags |= RADEON_SURF_ZBUFFER;
|
||||
surface->flags |= RADEON_SURF_SBUFFER;
|
||||
}
|
||||
|
||||
if ((tiling_flags & RADEON_TILING_MACRO)) {
|
||||
surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
|
||||
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
|
||||
} else if ((tiling_flags & RADEON_TILING_MICRO)) {
|
||||
surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
|
||||
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
|
||||
} else
|
||||
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
|
||||
|
||||
if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
|
||||
surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
|
||||
RADEON_TILING_EG_BANKW_MASK;
|
||||
surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
|
||||
RADEON_TILING_EG_BANKH_MASK;
|
||||
surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
|
||||
RADEON_TILING_EG_TILE_SPLIT_MASK);
|
||||
if (surface->flags & RADEON_SURF_SBUFFER) {
|
||||
surface->stencil_tile_split =
|
||||
(tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
|
||||
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
|
||||
}
|
||||
surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
|
||||
RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
|
||||
}
|
||||
|
||||
if (radeon_surface_best(info->surf_man, surface))
|
||||
return FALSE;
|
||||
|
||||
if (radeon_surface_init(info->surf_man, surface))
|
||||
return FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that
|
||||
* can hold it.
|
||||
*/
|
||||
struct radeon_buffer *
|
||||
radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
|
||||
int usage_hint, int bitsPerPixel, int *new_pitch,
|
||||
struct radeon_surface *new_surface, uint32_t *new_tiling)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int pitch, base_align;
|
||||
uint32_t size, heighta;
|
||||
int cpp = bitsPerPixel / 8;
|
||||
uint32_t tiling = 0, flags = 0;
|
||||
struct radeon_surface surface;
|
||||
struct radeon_buffer *bo;
|
||||
int domain = RADEON_GEM_DOMAIN_VRAM;
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
if (info->use_glamor &&
|
||||
!(usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
|
||||
info->shadow_primary)) {
|
||||
uint32_t bo_use = GBM_BO_USE_RENDERING;
|
||||
uint32_t gbm_format = radeon_get_gbm_format(depth, bitsPerPixel);
|
||||
|
||||
if (gbm_format == ~0U)
|
||||
return NULL;
|
||||
|
||||
bo = calloc(1, sizeof(struct radeon_buffer));
|
||||
if (!bo)
|
||||
return NULL;
|
||||
|
||||
bo->ref_count = 1;
|
||||
|
||||
if (bitsPerPixel == pScrn->bitsPerPixel)
|
||||
bo_use |= GBM_BO_USE_SCANOUT;
|
||||
|
||||
if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
|
||||
info->shadow_primary) ||
|
||||
(usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED)
|
||||
bo_use |= GBM_BO_USE_LINEAR;
|
||||
|
||||
bo->bo.gbm = gbm_bo_create(info->gbm, width, height, gbm_format, bo_use);
|
||||
if (!bo->bo.gbm) {
|
||||
free(bo);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
bo->flags |= RADEON_BO_FLAGS_GBM;
|
||||
|
||||
if (new_pitch)
|
||||
*new_pitch = gbm_bo_get_stride(bo->bo.gbm);
|
||||
|
||||
return bo;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (usage_hint) {
|
||||
if (info->allowColorTiling) {
|
||||
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO)
|
||||
tiling |= RADEON_TILING_MACRO;
|
||||
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MICRO)
|
||||
tiling |= RADEON_TILING_MICRO;
|
||||
}
|
||||
if (usage_hint & RADEON_CREATE_PIXMAP_DEPTH)
|
||||
tiling |= RADEON_TILING_MACRO | RADEON_TILING_MICRO;
|
||||
|
||||
if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
|
||||
info->shadow_primary) ||
|
||||
(usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED) {
|
||||
tiling = 0;
|
||||
domain = RADEON_GEM_DOMAIN_GTT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Small pixmaps must not be macrotiled on R300, hw cannot sample them
|
||||
* correctly because samplers automatically switch to macrolinear. */
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R300 &&
|
||||
info->ChipFamily <= CHIP_FAMILY_RS740 &&
|
||||
(tiling & RADEON_TILING_MACRO) &&
|
||||
!RADEONMacroSwitch(width, height, bitsPerPixel, tiling,
|
||||
info->ChipFamily >= CHIP_FAMILY_RV350)) {
|
||||
tiling &= ~RADEON_TILING_MACRO;
|
||||
}
|
||||
|
||||
heighta = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling));
|
||||
pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp;
|
||||
base_align = drmmode_get_base_align(pScrn, cpp, tiling);
|
||||
size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
|
||||
|
||||
if (width && info->surf_man) {
|
||||
if (!radeon_surface_initialize(info, &surface, width, height, cpp,
|
||||
tiling, usage_hint))
|
||||
return NULL;
|
||||
|
||||
size = surface.bo_size;
|
||||
base_align = surface.bo_alignment;
|
||||
pitch = surface.level[0].pitch_bytes;
|
||||
tiling = 0;
|
||||
switch (surface.level[0].mode) {
|
||||
case RADEON_SURF_MODE_2D:
|
||||
tiling |= RADEON_TILING_MACRO;
|
||||
tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
|
||||
tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
|
||||
tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
|
||||
if (surface.tile_split)
|
||||
tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
|
||||
if (surface.flags & RADEON_SURF_SBUFFER)
|
||||
tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
|
||||
break;
|
||||
case RADEON_SURF_MODE_1D:
|
||||
tiling |= RADEON_TILING_MICRO;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (new_surface)
|
||||
*new_surface = surface;
|
||||
}
|
||||
|
||||
if (tiling)
|
||||
flags |= RADEON_GEM_NO_CPU_ACCESS;
|
||||
|
||||
bo = calloc(1, sizeof(struct radeon_buffer));
|
||||
if (!bo)
|
||||
return NULL;
|
||||
|
||||
bo->ref_count = 1;
|
||||
bo->bo.radeon = radeon_bo_open(info->bufmgr, 0, size, base_align,
|
||||
domain, flags);
|
||||
|
||||
if (bo && tiling && radeon_bo_set_tiling(bo->bo.radeon, tiling, pitch) == 0)
|
||||
*new_tiling = tiling;
|
||||
|
||||
*new_pitch = pitch;
|
||||
return bo;
|
||||
}
|
||||
|
||||
|
||||
/* Flush and wait for the BO to become idle */
|
||||
void
|
||||
radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
if (info->use_glamor) {
|
||||
radeon_glamor_finish(scrn);
|
||||
return;
|
||||
}
|
||||
|
||||
radeon_cs_flush_indirect(scrn);
|
||||
radeon_bo_wait(bo->bo.radeon);
|
||||
}
|
||||
|
||||
|
||||
/* Clear the pixmap contents to black */
|
||||
void
|
||||
radeon_pixmap_clear(PixmapPtr pixmap)
|
||||
{
|
||||
ScreenPtr screen = pixmap->drawable.pScreen;
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen));
|
||||
GCPtr gc = GetScratchGC(pixmap->drawable.depth, screen);
|
||||
Bool force = info->accel_state->force;
|
||||
xRectangle rect;
|
||||
|
||||
info->accel_state->force = TRUE;
|
||||
ValidateGC(&pixmap->drawable, gc);
|
||||
rect.x = 0;
|
||||
rect.y = 0;
|
||||
rect.width = pixmap->drawable.width;
|
||||
rect.height = pixmap->drawable.height;
|
||||
gc->ops->PolyFillRect(&pixmap->drawable, gc, 1, &rect);
|
||||
FreeScratchGC(gc);
|
||||
info->accel_state->force = force;
|
||||
}
|
||||
|
||||
/* Get GEM handle for the pixmap */
|
||||
Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
|
||||
{
|
||||
struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap);
|
||||
#ifdef USE_GLAMOR
|
||||
ScreenPtr screen = pixmap->drawable.pScreen;
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
#endif
|
||||
|
||||
if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM)) {
|
||||
*handle = bo->bo.radeon->handle;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
if (info->use_glamor) {
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
CARD16 stride;
|
||||
CARD32 size;
|
||||
int fd, r;
|
||||
|
||||
if (!priv) {
|
||||
priv = calloc(1, sizeof(*priv));
|
||||
radeon_set_pixmap_private(pixmap, priv);
|
||||
}
|
||||
|
||||
if (priv->handle_valid) {
|
||||
*handle = priv->handle;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
fd = glamor_fd_from_pixmap(screen, pixmap, &stride, &size);
|
||||
if (fd < 0)
|
||||
return FALSE;
|
||||
|
||||
r = drmPrimeFDToHandle(pRADEONEnt->fd, fd, &priv->handle);
|
||||
close(fd);
|
||||
if (r == 0) {
|
||||
struct drm_radeon_gem_set_tiling args = { .handle = priv->handle };
|
||||
|
||||
priv->handle_valid = TRUE;
|
||||
*handle = priv->handle;
|
||||
|
||||
if (drmCommandWriteRead(pRADEONEnt->fd,
|
||||
DRM_RADEON_GEM_GET_TILING, &args,
|
||||
sizeof(args)) == 0)
|
||||
priv->tiling_flags = args.tiling_flags;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
uint32_t radeon_get_pixmap_tiling_flags(PixmapPtr pPix)
|
||||
{
|
||||
#ifdef USE_GLAMOR
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
|
||||
|
||||
if (info->use_glamor) {
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pPix);
|
||||
|
||||
if (!priv || (!priv->bo && !priv->handle_valid)) {
|
||||
uint32_t handle;
|
||||
|
||||
radeon_get_pixmap_handle(pPix, &handle);
|
||||
priv = radeon_get_pixmap_private(pPix);
|
||||
}
|
||||
|
||||
return priv ? priv->tiling_flags : 0;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
return driver_priv ? driver_priv->tiling_flags : 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Bool radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p)
|
||||
{
|
||||
int handle;
|
||||
|
||||
if (radeon_gem_prime_share_bo(bo, &handle) != 0)
|
||||
return FALSE;
|
||||
|
||||
*handle_p = (void *)(long)handle;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
|
||||
struct radeon_surface *surface)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_buffer *bo;
|
||||
int ihandle = (int)(long)fd_handle;
|
||||
uint32_t size = ppix->devKind * ppix->drawable.height;
|
||||
Bool ret = FALSE;
|
||||
|
||||
if (ihandle == -1)
|
||||
return radeon_set_pixmap_bo(ppix, NULL);
|
||||
|
||||
bo = (struct radeon_buffer *)calloc(1, sizeof(struct radeon_buffer));
|
||||
if (!bo)
|
||||
goto error;
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
if (info->use_glamor) {
|
||||
struct gbm_import_fd_data data;
|
||||
uint32_t bo_use = GBM_BO_USE_RENDERING;
|
||||
|
||||
data.format = radeon_get_gbm_format(ppix->drawable.depth,
|
||||
ppix->drawable.bitsPerPixel);
|
||||
if (data.format == ~0U)
|
||||
goto error;
|
||||
|
||||
bo->ref_count = 1;
|
||||
|
||||
data.fd = ihandle;
|
||||
data.width = ppix->drawable.width;
|
||||
data.height = ppix->drawable.height;
|
||||
data.stride = ppix->devKind;
|
||||
|
||||
if (ppix->drawable.bitsPerPixel == pScrn->bitsPerPixel)
|
||||
bo_use |= GBM_BO_USE_SCANOUT;
|
||||
|
||||
bo->bo.gbm = gbm_bo_import(info->gbm, GBM_BO_IMPORT_FD, &data, bo_use);
|
||||
if (!bo->bo.gbm)
|
||||
goto error;
|
||||
|
||||
bo->flags |= RADEON_BO_FLAGS_GBM;
|
||||
|
||||
if (!radeon_glamor_create_textured_pixmap(ppix, bo)) {
|
||||
radeon_buffer_unref(&bo);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
ret = radeon_set_pixmap_bo(ppix, bo);
|
||||
/* radeon_set_pixmap_bo increments ref_count if it succeeds */
|
||||
radeon_buffer_unref(&bo);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
bo->bo.radeon = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
|
||||
if (!bo)
|
||||
goto error;
|
||||
|
||||
bo->ref_count = 1;
|
||||
ret = radeon_set_pixmap_bo(ppix, bo);
|
||||
if (!ret)
|
||||
goto error;
|
||||
|
||||
if (surface) {
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
uint32_t tiling_flags;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(ppix);
|
||||
tiling_flags = driver_priv->tiling_flags;
|
||||
|
||||
if (!radeon_surface_initialize(info, surface, ppix->drawable.width,
|
||||
ppix->drawable.height,
|
||||
ppix->drawable.bitsPerPixel / 8,
|
||||
tiling_flags, 0)) {
|
||||
ret = FALSE;
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* we have to post hack the surface to reflect the actual size
|
||||
of the shared pixmap */
|
||||
surface->level[0].pitch_bytes = ppix->devKind;
|
||||
surface->level[0].nblk_x = ppix->devKind / surface->bpe;
|
||||
}
|
||||
|
||||
error:
|
||||
close(ihandle);
|
||||
/* we have a reference from the alloc and one from set pixmap bo,
|
||||
drop one */
|
||||
radeon_buffer_unref(&bo);
|
||||
return ret;
|
||||
}
|
||||
113
src/radeon_bo_helper.h
Normal file
113
src/radeon_bo_helper.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef RADEON_BO_HELPER_H
|
||||
#define RADEON_BO_HELPER_H 1
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
#include <gbm.h>
|
||||
#endif
|
||||
|
||||
#define RADEON_BO_FLAGS_GBM 0x1
|
||||
|
||||
struct radeon_buffer {
|
||||
union {
|
||||
#ifdef USE_GLAMOR
|
||||
struct gbm_bo *gbm;
|
||||
#endif
|
||||
struct radeon_bo *radeon;
|
||||
} bo;
|
||||
uint32_t ref_count;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
extern struct radeon_buffer *
|
||||
radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
|
||||
int usage_hint, int bitsPerPixel, int *new_pitch,
|
||||
struct radeon_surface *new_surface, uint32_t *new_tiling);
|
||||
|
||||
extern void
|
||||
radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo);
|
||||
|
||||
extern void
|
||||
radeon_pixmap_clear(PixmapPtr pixmap);
|
||||
|
||||
extern uint32_t
|
||||
radeon_get_pixmap_tiling_flags(PixmapPtr pPix);
|
||||
|
||||
extern Bool
|
||||
radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p);
|
||||
|
||||
extern Bool
|
||||
radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
|
||||
struct radeon_surface *surface);
|
||||
|
||||
/**
|
||||
* get_drawable_pixmap() returns the backing pixmap for a given drawable.
|
||||
*
|
||||
* @param drawable the drawable being requested.
|
||||
*
|
||||
* This function returns the backing pixmap for a drawable, whether it is a
|
||||
* redirected window, unredirected window, or already a pixmap.
|
||||
*/
|
||||
static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
|
||||
{
|
||||
if (drawable->type == DRAWABLE_PIXMAP)
|
||||
return (PixmapPtr)drawable;
|
||||
else
|
||||
return drawable->pScreen->GetWindowPixmap((WindowPtr)drawable);
|
||||
}
|
||||
|
||||
static inline void
|
||||
radeon_buffer_ref(struct radeon_buffer *buffer)
|
||||
{
|
||||
buffer->ref_count++;
|
||||
}
|
||||
|
||||
static inline void
|
||||
radeon_buffer_unref(struct radeon_buffer **buffer)
|
||||
{
|
||||
struct radeon_buffer *buf = *buffer;
|
||||
|
||||
if (!buf)
|
||||
return;
|
||||
|
||||
if (buf->ref_count > 1) {
|
||||
buf->ref_count--;
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
if (buf->flags & RADEON_BO_FLAGS_GBM) {
|
||||
gbm_bo_destroy(buf->bo.gbm);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
radeon_bo_unmap(buf->bo.radeon);
|
||||
radeon_bo_unref(buf->bo.radeon);
|
||||
}
|
||||
|
||||
free(buf);
|
||||
*buffer = NULL;
|
||||
}
|
||||
|
||||
#endif /* RADEON_BO_HELPER_H */
|
||||
703
src/radeon_chipinfo_gen.h
Normal file
703
src/radeon_chipinfo_gen.h
Normal file
|
|
@ -0,0 +1,703 @@
|
|||
/* This file is autogenerated please do not edit */
|
||||
static RADEONCardInfo RADEONCards[] = {
|
||||
{ 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x3155, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 },
|
||||
{ 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
|
||||
{ 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
|
||||
{ 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
|
||||
{ 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 },
|
||||
{ 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
|
||||
{ 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
|
||||
{ 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
|
||||
{ 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
|
||||
{ 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4A54, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4B48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
|
||||
{ 0x4C6E, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
|
||||
{ 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
|
||||
{ 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
|
||||
{ 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
|
||||
{ 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
|
||||
{ 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
|
||||
{ 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
|
||||
{ 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
|
||||
{ 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
|
||||
{ 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
|
||||
{ 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
|
||||
{ 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
|
||||
{ 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
|
||||
{ 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
|
||||
{ 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
|
||||
{ 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
|
||||
{ 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
|
||||
{ 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
|
||||
{ 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
|
||||
{ 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
|
||||
{ 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
|
||||
{ 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
|
||||
{ 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
|
||||
{ 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
|
||||
{ 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
|
||||
{ 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
|
||||
{ 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
|
||||
{ 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
|
||||
{ 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
|
||||
{ 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
|
||||
{ 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
|
||||
{ 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
|
||||
{ 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
|
||||
{ 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
|
||||
{ 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
|
||||
{ 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
|
||||
{ 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
|
||||
{ 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
|
||||
{ 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
|
||||
{ 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
|
||||
{ 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
|
||||
{ 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
|
||||
{ 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
|
||||
{ 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
|
||||
{ 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
|
||||
{ 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
|
||||
{ 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
|
||||
{ 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
|
||||
{ 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
|
||||
{ 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
|
||||
{ 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
|
||||
{ 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
|
||||
{ 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
|
||||
{ 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
|
||||
{ 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 },
|
||||
{ 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
|
||||
{ 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
|
||||
{ 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
|
||||
{ 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
|
||||
{ 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
|
||||
{ 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
|
||||
{ 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
|
||||
{ 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
|
||||
{ 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
|
||||
{ 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
|
||||
{ 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
|
||||
{ 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
|
||||
{ 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
|
||||
{ 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
|
||||
{ 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
|
||||
{ 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
|
||||
{ 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
|
||||
{ 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9443, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9444, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9446, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x944A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x944B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x944C, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x944E, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9450, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9452, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x945E, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x9460, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x9462, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
|
||||
{ 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x947B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
|
||||
{ 0x9480, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
|
||||
{ 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x9488, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
|
||||
{ 0x9489, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
|
||||
{ 0x948A, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
|
||||
{ 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x9491, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x9495, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x949F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
|
||||
{ 0x94A0, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 },
|
||||
{ 0x94A1, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 },
|
||||
{ 0x94A3, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 },
|
||||
{ 0x94B1, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 },
|
||||
{ 0x94B3, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 },
|
||||
{ 0x94B4, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 },
|
||||
{ 0x94B5, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 },
|
||||
{ 0x94B9, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 },
|
||||
{ 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
|
||||
{ 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
|
||||
{ 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
|
||||
{ 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x94CD, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
|
||||
{ 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9504, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
|
||||
{ 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9506, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
|
||||
{ 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9508, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
|
||||
{ 0x9509, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
|
||||
{ 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9517, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9519, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
|
||||
{ 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
|
||||
{ 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
|
||||
{ 0x9542, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
|
||||
{ 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
|
||||
{ 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
|
||||
{ 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
|
||||
{ 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
|
||||
{ 0x9555, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
|
||||
{ 0x9557, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
|
||||
{ 0x955F, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
|
||||
{ 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
|
||||
{ 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
|
||||
{ 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
|
||||
{ 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
|
||||
{ 0x958F, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
|
||||
{ 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
|
||||
{ 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
|
||||
{ 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95C6, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95C9, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95CC, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
|
||||
{ 0x9590, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
|
||||
{ 0x9596, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
|
||||
{ 0x9597, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
|
||||
{ 0x9598, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
|
||||
{ 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
|
||||
{ 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
|
||||
{ 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
|
||||
{ 0x9595, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
|
||||
{ 0x959B, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
|
||||
{ 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9615, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9616, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
|
||||
{ 0x9640, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x9641, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9642, CHIP_FAMILY_SUMO2, 0, 1, 0, 0, 1 },
|
||||
{ 0x9643, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
|
||||
{ 0x9644, CHIP_FAMILY_SUMO2, 0, 1, 0, 0, 1 },
|
||||
{ 0x9645, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
|
||||
{ 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9649, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
|
||||
{ 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x964E, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x964F, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9710, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
|
||||
{ 0x9711, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
|
||||
{ 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
|
||||
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
|
||||
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
|
||||
{ 0x9715, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
|
||||
{ 0x9802, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9803, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9804, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9805, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9806, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9807, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9808, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x9809, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x980A, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
|
||||
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x688A, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x688C, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x688D, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6898, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6899, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x689B, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x689E, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
|
||||
{ 0x689C, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
|
||||
{ 0x689D, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
|
||||
{ 0x68A0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
|
||||
{ 0x68A1, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
|
||||
{ 0x68A8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68A9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68B0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
|
||||
{ 0x68B8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68B9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68BA, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68BE, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68BF, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
|
||||
{ 0x68C0, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
|
||||
{ 0x68C1, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
|
||||
{ 0x68C7, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
|
||||
{ 0x68C8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68C9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68D8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68D9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68DA, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68DE, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
|
||||
{ 0x68E0, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
|
||||
{ 0x68E1, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
|
||||
{ 0x68E4, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
|
||||
{ 0x68E5, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
|
||||
{ 0x68E8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68E9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68F1, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68F2, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68FA, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
|
||||
{ 0x6700, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6701, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6702, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6703, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6704, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6705, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6706, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6707, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6708, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6709, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6718, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6719, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x671C, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x671D, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x671F, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6720, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6721, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6722, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6723, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6724, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6725, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6726, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6727, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6728, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6729, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6738, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6739, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x673E, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6740, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6741, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6742, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6743, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6744, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6745, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6746, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6747, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6748, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6749, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x674A, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6750, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6751, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6758, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6759, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x675B, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x675D, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x675F, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6840, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6841, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6842, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6843, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6849, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6850, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6858, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6859, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6760, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6761, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6762, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6763, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6764, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6765, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
|
||||
{ 0x6766, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6767, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6768, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6770, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6771, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6772, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6778, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x677B, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
|
||||
{ 0x9900, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9901, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9903, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9904, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9905, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9906, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9907, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9908, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9909, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x990A, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x990B, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x990C, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x990D, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x990E, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x990F, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9910, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9913, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9917, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9918, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9919, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9990, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9991, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9992, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9993, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9994, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9995, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9996, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9997, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x9998, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x9999, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x999A, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x999B, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x999C, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x999D, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x99A0, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x99A2, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 },
|
||||
{ 0x99A4, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 },
|
||||
{ 0x6780, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6784, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6788, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x678A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6790, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6791, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6792, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6798, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6799, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x679A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x679B, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x679E, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x679F, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 },
|
||||
{ 0x6800, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6801, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6802, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6806, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6808, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6809, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6810, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6811, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6816, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6817, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6818, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6819, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x684C, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 },
|
||||
{ 0x6820, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6821, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6822, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6823, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6824, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6825, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6826, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6827, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6828, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6829, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x682A, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x682B, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x682C, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x682D, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x682F, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6830, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6831, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6835, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6837, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6838, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6839, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x683B, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x683D, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x683F, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6600, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6601, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6602, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6603, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6604, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6605, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6606, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6607, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6608, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 },
|
||||
{ 0x6610, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 },
|
||||
{ 0x6611, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 },
|
||||
{ 0x6613, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 },
|
||||
{ 0x6617, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6620, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6621, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6623, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 },
|
||||
{ 0x6631, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 },
|
||||
{ 0x6660, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6663, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6664, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6665, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6667, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x666F, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 },
|
||||
{ 0x6640, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6641, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6646, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6647, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 },
|
||||
{ 0x6649, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6650, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6651, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x6658, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x665C, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x665D, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x665F, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 },
|
||||
{ 0x9830, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x9831, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x9832, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x9833, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x9834, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x9835, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x9836, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x9837, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x9838, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x9839, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x983A, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983B, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 },
|
||||
{ 0x983C, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983D, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983E, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983F, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x9850, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9851, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9852, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9853, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9854, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9855, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9856, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9857, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9858, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x9859, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985A, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985B, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985C, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985D, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985E, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x985F, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 },
|
||||
{ 0x1304, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x1305, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1306, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x1307, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1309, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130A, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130B, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130C, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130D, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130E, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130F, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1310, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1311, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1312, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1313, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1315, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1316, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1317, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x1318, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x131B, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x131C, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x131D, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x67A0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A2, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67AA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67BA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67BE, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
1011
src/radeon_chipset_gen.h
Normal file
1011
src/radeon_chipset_gen.h
Normal file
File diff suppressed because it is too large
Load diff
1485
src/radeon_dri2.c
Normal file
1485
src/radeon_dri2.c
Normal file
File diff suppressed because it is too large
Load diff
52
src/radeon_dri2.h
Normal file
52
src/radeon_dri2.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright 2008 Jerome Glisse
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation on the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
|
||||
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef RADEON_DRI2_H
|
||||
#define RADEON_DRI2_H
|
||||
|
||||
#include <xorg-server.h>
|
||||
|
||||
struct radeon_dri2 {
|
||||
drmVersionPtr pKernelDRMVersion;
|
||||
Bool available;
|
||||
Bool enabled;
|
||||
char *device_name;
|
||||
};
|
||||
|
||||
#ifdef DRI2
|
||||
|
||||
#include "dri2.h"
|
||||
Bool radeon_dri2_screen_init(ScreenPtr pScreen);
|
||||
void radeon_dri2_close_screen(ScreenPtr pScreen);
|
||||
|
||||
#else
|
||||
|
||||
static inline Bool radeon_dri2_screen_init(ScreenPtr pScreen) { return FALSE; }
|
||||
static inline void radeon_dri2_close_screen(ScreenPtr pScreen) {}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* RADEON_DRI2_H */
|
||||
238
src/radeon_dri3.c
Normal file
238
src/radeon_dri3.c
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* Copyright © 2013-2014 Intel Corporation
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of the copyright holders not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. The copyright holders make no representations
|
||||
* about the suitability of this software for any purpose. It is provided "as
|
||||
* is" without express or implied warranty.
|
||||
*
|
||||
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
|
||||
* OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_bo_gem.h"
|
||||
#include "radeon_glamor.h"
|
||||
#include "dri3.h"
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <gbm.h>
|
||||
#include <errno.h>
|
||||
#include <libgen.h>
|
||||
|
||||
static int open_master_node(ScreenPtr screen, int *out)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
drm_magic_t magic;
|
||||
int fd;
|
||||
|
||||
fd = open(info->dri2.device_name, O_RDWR | O_CLOEXEC);
|
||||
if (fd < 0)
|
||||
return BadAlloc;
|
||||
|
||||
/* Before FD passing in the X protocol with DRI3 (and increased
|
||||
* security of rendering with per-process address spaces on the
|
||||
* GPU), the kernel had to come up with a way to have the server
|
||||
* decide which clients got to access the GPU, which was done by
|
||||
* each client getting a unique (magic) number from the kernel,
|
||||
* passing it to the server, and the server then telling the
|
||||
* kernel which clients were authenticated for using the device.
|
||||
*
|
||||
* Now that we have FD passing, the server can just set up the
|
||||
* authentication on its own and hand the prepared FD off to the
|
||||
* client.
|
||||
*/
|
||||
if (drmGetMagic(fd, &magic) < 0) {
|
||||
if (errno == EACCES) {
|
||||
/* Assume that we're on a render node, and the fd is
|
||||
* already as authenticated as it should be.
|
||||
*/
|
||||
*out = fd;
|
||||
return Success;
|
||||
} else {
|
||||
close(fd);
|
||||
return BadMatch;
|
||||
}
|
||||
}
|
||||
|
||||
if (drmAuthMagic(pRADEONEnt->fd, magic) < 0) {
|
||||
close(fd);
|
||||
return BadMatch;
|
||||
}
|
||||
|
||||
*out = fd;
|
||||
return Success;
|
||||
}
|
||||
|
||||
static int open_render_node(ScreenPtr screen, int *out)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
int fd;
|
||||
|
||||
fd = open(pRADEONEnt->render_node, O_RDWR | O_CLOEXEC);
|
||||
if (fd < 0)
|
||||
return BadAlloc;
|
||||
|
||||
*out = fd;
|
||||
return Success;
|
||||
}
|
||||
|
||||
static int
|
||||
radeon_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
int ret = BadAlloc;
|
||||
|
||||
if (pRADEONEnt->render_node)
|
||||
ret = open_render_node(screen, out);
|
||||
|
||||
if (ret != Success)
|
||||
ret = open_master_node(screen, out);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static PixmapPtr radeon_dri3_pixmap_from_fd(ScreenPtr screen,
|
||||
int fd,
|
||||
CARD16 width,
|
||||
CARD16 height,
|
||||
CARD16 stride,
|
||||
CARD8 depth,
|
||||
CARD8 bpp)
|
||||
{
|
||||
PixmapPtr pixmap;
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
/* Avoid generating a GEM flink name if possible */
|
||||
if (RADEONPTR(xf86ScreenToScrn(screen))->use_glamor) {
|
||||
pixmap = glamor_pixmap_from_fd(screen, fd, width, height,
|
||||
stride, depth, bpp);
|
||||
if (pixmap) {
|
||||
struct radeon_pixmap *priv =
|
||||
calloc(1, sizeof(struct radeon_pixmap));
|
||||
|
||||
if (priv) {
|
||||
radeon_set_pixmap_private(pixmap, priv);
|
||||
pixmap->usage_hint |= RADEON_CREATE_PIXMAP_DRI2;
|
||||
return pixmap;
|
||||
}
|
||||
|
||||
screen->DestroyPixmap(pixmap);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (depth < 8)
|
||||
return NULL;
|
||||
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pixmap = screen->CreatePixmap(screen, 0, 0, depth, RADEON_CREATE_PIXMAP_DRI2);
|
||||
if (!pixmap)
|
||||
return NULL;
|
||||
|
||||
if (!screen->ModifyPixmapHeader(pixmap, width, height, 0, bpp, stride,
|
||||
NULL))
|
||||
goto free_pixmap;
|
||||
|
||||
if (screen->SetSharedPixmapBacking(pixmap, (void*)(intptr_t)fd))
|
||||
return pixmap;
|
||||
|
||||
free_pixmap:
|
||||
fbDestroyPixmap(pixmap);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int radeon_dri3_fd_from_pixmap(ScreenPtr screen,
|
||||
PixmapPtr pixmap,
|
||||
CARD16 *stride,
|
||||
CARD32 *size)
|
||||
{
|
||||
struct radeon_buffer *bo;
|
||||
int fd;
|
||||
#ifdef USE_GLAMOR
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
if (info->use_glamor) {
|
||||
int ret = glamor_fd_from_pixmap(screen, pixmap, stride, size);
|
||||
|
||||
/* Any pending drawing operations need to be flushed to the
|
||||
* kernel driver before the client starts using the pixmap
|
||||
* storage for direct rendering.
|
||||
*/
|
||||
if (ret >= 0)
|
||||
radeon_cs_flush_indirect(scrn);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
bo = radeon_get_pixmap_bo(pixmap);
|
||||
if (!bo) {
|
||||
exaMoveInPixmap(pixmap);
|
||||
bo = radeon_get_pixmap_bo(pixmap);
|
||||
if (!bo)
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (pixmap->devKind > UINT16_MAX)
|
||||
return -1;
|
||||
|
||||
if (radeon_gem_prime_share_bo(bo->bo.radeon, &fd) < 0)
|
||||
return -1;
|
||||
|
||||
*stride = pixmap->devKind;
|
||||
*size = bo->bo.radeon->size;
|
||||
return fd;
|
||||
}
|
||||
|
||||
static dri3_screen_info_rec radeon_dri3_screen_info = {
|
||||
.version = 0,
|
||||
.open = radeon_dri3_open,
|
||||
.pixmap_from_fd = radeon_dri3_pixmap_from_fd,
|
||||
.fd_from_pixmap = radeon_dri3_fd_from_pixmap
|
||||
};
|
||||
|
||||
Bool
|
||||
radeon_dri3_screen_init(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
|
||||
pRADEONEnt->render_node = drmGetRenderDeviceNameFromFd(pRADEONEnt->fd);
|
||||
|
||||
if (!dri3_screen_init(screen, &radeon_dri3_screen_info)) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"dri3_screen_init failed\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
364
src/radeon_drm_queue.c
Normal file
364
src/radeon_drm_queue.c
Normal file
|
|
@ -0,0 +1,364 @@
|
|||
/*
|
||||
* Copyright © 2007 Red Hat, Inc.
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Dave Airlie <airlied@redhat.com>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <xorg-server.h>
|
||||
#include <X11/Xdefs.h>
|
||||
#include <list.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_drm_queue.h"
|
||||
|
||||
|
||||
struct radeon_drm_queue_entry {
|
||||
struct xorg_list list;
|
||||
uint64_t usec;
|
||||
uint64_t id;
|
||||
uintptr_t seq;
|
||||
void *data;
|
||||
ClientPtr client;
|
||||
xf86CrtcPtr crtc;
|
||||
radeon_drm_handler_proc handler;
|
||||
radeon_drm_abort_proc abort;
|
||||
Bool is_flip;
|
||||
unsigned int frame;
|
||||
};
|
||||
|
||||
static int radeon_drm_queue_refcnt;
|
||||
static struct xorg_list radeon_drm_queue;
|
||||
static struct xorg_list radeon_drm_flip_signalled;
|
||||
static struct xorg_list radeon_drm_vblank_signalled;
|
||||
static struct xorg_list radeon_drm_vblank_deferred;
|
||||
static uintptr_t radeon_drm_queue_seq;
|
||||
|
||||
|
||||
/*
|
||||
* Process a DRM event
|
||||
*/
|
||||
static void
|
||||
radeon_drm_queue_handle_one(struct radeon_drm_queue_entry *e)
|
||||
{
|
||||
xorg_list_del(&e->list);
|
||||
if (e->handler) {
|
||||
e->handler(e->crtc, e->frame, e->usec, e->data);
|
||||
} else
|
||||
e->abort(e->crtc, e->data);
|
||||
free(e);
|
||||
}
|
||||
|
||||
/*
|
||||
* Abort one queued DRM entry, removing it
|
||||
* from the list, calling the abort function and
|
||||
* freeing the memory
|
||||
*/
|
||||
static void
|
||||
radeon_drm_abort_one(struct radeon_drm_queue_entry *e)
|
||||
{
|
||||
xorg_list_del(&e->list);
|
||||
e->abort(e->crtc, e->data);
|
||||
free(e);
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_drm_queue_handler(int fd, unsigned int frame, unsigned int sec,
|
||||
unsigned int usec, void *user_ptr)
|
||||
{
|
||||
uintptr_t seq = (uintptr_t)user_ptr;
|
||||
struct radeon_drm_queue_entry *e, *tmp;
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
|
||||
if (e->seq == seq) {
|
||||
if (!e->handler) {
|
||||
radeon_drm_abort_one(e);
|
||||
break;
|
||||
}
|
||||
|
||||
xorg_list_del(&e->list);
|
||||
e->usec = (uint64_t)sec * 1000000 + usec;
|
||||
e->frame = frame;
|
||||
xorg_list_append(&e->list, e->is_flip ?
|
||||
&radeon_drm_flip_signalled :
|
||||
&radeon_drm_vblank_signalled);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle signalled vblank events. If we're waiting for a flip event,
|
||||
* put events for that CRTC in the vblank_deferred list.
|
||||
*/
|
||||
static void
|
||||
radeon_drm_handle_vblank_signalled(void)
|
||||
{
|
||||
drmmode_crtc_private_ptr drmmode_crtc;
|
||||
struct radeon_drm_queue_entry *e;
|
||||
|
||||
while (!xorg_list_is_empty(&radeon_drm_vblank_signalled)) {
|
||||
e = xorg_list_first_entry(&radeon_drm_vblank_signalled,
|
||||
struct radeon_drm_queue_entry, list);
|
||||
drmmode_crtc = e->crtc->driver_private;
|
||||
|
||||
if (drmmode_crtc->wait_flip_nesting_level == 0) {
|
||||
radeon_drm_queue_handle_one(e);
|
||||
continue;
|
||||
}
|
||||
|
||||
xorg_list_del(&e->list);
|
||||
xorg_list_append(&e->list, &radeon_drm_vblank_deferred);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle deferred DRM vblank events
|
||||
*
|
||||
* This function must be called after radeon_drm_wait_pending_flip, once
|
||||
* it's safe to attempt queueing a flip again
|
||||
*/
|
||||
void
|
||||
radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc)
|
||||
{
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
struct radeon_drm_queue_entry *e, *tmp;
|
||||
|
||||
if (drmmode_crtc->wait_flip_nesting_level == 0 ||
|
||||
--drmmode_crtc->wait_flip_nesting_level > 0)
|
||||
return;
|
||||
|
||||
/* Put previously deferred vblank events for this CRTC back in the
|
||||
* signalled queue
|
||||
*/
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_deferred, list) {
|
||||
if (e->crtc != crtc)
|
||||
continue;
|
||||
|
||||
xorg_list_del(&e->list);
|
||||
xorg_list_append(&e->list, &radeon_drm_vblank_signalled);
|
||||
}
|
||||
|
||||
radeon_drm_handle_vblank_signalled();
|
||||
}
|
||||
|
||||
/*
|
||||
* Enqueue a potential drm response; when the associated response
|
||||
* appears, we've got data to pass to the handler from here
|
||||
*/
|
||||
uintptr_t
|
||||
radeon_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
|
||||
uint64_t id, void *data,
|
||||
radeon_drm_handler_proc handler,
|
||||
radeon_drm_abort_proc abort,
|
||||
Bool is_flip)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e;
|
||||
|
||||
e = calloc(1, sizeof(struct radeon_drm_queue_entry));
|
||||
if (!e)
|
||||
return RADEON_DRM_QUEUE_ERROR;
|
||||
|
||||
if (_X_UNLIKELY(radeon_drm_queue_seq == RADEON_DRM_QUEUE_ERROR))
|
||||
radeon_drm_queue_seq++;
|
||||
|
||||
e->seq = radeon_drm_queue_seq++;
|
||||
e->client = client;
|
||||
e->crtc = crtc;
|
||||
e->id = id;
|
||||
e->data = data;
|
||||
e->handler = handler;
|
||||
e->abort = abort;
|
||||
e->is_flip = is_flip;
|
||||
|
||||
xorg_list_append(&e->list, &radeon_drm_queue);
|
||||
|
||||
return e->seq;
|
||||
}
|
||||
|
||||
/*
|
||||
* Abort drm queue entries for a client
|
||||
*
|
||||
* NOTE: This keeps the entries in the list until the DRM event arrives,
|
||||
* but then it calls the abort functions instead of the handler
|
||||
* functions.
|
||||
*/
|
||||
void
|
||||
radeon_drm_abort_client(ClientPtr client)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e;
|
||||
|
||||
xorg_list_for_each_entry(e, &radeon_drm_queue, list) {
|
||||
if (e->client == client)
|
||||
e->handler = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Abort specific drm queue entry
|
||||
*/
|
||||
void
|
||||
radeon_drm_abort_entry(uintptr_t seq)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e, *tmp;
|
||||
|
||||
if (seq == RADEON_DRM_QUEUE_ERROR)
|
||||
return;
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) {
|
||||
if (e->seq == seq) {
|
||||
radeon_drm_abort_one(e);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_deferred, list) {
|
||||
if (e->seq == seq) {
|
||||
radeon_drm_abort_one(e);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
|
||||
if (e->seq == seq) {
|
||||
radeon_drm_abort_one(e);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Abort specific drm queue entry by ID
|
||||
*/
|
||||
void
|
||||
radeon_drm_abort_id(uint64_t id)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e, *tmp;
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
|
||||
if (e->id == id) {
|
||||
radeon_drm_abort_one(e);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* drmHandleEvent wrapper
|
||||
*/
|
||||
int
|
||||
radeon_drm_handle_event(int fd, drmEventContext *event_context)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e;
|
||||
int r;
|
||||
|
||||
/* Retry drmHandleEvent if it was interrupted by a signal in read() */
|
||||
do {
|
||||
r = drmHandleEvent(fd, event_context);
|
||||
} while (r < 0 && (errno == EINTR || errno == EAGAIN));
|
||||
|
||||
if (r < 0) {
|
||||
static Bool printed;
|
||||
|
||||
if (!printed) {
|
||||
ErrorF("%s: drmHandleEvent returned %d, errno=%d (%s)\n",
|
||||
__func__, r, errno, strerror(errno));
|
||||
printed = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
while (!xorg_list_is_empty(&radeon_drm_flip_signalled)) {
|
||||
e = xorg_list_first_entry(&radeon_drm_flip_signalled,
|
||||
struct radeon_drm_queue_entry, list);
|
||||
radeon_drm_queue_handle_one(e);
|
||||
}
|
||||
|
||||
radeon_drm_handle_vblank_signalled();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for pending page flip on given CRTC to complete
|
||||
*/
|
||||
void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc)
|
||||
{
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
|
||||
struct radeon_drm_queue_entry *e;
|
||||
|
||||
drmmode_crtc->wait_flip_nesting_level++;
|
||||
|
||||
while (drmmode_crtc->flip_pending &&
|
||||
!xorg_list_is_empty(&radeon_drm_flip_signalled)) {
|
||||
e = xorg_list_first_entry(&radeon_drm_flip_signalled,
|
||||
struct radeon_drm_queue_entry, list);
|
||||
radeon_drm_queue_handle_one(e);
|
||||
}
|
||||
|
||||
while (drmmode_crtc->flip_pending
|
||||
&& radeon_drm_handle_event(pRADEONEnt->fd,
|
||||
&drmmode_crtc->drmmode->event_context) >= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the DRM event queue
|
||||
*/
|
||||
void
|
||||
radeon_drm_queue_init(ScrnInfoPtr scrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
drmmode_ptr drmmode = &info->drmmode;
|
||||
|
||||
drmmode->event_context.version = 2;
|
||||
drmmode->event_context.vblank_handler = radeon_drm_queue_handler;
|
||||
drmmode->event_context.page_flip_handler = radeon_drm_queue_handler;
|
||||
|
||||
if (radeon_drm_queue_refcnt++)
|
||||
return;
|
||||
|
||||
xorg_list_init(&radeon_drm_queue);
|
||||
xorg_list_init(&radeon_drm_flip_signalled);
|
||||
xorg_list_init(&radeon_drm_vblank_signalled);
|
||||
xorg_list_init(&radeon_drm_vblank_deferred);
|
||||
}
|
||||
|
||||
/*
|
||||
* Deinitialize the DRM event queue
|
||||
*/
|
||||
void
|
||||
radeon_drm_queue_close(ScrnInfoPtr scrn)
|
||||
{
|
||||
struct radeon_drm_queue_entry *e, *tmp;
|
||||
|
||||
xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
|
||||
if (e->crtc->scrn == scrn)
|
||||
radeon_drm_abort_one(e);
|
||||
}
|
||||
|
||||
radeon_drm_queue_refcnt--;
|
||||
}
|
||||
57
src/radeon_drm_queue.h
Normal file
57
src/radeon_drm_queue.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright © 2007 Red Hat, Inc.
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Dave Airlie <airlied@redhat.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RADEON_DRM_QUEUE_H_
|
||||
#define _RADEON_DRM_QUEUE_H_
|
||||
|
||||
#define RADEON_DRM_QUEUE_ERROR 0
|
||||
|
||||
#define RADEON_DRM_QUEUE_CLIENT_DEFAULT serverClient
|
||||
#define RADEON_DRM_QUEUE_ID_DEFAULT ~0ULL
|
||||
|
||||
struct radeon_drm_queue_entry;
|
||||
|
||||
typedef void (*radeon_drm_handler_proc)(xf86CrtcPtr crtc, uint32_t seq,
|
||||
uint64_t usec, void *data);
|
||||
typedef void (*radeon_drm_abort_proc)(xf86CrtcPtr crtc, void *data);
|
||||
|
||||
void radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc);
|
||||
uintptr_t radeon_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
|
||||
uint64_t id, void *data,
|
||||
radeon_drm_handler_proc handler,
|
||||
radeon_drm_abort_proc abort,
|
||||
Bool is_flip);
|
||||
void radeon_drm_abort_client(ClientPtr client);
|
||||
void radeon_drm_abort_entry(uintptr_t seq);
|
||||
void radeon_drm_abort_id(uint64_t id);
|
||||
int radeon_drm_handle_event(int fd, drmEventContext *event_context);
|
||||
void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc);
|
||||
void radeon_drm_queue_init(ScrnInfoPtr scrn);
|
||||
void radeon_drm_queue_close(ScrnInfoPtr scrn);
|
||||
|
||||
#endif /* _RADEON_DRM_QUEUE_H_ */
|
||||
335
src/radeon_exa.c
Normal file
335
src/radeon_exa.c
Normal file
|
|
@ -0,0 +1,335 @@
|
|||
/*
|
||||
* Copyright 2005 Eric Anholt
|
||||
* Copyright 2005 Benjamin Herrenschmidt
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Zack Rusin <zrusin@trolltech.com>
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "r600_reg.h"
|
||||
#include "radeon_bo_helper.h"
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_version.h"
|
||||
#include "radeon_exa_shared.h"
|
||||
#include "xf86.h"
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
#define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86ScreenToScrn(pScr); \
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn)
|
||||
|
||||
static struct {
|
||||
int rop;
|
||||
int pattern;
|
||||
} RADEON_ROP[] = {
|
||||
{ RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */
|
||||
{ RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */
|
||||
{ RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */
|
||||
{ RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */
|
||||
{ RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */
|
||||
{ RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */
|
||||
{ RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */
|
||||
{ RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */
|
||||
{ RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */
|
||||
{ RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */
|
||||
{ RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */
|
||||
{ RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */
|
||||
{ RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */
|
||||
{ RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */
|
||||
{ RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */
|
||||
{ RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */
|
||||
};
|
||||
|
||||
static __inline__ uint32_t F_TO_DW(float val)
|
||||
{
|
||||
union {
|
||||
float f;
|
||||
uint32_t l;
|
||||
} tmp;
|
||||
tmp.f = val;
|
||||
return tmp.l;
|
||||
}
|
||||
|
||||
|
||||
/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
|
||||
* require src and dest datatypes to be equal.
|
||||
*/
|
||||
Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type)
|
||||
{
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
*type = ATI_DATATYPE_CI8;
|
||||
return TRUE;
|
||||
case 16:
|
||||
*type = ATI_DATATYPE_RGB565;
|
||||
return TRUE;
|
||||
case 24:
|
||||
*type = ATI_DATATYPE_CI8;
|
||||
return TRUE;
|
||||
case 32:
|
||||
*type = ATI_DATATYPE_ARGB8888;
|
||||
return TRUE;
|
||||
default:
|
||||
RADEON_FALLBACK(("Unsupported bpp: %d\n", bpp));
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
static Bool RADEONPixmapIsColortiled(PixmapPtr pPix)
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset,
|
||||
unsigned int offset, unsigned int pitch)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
|
||||
|
||||
if (pitch > 16320 || pitch % info->accel_state->exa->pixmapPitchAlign != 0)
|
||||
RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch));
|
||||
|
||||
if (offset % info->accel_state->exa->pixmapOffsetAlign != 0)
|
||||
RADEON_FALLBACK(("Bad offset 0x%08x\n", offset));
|
||||
|
||||
pitch = pitch >> 6;
|
||||
*pitch_offset = (pitch << 22) | (offset >> 10);
|
||||
|
||||
/* If it's the front buffer, we've got to note that it's tiled? */
|
||||
if (RADEONPixmapIsColortiled(pPix))
|
||||
*pitch_offset |= RADEON_DST_TILE_MACRO;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset)
|
||||
{
|
||||
uint32_t pitch;
|
||||
int bpp;
|
||||
|
||||
bpp = pPix->drawable.bitsPerPixel;
|
||||
if (bpp == 24)
|
||||
bpp = 8;
|
||||
|
||||
pitch = exaGetPixmapPitch(pPix);
|
||||
|
||||
return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, 0, pitch);
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns whether the provided transform is affine.
|
||||
*
|
||||
* transform may be null.
|
||||
*/
|
||||
Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t)
|
||||
{
|
||||
if (!t)
|
||||
return TRUE;
|
||||
/* the shaders don't handle scaling either */
|
||||
return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1);
|
||||
}
|
||||
|
||||
Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
|
||||
{
|
||||
ScreenPtr pScreen = pPix->drawable.pScreen;
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
uint32_t possible_domains = ~0U;
|
||||
uint32_t current_domain = 0;
|
||||
Bool can_fail = !(pPix->drawable.bitsPerPixel < 8) &&
|
||||
pPix != pScreen->GetScreenPixmap(pScreen);
|
||||
Bool flush = FALSE;
|
||||
int ret;
|
||||
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
/* May need to handle byte swapping in DownloadFrom/UploadToScreen */
|
||||
if (pPix->drawable.bitsPerPixel > 8)
|
||||
return FALSE;
|
||||
#endif
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
if (!driver_priv)
|
||||
return FALSE;
|
||||
|
||||
/* untile in DFS/UTS */
|
||||
if (driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
|
||||
return FALSE;
|
||||
|
||||
/* if we have more refs than just the BO then flush */
|
||||
if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
|
||||
flush = TRUE;
|
||||
|
||||
if (can_fail) {
|
||||
possible_domains = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
|
||||
if (possible_domains == RADEON_GEM_DOMAIN_VRAM)
|
||||
return FALSE; /* use DownloadFromScreen */
|
||||
}
|
||||
}
|
||||
|
||||
/* if the BO might end up in VRAM, prefer DownloadFromScreen */
|
||||
if (can_fail && (possible_domains & RADEON_GEM_DOMAIN_VRAM)) {
|
||||
radeon_bo_is_busy(driver_priv->bo->bo.radeon, ¤t_domain);
|
||||
|
||||
if (current_domain & possible_domains) {
|
||||
if (current_domain == RADEON_GEM_DOMAIN_VRAM)
|
||||
return FALSE;
|
||||
} else if (possible_domains & RADEON_GEM_DOMAIN_VRAM)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (flush)
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
|
||||
/* flush IB */
|
||||
ret = radeon_bo_map(driver_priv->bo->bo.radeon, 1);
|
||||
if (ret) {
|
||||
FatalError("failed to map pixmap %d\n", ret);
|
||||
return FALSE;
|
||||
}
|
||||
driver_priv->bo_mapped = TRUE;
|
||||
|
||||
pPix->devPrivate.ptr = driver_priv->bo->bo.radeon->ptr;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void RADEONFinishAccess_CS(PixmapPtr pPix, int index)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
if (!driver_priv || !driver_priv->bo_mapped)
|
||||
return;
|
||||
|
||||
radeon_bo_unmap(driver_priv->bo->bo.radeon);
|
||||
driver_priv->bo_mapped = FALSE;
|
||||
pPix->devPrivate.ptr = NULL;
|
||||
}
|
||||
|
||||
|
||||
void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
|
||||
int depth, int usage_hint, int bitsPerPixel,
|
||||
int *new_pitch)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_exa_pixmap_priv *new_priv;
|
||||
|
||||
if (width != 0 && height != 0 && !info->exa_force_create &&
|
||||
info->exa_pixmaps == FALSE)
|
||||
return NULL;
|
||||
|
||||
new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
|
||||
if (!new_priv) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (width == 0 || height == 0) {
|
||||
return new_priv;
|
||||
}
|
||||
|
||||
new_priv->bo = radeon_alloc_pixmap_bo(pScrn, width, height, depth,
|
||||
usage_hint, bitsPerPixel, new_pitch,
|
||||
&new_priv->surface,
|
||||
&new_priv->tiling_flags);
|
||||
if (!new_priv->bo) {
|
||||
free(new_priv);
|
||||
ErrorF("Failed to alloc memory\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return new_priv;
|
||||
}
|
||||
|
||||
void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv)
|
||||
{
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(xf86ScreenToScrn(pScreen));
|
||||
struct radeon_exa_pixmap_priv *driver_priv = driverPriv;
|
||||
|
||||
if (!driverPriv)
|
||||
return;
|
||||
|
||||
radeon_buffer_unref(&driver_priv->bo);
|
||||
drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL);
|
||||
free(driverPriv);
|
||||
}
|
||||
|
||||
Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr seconndary, void **fd_handle)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix);
|
||||
|
||||
if (!radeon_share_pixmap_backing(driver_priv->bo->bo.radeon, fd_handle))
|
||||
return FALSE;
|
||||
|
||||
driver_priv->shared = TRUE;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *fd_handle)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix);
|
||||
int ihandle = (int)(long)fd_handle;
|
||||
|
||||
if (!radeon_set_shared_pixmap_backing(ppix, fd_handle, &driver_priv->surface))
|
||||
return FALSE;
|
||||
|
||||
driver_priv->shared = ihandle != -1;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
return driver_priv->tiling_flags;
|
||||
}
|
||||
|
||||
Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
|
||||
if (!driver_priv)
|
||||
return FALSE;
|
||||
if (driver_priv->bo)
|
||||
return TRUE;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
#define ENTER_DRAW(x) TRACE
|
||||
#define LEAVE_DRAW(x) TRACE
|
||||
/***********************************************************************/
|
||||
|
||||
#ifdef RENDER
|
||||
#include "radeon_exa_render.c"
|
||||
#endif
|
||||
#include "radeon_exa_funcs.c"
|
||||
|
||||
|
||||
|
||||
673
src/radeon_exa_funcs.c
Normal file
673
src/radeon_exa_funcs.c
Normal file
|
|
@ -0,0 +1,673 @@
|
|||
/*
|
||||
* Copyright 2005 Eric Anholt
|
||||
* Copyright 2005 Benjamin Herrenschmidt
|
||||
* Copyright 2006 Tungsten Graphics, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Zack Rusin <zrusin@trolltech.com>
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
* Michel Dänzer <michel@daenzer.net>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
#include "exa.h"
|
||||
|
||||
static int
|
||||
RADEONMarkSync(ScreenPtr pScreen)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pScreen);
|
||||
|
||||
TRACE;
|
||||
|
||||
return ++info->accel_state->exaSyncMarker;
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONSync(ScreenPtr pScreen, int marker)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void Emit2DState(ScrnInfoPtr pScrn, int op)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int has_src;
|
||||
|
||||
/* don't emit if no operation in progress */
|
||||
if (info->state_2d.op == 0 && op == 0)
|
||||
return;
|
||||
|
||||
has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo;
|
||||
|
||||
if (has_src) {
|
||||
BEGIN_ACCEL_RELOC(10, 2);
|
||||
} else {
|
||||
BEGIN_ACCEL_RELOC(9, 1);
|
||||
}
|
||||
OUT_RING_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
|
||||
OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
|
||||
OUT_RING_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
|
||||
OUT_RING_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
|
||||
OUT_RING_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
|
||||
OUT_RING_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
|
||||
OUT_RING_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask);
|
||||
OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
|
||||
|
||||
OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
|
||||
OUT_RING_RELOC(info->state_2d.dst_bo, 0, info->state_2d.dst_domain);
|
||||
|
||||
if (has_src) {
|
||||
OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
|
||||
OUT_RING_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
}
|
||||
ADVANCE_RING();
|
||||
|
||||
if (op)
|
||||
info->state_2d.op = op;
|
||||
info->reemit_current2d = Emit2DState;
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONFlush2D(PixmapPtr pPix)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
|
||||
|
||||
TRACE;
|
||||
|
||||
BEGIN_RING(2*2);
|
||||
OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
|
||||
OUT_RING_REG(RADEON_WAIT_UNTIL,
|
||||
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONDone2D(PixmapPtr pPix)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
|
||||
info->state_2d.op = 0;
|
||||
|
||||
RADEONFlush2D(pPix);
|
||||
}
|
||||
|
||||
static Bool
|
||||
RADEONPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
|
||||
uint32_t datatype, dst_pitch_offset;
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
int ret;
|
||||
|
||||
TRACE;
|
||||
|
||||
if (pPix->drawable.bitsPerPixel == 24)
|
||||
RADEON_FALLBACK(("24bpp unsupported\n"));
|
||||
if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype))
|
||||
RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n"));
|
||||
if (!RADEONGetPixmapOffsetPitch(pPix, &dst_pitch_offset))
|
||||
RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n"));
|
||||
|
||||
RADEON_SWITCH_TO_2D();
|
||||
|
||||
radeon_cs_space_reset_bos(info->cs);
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
|
||||
RADEON_GEM_DOMAIN_VRAM);
|
||||
|
||||
ret = radeon_cs_space_check(info->cs);
|
||||
if (ret)
|
||||
RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
if (driver_priv) {
|
||||
info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
|
||||
info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
|
||||
}
|
||||
|
||||
info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX |
|
||||
RADEON_DEFAULT_SC_BOTTOM_MAX);
|
||||
info->state_2d.dp_brush_bkgd_clr = 0x00000000;
|
||||
info->state_2d.dp_src_frgd_clr = 0xffffffff;
|
||||
info->state_2d.dp_src_bkgd_clr = 0x00000000;
|
||||
info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_SOLID_COLOR |
|
||||
(datatype << 8) |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_ROP[alu].pattern |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS);
|
||||
info->state_2d.dp_brush_frgd_clr = fg;
|
||||
info->state_2d.dp_cntl = (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM);
|
||||
info->state_2d.dp_write_mask = pm;
|
||||
info->state_2d.dst_pitch_offset = dst_pitch_offset;
|
||||
info->state_2d.src_pitch_offset = 0;
|
||||
info->state_2d.src_bo = NULL;
|
||||
|
||||
info->accel_state->dst_pix = pPix;
|
||||
|
||||
Emit2DState(pScrn, RADEON_2D_EXA_SOLID);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
RADEONSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
|
||||
|
||||
TRACE;
|
||||
|
||||
if (CS_FULL(info->cs)) {
|
||||
RADEONFlush2D(info->accel_state->dst_pix);
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
}
|
||||
|
||||
if (info->accel_state->vsync)
|
||||
RADEONWaitForVLine(pScrn, pPix,
|
||||
radeon_pick_best_crtc(pScrn, FALSE, x1, x2, y1, y2),
|
||||
y1, y2);
|
||||
|
||||
BEGIN_RING(2*2);
|
||||
OUT_RING_REG(RADEON_DST_Y_X, (y1 << 16) | x1);
|
||||
OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONDoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
|
||||
uint32_t dst_pitch_offset, uint32_t datatype, int rop,
|
||||
Pixel planemask)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
|
||||
/* setup 2D state */
|
||||
info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_NONE |
|
||||
(datatype << 8) |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_ROP[rop].rop |
|
||||
RADEON_DP_SRC_SOURCE_MEMORY |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS);
|
||||
info->state_2d.dp_cntl = ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
|
||||
(info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
|
||||
info->state_2d.dp_brush_frgd_clr = 0xffffffff;
|
||||
info->state_2d.dp_brush_bkgd_clr = 0x00000000;
|
||||
info->state_2d.dp_src_frgd_clr = 0xffffffff;
|
||||
info->state_2d.dp_src_bkgd_clr = 0x00000000;
|
||||
info->state_2d.dp_write_mask = planemask;
|
||||
info->state_2d.dst_pitch_offset = dst_pitch_offset;
|
||||
info->state_2d.src_pitch_offset = src_pitch_offset;
|
||||
info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX
|
||||
| RADEON_DEFAULT_SC_BOTTOM_MAX);
|
||||
|
||||
Emit2DState(pScrn, RADEON_2D_EXA_COPY);
|
||||
}
|
||||
|
||||
static Bool
|
||||
RADEONPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
|
||||
int xdir, int ydir,
|
||||
int rop,
|
||||
Pixel planemask)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
|
||||
uint32_t datatype, src_pitch_offset, dst_pitch_offset;
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
int ret;
|
||||
TRACE;
|
||||
|
||||
if (pDst->drawable.bitsPerPixel == 24)
|
||||
RADEON_FALLBACK(("24bpp unsupported"));
|
||||
if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype))
|
||||
RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n"));
|
||||
if (!RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset))
|
||||
RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch source failed\n"));
|
||||
if (!RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset))
|
||||
RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch dest failed\n"));
|
||||
|
||||
RADEON_SWITCH_TO_2D();
|
||||
|
||||
radeon_cs_space_reset_bos(info->cs);
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pSrc);
|
||||
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon,
|
||||
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
info->state_2d.src_bo = driver_priv->bo->bo.radeon;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pDst);
|
||||
info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
|
||||
info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
|
||||
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
|
||||
info->state_2d.dst_domain);
|
||||
|
||||
ret = radeon_cs_space_check(info->cs);
|
||||
if (ret)
|
||||
RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n"));
|
||||
|
||||
info->accel_state->xdir = xdir;
|
||||
info->accel_state->ydir = ydir;
|
||||
info->accel_state->dst_pix = pDst;
|
||||
|
||||
RADEONDoPrepareCopy(pScrn, src_pitch_offset, dst_pitch_offset,
|
||||
datatype, rop, planemask);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONCopy(PixmapPtr pDst,
|
||||
int srcX, int srcY,
|
||||
int dstX, int dstY,
|
||||
int w, int h)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
|
||||
|
||||
TRACE;
|
||||
|
||||
if (CS_FULL(info->cs)) {
|
||||
RADEONFlush2D(info->accel_state->dst_pix);
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
}
|
||||
|
||||
if (info->accel_state->xdir < 0) {
|
||||
srcX += w - 1;
|
||||
dstX += w - 1;
|
||||
}
|
||||
if (info->accel_state->ydir < 0) {
|
||||
srcY += h - 1;
|
||||
dstY += h - 1;
|
||||
}
|
||||
|
||||
if (info->accel_state->vsync)
|
||||
RADEONWaitForVLine(pScrn, pDst,
|
||||
radeon_pick_best_crtc(pScrn, FALSE, dstX, dstX + w, dstY, dstY + h),
|
||||
dstY, dstY + h);
|
||||
|
||||
BEGIN_RING(2*3);
|
||||
|
||||
OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
|
||||
OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
|
||||
OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
/* Emit blit with arbitrary source and destination offsets and pitches */
|
||||
static void
|
||||
RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
|
||||
struct radeon_bo *dst_bo, uint32_t datatype,
|
||||
uint32_t src_pitch_offset, uint32_t dst_pitch_offset,
|
||||
int srcX, int srcY, int dstX, int dstY, int w, int h,
|
||||
uint32_t src_domain, uint32_t dst_domain)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
|
||||
if (src_bo && dst_bo) {
|
||||
BEGIN_ACCEL_RELOC(6, 2);
|
||||
} else if (src_bo && !dst_bo) {
|
||||
BEGIN_ACCEL_RELOC(6, 1);
|
||||
} else {
|
||||
BEGIN_RING(2*6);
|
||||
}
|
||||
OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL,
|
||||
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_NONE |
|
||||
(datatype << 8) |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_ROP3_S |
|
||||
RADEON_DP_SRC_SOURCE_MEMORY |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS |
|
||||
RADEON_GMC_WR_MSK_DIS);
|
||||
OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset);
|
||||
if (src_bo) {
|
||||
OUT_RING_RELOC(src_bo, src_domain, 0);
|
||||
}
|
||||
OUT_RING_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
|
||||
if (dst_bo) {
|
||||
OUT_RING_RELOC(dst_bo, 0, dst_domain);
|
||||
}
|
||||
OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
|
||||
OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
|
||||
OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
|
||||
ADVANCE_RING();
|
||||
BEGIN_RING(2*2);
|
||||
OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
|
||||
OUT_RING_REG(RADEON_WAIT_UNTIL,
|
||||
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static Bool
|
||||
RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
|
||||
char *src, int src_pitch)
|
||||
{
|
||||
ScreenPtr pScreen = pDst->drawable.pScreen;
|
||||
RINFO_FROM_SCREEN(pScreen);
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
struct radeon_bo *scratch = NULL;
|
||||
struct radeon_bo *copy_dst;
|
||||
unsigned char *dst;
|
||||
unsigned size;
|
||||
uint32_t datatype = 0;
|
||||
uint32_t dst_domain;
|
||||
uint32_t dst_pitch_offset;
|
||||
unsigned bpp = pDst->drawable.bitsPerPixel;
|
||||
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
|
||||
uint32_t copy_pitch;
|
||||
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
|
||||
int ret;
|
||||
Bool flush = TRUE;
|
||||
Bool r;
|
||||
int i;
|
||||
|
||||
if (bpp < 8)
|
||||
return FALSE;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pDst);
|
||||
if (!driver_priv || !driver_priv->bo->bo.radeon)
|
||||
return FALSE;
|
||||
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
switch (bpp) {
|
||||
case 32:
|
||||
swap = RADEON_HOST_DATA_SWAP_32BIT;
|
||||
break;
|
||||
case 16:
|
||||
swap = RADEON_HOST_DATA_SWAP_16BIT;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
|
||||
copy_dst = driver_priv->bo->bo.radeon;
|
||||
copy_pitch = pDst->devKind;
|
||||
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
|
||||
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
|
||||
flush = FALSE;
|
||||
if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
|
||||
!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
|
||||
goto copy;
|
||||
}
|
||||
/* use cpu copy for fast fb access */
|
||||
if (info->is_fast_fb)
|
||||
goto copy;
|
||||
}
|
||||
|
||||
size = scratch_pitch * h;
|
||||
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
if (!scratch) {
|
||||
goto copy;
|
||||
}
|
||||
radeon_cs_space_reset_bos(info->cs);
|
||||
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
|
||||
radeon_cs_space_add_persistent_bo(info->cs, scratch, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
ret = radeon_cs_space_check(info->cs);
|
||||
if (ret) {
|
||||
goto copy;
|
||||
}
|
||||
copy_dst = scratch;
|
||||
copy_pitch = scratch_pitch;
|
||||
flush = FALSE;
|
||||
|
||||
copy:
|
||||
if (flush)
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
|
||||
ret = radeon_bo_map(copy_dst, 0);
|
||||
if (ret) {
|
||||
r = FALSE;
|
||||
goto out;
|
||||
}
|
||||
r = TRUE;
|
||||
size = w * bpp / 8;
|
||||
dst = copy_dst->ptr;
|
||||
if (copy_dst == driver_priv->bo->bo.radeon)
|
||||
dst += y * copy_pitch + x * bpp / 8;
|
||||
for (i = 0; i < h; i++) {
|
||||
RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap);
|
||||
src += src_pitch;
|
||||
}
|
||||
radeon_bo_unmap(copy_dst);
|
||||
|
||||
if (copy_dst == scratch) {
|
||||
RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype);
|
||||
RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset);
|
||||
RADEON_SWITCH_TO_2D();
|
||||
RADEONBlitChunk(pScrn, scratch, driver_priv->bo->bo.radeon, datatype, scratch_pitch << 16,
|
||||
dst_pitch_offset, 0, 0, x, y, w, h,
|
||||
RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_VRAM);
|
||||
}
|
||||
|
||||
out:
|
||||
if (scratch)
|
||||
radeon_bo_unref(scratch);
|
||||
return r;
|
||||
}
|
||||
|
||||
static Bool
|
||||
RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
|
||||
int h, char *dst, int dst_pitch)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
|
||||
struct radeon_exa_pixmap_priv *driver_priv;
|
||||
struct radeon_bo *scratch = NULL;
|
||||
struct radeon_bo *copy_src;
|
||||
unsigned size;
|
||||
uint32_t datatype = 0;
|
||||
uint32_t src_domain = 0;
|
||||
uint32_t src_pitch_offset;
|
||||
unsigned bpp = pSrc->drawable.bitsPerPixel;
|
||||
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
|
||||
uint32_t copy_pitch;
|
||||
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
|
||||
int ret;
|
||||
Bool flush = FALSE;
|
||||
Bool r;
|
||||
|
||||
if (bpp < 8)
|
||||
return FALSE;
|
||||
|
||||
driver_priv = exaGetPixmapDriverPrivate(pSrc);
|
||||
if (!driver_priv || !driver_priv->bo->bo.radeon)
|
||||
return FALSE;
|
||||
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
switch (bpp) {
|
||||
case 32:
|
||||
swap = RADEON_HOST_DATA_SWAP_32BIT;
|
||||
break;
|
||||
case 16:
|
||||
swap = RADEON_HOST_DATA_SWAP_16BIT;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
|
||||
copy_src = driver_priv->bo->bo.radeon;
|
||||
copy_pitch = pSrc->devKind;
|
||||
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
|
||||
if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
|
||||
src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
|
||||
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
|
||||
(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
|
||||
src_domain = 0;
|
||||
else /* A write may be scheduled */
|
||||
flush = TRUE;
|
||||
}
|
||||
|
||||
if (!src_domain)
|
||||
radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);
|
||||
|
||||
if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
|
||||
goto copy;
|
||||
}
|
||||
size = scratch_pitch * h;
|
||||
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
if (!scratch) {
|
||||
goto copy;
|
||||
}
|
||||
radeon_cs_space_reset_bos(info->cs);
|
||||
radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
|
||||
radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, RADEON_GEM_DOMAIN_GTT);
|
||||
ret = radeon_cs_space_check(info->cs);
|
||||
if (ret) {
|
||||
goto copy;
|
||||
}
|
||||
RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype);
|
||||
RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset);
|
||||
RADEON_SWITCH_TO_2D();
|
||||
RADEONBlitChunk(pScrn, driver_priv->bo->bo.radeon, scratch, datatype,
|
||||
src_pitch_offset, scratch_pitch << 16, x, y, 0, 0, w, h,
|
||||
RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT,
|
||||
RADEON_GEM_DOMAIN_GTT);
|
||||
copy_src = scratch;
|
||||
copy_pitch = scratch_pitch;
|
||||
flush = TRUE;
|
||||
|
||||
copy:
|
||||
if (flush)
|
||||
FLUSH_RING();
|
||||
|
||||
ret = radeon_bo_map(copy_src, 0);
|
||||
if (ret) {
|
||||
ErrorF("failed to map pixmap: %d\n", ret);
|
||||
r = FALSE;
|
||||
goto out;
|
||||
}
|
||||
r = TRUE;
|
||||
w *= bpp / 8;
|
||||
if (copy_src == driver_priv->bo->bo.radeon)
|
||||
size = y * copy_pitch + x * bpp / 8;
|
||||
else
|
||||
size = 0;
|
||||
while (h--) {
|
||||
RADEONCopySwap((uint8_t*)dst, copy_src->ptr + size, w, swap);
|
||||
size += copy_pitch;
|
||||
dst += dst_pitch;
|
||||
}
|
||||
radeon_bo_unmap(copy_src);
|
||||
out:
|
||||
if (scratch)
|
||||
radeon_bo_unref(scratch);
|
||||
return r;
|
||||
}
|
||||
|
||||
Bool RADEONDrawInit(ScreenPtr pScreen)
|
||||
{
|
||||
RINFO_FROM_SCREEN(pScreen);
|
||||
|
||||
if (!info->accel_state->exa) {
|
||||
xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
|
||||
info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
|
||||
|
||||
info->accel_state->exa->PrepareSolid = RADEONPrepareSolid;
|
||||
info->accel_state->exa->Solid = RADEONSolid;
|
||||
info->accel_state->exa->DoneSolid = RADEONDone2D;
|
||||
|
||||
info->accel_state->exa->PrepareCopy = RADEONPrepareCopy;
|
||||
info->accel_state->exa->Copy = RADEONCopy;
|
||||
info->accel_state->exa->DoneCopy = RADEONDone2D;
|
||||
|
||||
info->accel_state->exa->MarkSync = RADEONMarkSync;
|
||||
info->accel_state->exa->WaitMarker = RADEONSync;
|
||||
|
||||
info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS;
|
||||
info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS;
|
||||
|
||||
info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX |
|
||||
EXA_SUPPORTS_OFFSCREEN_OVERLAPS | EXA_HANDLES_PIXMAPS | EXA_MIXED_PIXMAPS;
|
||||
info->accel_state->exa->pixmapOffsetAlign = RADEON_GPU_PAGE_SIZE;
|
||||
info->accel_state->exa->pixmapPitchAlign = 64;
|
||||
|
||||
#ifdef RENDER
|
||||
if (info->RenderAccel) {
|
||||
if (IS_R300_3D || IS_R500_3D) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
|
||||
"enabled for R300/R400/R500 type cards.\n");
|
||||
info->accel_state->exa->CheckComposite = R300CheckComposite;
|
||||
info->accel_state->exa->PrepareComposite =
|
||||
R300PrepareComposite;
|
||||
info->accel_state->exa->Composite = RadeonComposite;
|
||||
info->accel_state->exa->DoneComposite = RadeonDoneComposite;
|
||||
} else if (IS_R200_3D) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
|
||||
"enabled for R200 type cards.\n");
|
||||
info->accel_state->exa->CheckComposite = R200CheckComposite;
|
||||
info->accel_state->exa->PrepareComposite =
|
||||
R200PrepareComposite;
|
||||
info->accel_state->exa->Composite = RadeonComposite;
|
||||
info->accel_state->exa->DoneComposite = RadeonDoneComposite;
|
||||
} else {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
|
||||
"enabled for R100 type cards.\n");
|
||||
info->accel_state->exa->CheckComposite = R100CheckComposite;
|
||||
info->accel_state->exa->PrepareComposite =
|
||||
R100PrepareComposite;
|
||||
info->accel_state->exa->Composite = RadeonComposite;
|
||||
info->accel_state->exa->DoneComposite = RadeonDoneComposite;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
|
||||
info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
|
||||
info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
|
||||
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
|
||||
info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
|
||||
info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking;
|
||||
info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking;
|
||||
|
||||
|
||||
info->accel_state->exa->maxPitchBytes = 16320;
|
||||
info->accel_state->exa->maxX = 8191;
|
||||
info->accel_state->exa->maxY = 8191;
|
||||
|
||||
if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n");
|
||||
info->accel_state->vsync = TRUE;
|
||||
} else
|
||||
info->accel_state->vsync = FALSE;
|
||||
|
||||
RADEONEngineInit(pScrn);
|
||||
|
||||
if (!exaDriverInit(pScreen, info->accel_state->exa)) {
|
||||
free(info->accel_state->exa);
|
||||
return FALSE;
|
||||
}
|
||||
exaMarkSync(pScreen);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
2425
src/radeon_exa_render.c
Normal file
2425
src/radeon_exa_render.c
Normal file
File diff suppressed because it is too large
Load diff
220
src/radeon_exa_shared.c
Normal file
220
src/radeon_exa_shared.c
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright 2005 Eric Anholt
|
||||
* Copyright 2005 Benjamin Herrenschmidt
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Zack Rusin <zrusin@trolltech.com>
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
* Alex Deucher <alexander.deucher@amd.com>
|
||||
* Matthias Hopf <mhopf@suse.de>
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_version.h"
|
||||
#include "radeon_vbo.h"
|
||||
|
||||
PixmapPtr
|
||||
RADEONGetDrawablePixmap(DrawablePtr pDrawable)
|
||||
{
|
||||
if (pDrawable->type == DRAWABLE_WINDOW)
|
||||
return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
|
||||
else
|
||||
return (PixmapPtr)pDrawable;
|
||||
}
|
||||
|
||||
void RADEONVlineHelperClear(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
accel_state->vline_crtc = NULL;
|
||||
accel_state->vline_y1 = -1;
|
||||
accel_state->vline_y2 = 0;
|
||||
}
|
||||
|
||||
void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
accel_state->vline_crtc =
|
||||
radeon_pick_best_crtc(pScrn, FALSE, x1, x2, y1, y2);
|
||||
if (accel_state->vline_y1 == -1)
|
||||
accel_state->vline_y1 = y1;
|
||||
if (y1 < accel_state->vline_y1)
|
||||
accel_state->vline_y1 = y1;
|
||||
if (y2 > accel_state->vline_y2)
|
||||
accel_state->vline_y2 = y2;
|
||||
}
|
||||
|
||||
Bool RADEONValidPM(uint32_t pm, int bpp)
|
||||
{
|
||||
uint8_t r, g, b, a;
|
||||
Bool ret = FALSE;
|
||||
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
a = pm & 0xff;
|
||||
if ((a == 0) || (a == 0xff))
|
||||
ret = TRUE;
|
||||
break;
|
||||
case 16:
|
||||
r = (pm >> 11) & 0x1f;
|
||||
g = (pm >> 5) & 0x3f;
|
||||
b = (pm >> 0) & 0x1f;
|
||||
if (((r == 0) || (r == 0x1f)) &&
|
||||
((g == 0) || (g == 0x3f)) &&
|
||||
((b == 0) || (b == 0x1f)))
|
||||
ret = TRUE;
|
||||
break;
|
||||
case 32:
|
||||
a = (pm >> 24) & 0xff;
|
||||
r = (pm >> 16) & 0xff;
|
||||
g = (pm >> 8) & 0xff;
|
||||
b = (pm >> 0) & 0xff;
|
||||
if (((a == 0) || (a == 0xff)) &&
|
||||
((r == 0) || (r == 0xff)) &&
|
||||
((g == 0) || (g == 0xff)) &&
|
||||
((b == 0) || (b == 0xff)))
|
||||
ret = TRUE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
Bool RADEONCheckBPP(int bpp)
|
||||
{
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 32:
|
||||
return TRUE;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid)
|
||||
{
|
||||
PixmapPtr pPix = pScreen->CreatePixmap(pScreen, 1, 1, 32, 0);
|
||||
struct radeon_bo *bo;
|
||||
exaMoveInPixmap(pPix);
|
||||
|
||||
bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
|
||||
|
||||
if (radeon_bo_map(bo, 1)) {
|
||||
dixDestroyPixmap(pPix, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memcpy(bo->ptr, &solid, 4);
|
||||
radeon_bo_unmap(bo);
|
||||
|
||||
return pPix;
|
||||
}
|
||||
|
||||
int radeon_cp_start(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
if (CS_FULL(info->cs)) {
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
}
|
||||
accel_state->ib_reset_op = info->cs->cdw;
|
||||
accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
|
||||
accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void radeon_vb_no_space(ScrnInfoPtr pScrn,
|
||||
struct radeon_vbo_object *vbo,
|
||||
int vert_size)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
if (vbo->vb_bo) {
|
||||
if (vbo->vb_start_op != vbo->vb_offset) {
|
||||
accel_state->finish_op(pScrn, vert_size);
|
||||
accel_state->ib_reset_op = info->cs->cdw;
|
||||
}
|
||||
|
||||
/* release the current VBO */
|
||||
radeon_vbo_put(pScrn, vbo);
|
||||
}
|
||||
/* get a new one */
|
||||
radeon_vbo_get(pScrn, vbo);
|
||||
return;
|
||||
}
|
||||
|
||||
void radeon_ib_discard(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int ret;
|
||||
|
||||
if (info->accel_state->ib_reset_op) {
|
||||
/* if we have data just reset the CS and ignore the operation */
|
||||
info->cs->cdw = info->accel_state->ib_reset_op;
|
||||
info->accel_state->ib_reset_op = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
info->accel_state->vbo.vb_offset = 0;
|
||||
info->accel_state->vbo.vb_start_op = -1;
|
||||
info->accel_state->cbuf.vb_offset = 0;
|
||||
info->accel_state->cbuf.vb_start_op = -1;
|
||||
|
||||
if (CS_FULL(info->cs)) {
|
||||
radeon_cs_flush_indirect(pScrn);
|
||||
return;
|
||||
}
|
||||
radeon_cs_erase(info->cs);
|
||||
ret = radeon_cs_space_check_with_bo(info->cs,
|
||||
info->accel_state->vbo.vb_bo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
if (ret)
|
||||
ErrorF("space check failed in flush\n");
|
||||
|
||||
if (info->accel_state->cbuf.vb_bo) {
|
||||
ret = radeon_cs_space_check_with_bo(info->cs,
|
||||
info->accel_state->cbuf.vb_bo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
if (ret)
|
||||
ErrorF("space check failed in flush\n");
|
||||
}
|
||||
|
||||
out:
|
||||
if (info->dri2.enabled) {
|
||||
info->accel_state->XInited3D = FALSE;
|
||||
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
|
||||
}
|
||||
|
||||
}
|
||||
79
src/radeon_exa_shared.h
Normal file
79
src/radeon_exa_shared.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright 2005 Eric Anholt
|
||||
* Copyright 2005 Benjamin Herrenschmidt
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Zack Rusin <zrusin@trolltech.com>
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
* Alex Deucher <alexander.deucher@amd.com>
|
||||
* Matthias Hopf <mhopf@suse.de>
|
||||
*/
|
||||
#ifndef RADEON_EXA_SHARED_H
|
||||
|
||||
#define RADEON_EXA_SHARED_H
|
||||
|
||||
extern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable);
|
||||
|
||||
extern void RADEONVlineHelperClear(ScrnInfoPtr pScrn);
|
||||
extern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
|
||||
extern Bool RADEONValidPM(uint32_t pm, int bpp);
|
||||
extern Bool RADEONCheckBPP(int bpp);
|
||||
extern PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid);
|
||||
|
||||
#define RADEON_TRACE_FALL 0
|
||||
#define RADEON_TRACE_DRAW 0
|
||||
|
||||
#if RADEON_TRACE_FALL
|
||||
#define RADEON_FALLBACK(x) \
|
||||
do { \
|
||||
ErrorF("%s: ", __FUNCTION__); \
|
||||
ErrorF x; \
|
||||
return FALSE; \
|
||||
} while (0)
|
||||
#else
|
||||
#define RADEON_FALLBACK(x) return FALSE
|
||||
#endif
|
||||
|
||||
#if RADEON_TRACE_DRAW
|
||||
#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
|
||||
#else
|
||||
#define TRACE
|
||||
#endif
|
||||
|
||||
static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
|
||||
{
|
||||
struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
|
||||
|
||||
radeon_cs_space_add_persistent_bo(cs, driver_priv->bo->bo.radeon,
|
||||
read_domains, write_domain);
|
||||
}
|
||||
|
||||
extern void radeon_ib_discard(ScrnInfoPtr pScrn);
|
||||
|
||||
extern int radeon_cp_start(ScrnInfoPtr pScrn);
|
||||
extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);
|
||||
extern void radeon_vbo_done_composite(PixmapPtr pDst);
|
||||
|
||||
#endif
|
||||
464
src/radeon_glamor.c
Normal file
464
src/radeon_glamor.c
Normal file
|
|
@ -0,0 +1,464 @@
|
|||
/*
|
||||
* Copyright © 2011 Intel Corporation.
|
||||
* 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including
|
||||
* the next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <xf86.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_bo_helper.h"
|
||||
#include "radeon_glamor.h"
|
||||
|
||||
DevPrivateKeyRec glamor_pixmap_index;
|
||||
|
||||
void
|
||||
radeon_glamor_exchange_buffers(PixmapPtr src,
|
||||
PixmapPtr dst)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(dst->drawable.pScreen));
|
||||
|
||||
if (!info->use_glamor)
|
||||
return;
|
||||
glamor_egl_exchange_buffers(src, dst);
|
||||
}
|
||||
|
||||
Bool
|
||||
radeon_glamor_create_screen_resources(ScreenPtr screen)
|
||||
{
|
||||
PixmapPtr screen_pixmap = screen->GetScreenPixmap(screen);
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
if (!info->use_glamor)
|
||||
return TRUE;
|
||||
|
||||
#ifdef HAVE_GLAMOR_GLYPHS_INIT
|
||||
if (!glamor_glyphs_init(screen))
|
||||
return FALSE;
|
||||
#endif
|
||||
|
||||
return radeon_glamor_create_textured_pixmap(screen_pixmap,
|
||||
info->front_buffer);
|
||||
}
|
||||
|
||||
|
||||
Bool
|
||||
radeon_glamor_pre_init(ScrnInfoPtr scrn)
|
||||
{
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
void *glamor_module;
|
||||
CARD32 version;
|
||||
const char *s;
|
||||
|
||||
if (!info->dri2.available)
|
||||
return FALSE;
|
||||
|
||||
s = xf86GetOptValString(info->Options, OPTION_ACCELMETHOD);
|
||||
if (!s) {
|
||||
if (info->ChipFamily < CHIP_FAMILY_R600)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (s && strcasecmp(s, "glamor") != 0) {
|
||||
if (info->ChipFamily >= CHIP_FAMILY_TAHITI)
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"EXA not supported, using glamor\n");
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (info->ChipFamily < CHIP_FAMILY_R300) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"glamor requires R300 or higher GPU, disabling.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (info->ChipFamily < CHIP_FAMILY_RV515) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"glamor may not work (well) with GPUs < RV515.\n");
|
||||
}
|
||||
|
||||
if (scrn->depth < 15) {
|
||||
xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING,
|
||||
"Depth %d not supported with glamor, disabling\n",
|
||||
scrn->depth);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
info->gbm = gbm_create_device(pRADEONEnt->fd);
|
||||
if (!info->gbm) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"gbm_create_device returned NULL\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Load glamor module */
|
||||
if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) {
|
||||
version = xf86GetModuleVersion(glamor_module);
|
||||
if (version < MODULE_VERSION_NUMERIC(0,3,1)) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"Incompatible glamor version, required >= 0.3.0.\n");
|
||||
return FALSE;
|
||||
} else {
|
||||
if (glamor_egl_init(scrn, pRADEONEnt->fd)) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_INFO,
|
||||
"glamor detected, initialising EGL layer.\n");
|
||||
} else {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"glamor detected, failed to initialize EGL.\n");
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR, "glamor not available\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
info->use_glamor = TRUE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Bool
|
||||
radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
if (!info->use_glamor)
|
||||
return TRUE;
|
||||
|
||||
if (bo->flags & RADEON_BO_FLAGS_GBM) {
|
||||
return glamor_egl_create_textured_pixmap_from_gbm_bo(pixmap,
|
||||
bo->bo.gbm,
|
||||
FALSE);
|
||||
} else {
|
||||
return glamor_egl_create_textured_pixmap(pixmap,
|
||||
bo->bo.radeon->handle,
|
||||
pixmap->devKind);
|
||||
}
|
||||
}
|
||||
|
||||
static Bool radeon_glamor_destroy_pixmap(PixmapPtr pixmap)
|
||||
{
|
||||
ScreenPtr screen = pixmap->drawable.pScreen;
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen));
|
||||
Bool ret = TRUE;
|
||||
|
||||
if (pixmap->refcnt == 1)
|
||||
radeon_set_pixmap_bo(pixmap, NULL);
|
||||
|
||||
if (info->glamor.SavedDestroyPixmap) {
|
||||
screen->DestroyPixmap = info->glamor.SavedDestroyPixmap;
|
||||
ret = screen->DestroyPixmap(pixmap);
|
||||
}
|
||||
screen->DestroyPixmap = radeon_glamor_destroy_pixmap;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static PixmapPtr
|
||||
radeon_glamor_create_pixmap(ScreenPtr screen, int w, int h, int depth,
|
||||
unsigned usage)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
struct radeon_pixmap *priv;
|
||||
PixmapPtr pixmap, new_pixmap = NULL;
|
||||
|
||||
if (!xf86GetPixFormat(scrn, depth))
|
||||
return NULL;
|
||||
|
||||
if (!RADEON_CREATE_PIXMAP_SHARED(usage)) {
|
||||
if (info->shadow_primary) {
|
||||
if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP)
|
||||
return fbCreatePixmap(screen, w, h, depth, usage);
|
||||
} else {
|
||||
pixmap = glamor_create_pixmap(screen, w, h, depth, usage);
|
||||
if (pixmap)
|
||||
return pixmap;
|
||||
}
|
||||
}
|
||||
|
||||
if (w > 32767 || h > 32767)
|
||||
return NullPixmap;
|
||||
|
||||
if (depth == 1)
|
||||
return fbCreatePixmap(screen, w, h, depth, usage);
|
||||
|
||||
if (usage == CREATE_PIXMAP_USAGE_GLYPH_PICTURE && w <= 32 && h <= 32)
|
||||
return fbCreatePixmap(screen, w, h, depth, usage);
|
||||
|
||||
pixmap = fbCreatePixmap(screen, 0, 0, depth, usage);
|
||||
if (pixmap == NullPixmap)
|
||||
return pixmap;
|
||||
|
||||
if (w && h) {
|
||||
int stride;
|
||||
|
||||
priv = calloc(1, sizeof (struct radeon_pixmap));
|
||||
if (!priv)
|
||||
goto fallback_pixmap;
|
||||
|
||||
priv->bo = radeon_alloc_pixmap_bo(scrn, w, h, depth, usage,
|
||||
pixmap->drawable.bitsPerPixel,
|
||||
&stride, NULL,
|
||||
&priv->tiling_flags);
|
||||
if (!priv->bo)
|
||||
goto fallback_priv;
|
||||
|
||||
radeon_set_pixmap_private(pixmap, priv);
|
||||
|
||||
screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL);
|
||||
|
||||
if (!radeon_glamor_create_textured_pixmap(pixmap, priv->bo))
|
||||
goto fallback_glamor;
|
||||
|
||||
pixmap->devPrivate.ptr = NULL;
|
||||
}
|
||||
|
||||
return pixmap;
|
||||
|
||||
fallback_glamor:
|
||||
if (RADEON_CREATE_PIXMAP_SHARED(usage)) {
|
||||
/* XXX need further work to handle the DRI2 failure case.
|
||||
* Glamor don't know how to handle a BO only pixmap. Put
|
||||
* a warning indicator here.
|
||||
*/
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"Failed to create textured DRI2/PRIME pixmap.");
|
||||
|
||||
radeon_glamor_destroy_pixmap(pixmap);
|
||||
return NullPixmap;
|
||||
}
|
||||
/* Create textured pixmap failed means glamor failed to
|
||||
* create a texture from current BO for some reasons. We turn
|
||||
* to create a new glamor pixmap and clean up current one.
|
||||
* One thing need to be noted, this new pixmap doesn't
|
||||
* has a priv and bo attached to it. It's glamor's responsbility
|
||||
* to take care of it. Glamor will mark this new pixmap as a
|
||||
* texture only pixmap and will never fallback to DDX layer
|
||||
* afterwards.
|
||||
*/
|
||||
new_pixmap = glamor_create_pixmap(screen, w, h, depth, usage);
|
||||
radeon_buffer_unref(&priv->bo);
|
||||
fallback_priv:
|
||||
free(priv);
|
||||
fallback_pixmap:
|
||||
fbDestroyPixmap(pixmap);
|
||||
if (new_pixmap)
|
||||
return new_pixmap;
|
||||
else
|
||||
return fbCreatePixmap(screen, w, h, depth, usage);
|
||||
}
|
||||
|
||||
PixmapPtr
|
||||
radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap)
|
||||
{
|
||||
PixmapPtr old = get_drawable_pixmap(drawable);
|
||||
ScreenPtr screen = drawable->pScreen;
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
GCPtr gc;
|
||||
|
||||
/* With a glamor pixmap, 2D pixmaps are created in texture
|
||||
* and without a static BO attached to it. To support DRI,
|
||||
* we need to create a new textured-drm pixmap and
|
||||
* need to copy the original content to this new textured-drm
|
||||
* pixmap, and then convert the old pixmap to a coherent
|
||||
* textured-drm pixmap which has a valid BO attached to it
|
||||
* and also has a valid texture, thus both glamor and DRI2
|
||||
* can access it.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Copy the current contents of the pixmap to the bo. */
|
||||
gc = GetScratchGC(drawable->depth, screen);
|
||||
if (gc) {
|
||||
ValidateGC(&pixmap->drawable, gc);
|
||||
gc->ops->CopyArea(&old->drawable, &pixmap->drawable,
|
||||
gc,
|
||||
0, 0,
|
||||
old->drawable.width,
|
||||
old->drawable.height, 0, 0);
|
||||
FreeScratchGC(gc);
|
||||
}
|
||||
|
||||
/* And redirect the pixmap to the new bo (for 3D). */
|
||||
glamor_egl_exchange_buffers(old, pixmap);
|
||||
radeon_set_pixmap_private(pixmap, radeon_get_pixmap_private(old));
|
||||
radeon_set_pixmap_private(old, priv);
|
||||
|
||||
screen->ModifyPixmapHeader(old,
|
||||
old->drawable.width,
|
||||
old->drawable.height,
|
||||
0, 0, pixmap->devKind, NULL);
|
||||
old->devPrivate.ptr = NULL;
|
||||
|
||||
dixDestroyPixmap(pixmap, 0);
|
||||
|
||||
return old;
|
||||
}
|
||||
|
||||
|
||||
static Bool
|
||||
radeon_glamor_share_pixmap_backing(PixmapPtr pixmap, ScreenPtr secondary,
|
||||
void **handle_p)
|
||||
{
|
||||
ScreenPtr screen = pixmap->drawable.pScreen;
|
||||
CARD16 stride;
|
||||
CARD32 size;
|
||||
int fd;
|
||||
|
||||
if ((radeon_get_pixmap_tiling_flags(pixmap) &
|
||||
RADEON_TILING_MASK) != RADEON_TILING_LINEAR) {
|
||||
PixmapPtr linear;
|
||||
|
||||
/* We don't want to re-allocate the screen pixmap as
|
||||
* linear, to avoid trouble with page flipping
|
||||
*/
|
||||
if (screen->GetScreenPixmap(screen) == pixmap)
|
||||
return FALSE;
|
||||
|
||||
linear = screen->CreatePixmap(screen, pixmap->drawable.width,
|
||||
pixmap->drawable.height,
|
||||
pixmap->drawable.depth,
|
||||
CREATE_PIXMAP_USAGE_SHARED);
|
||||
if (!linear)
|
||||
return FALSE;
|
||||
|
||||
radeon_glamor_set_pixmap_bo(&pixmap->drawable, linear);
|
||||
}
|
||||
|
||||
fd = glamor_fd_from_pixmap(screen, pixmap, &stride, &size);
|
||||
if (fd < 0)
|
||||
return FALSE;
|
||||
|
||||
*handle_p = (void *)(long)fd;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_glamor_set_shared_pixmap_backing(PixmapPtr pixmap, void *handle)
|
||||
{
|
||||
ScreenPtr screen = pixmap->drawable.pScreen;
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
int ihandle = (int)(long)handle;
|
||||
|
||||
if (!radeon_set_shared_pixmap_backing(pixmap, handle, NULL))
|
||||
return FALSE;
|
||||
|
||||
if (ihandle != -1 &&
|
||||
!radeon_glamor_create_textured_pixmap(pixmap,
|
||||
radeon_get_pixmap_bo(pixmap))) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"Failed to get PRIME drawable for glamor pixmap.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
screen->ModifyPixmapHeader(pixmap,
|
||||
pixmap->drawable.width,
|
||||
pixmap->drawable.height,
|
||||
0, 0, 0, NULL);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
Bool
|
||||
radeon_glamor_init(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
#ifdef RENDER
|
||||
UnrealizeGlyphProcPtr SavedUnrealizeGlyph = NULL;
|
||||
PictureScreenPtr ps = NULL;
|
||||
|
||||
if (info->shadow_primary) {
|
||||
ps = GetPictureScreenIfSet(screen);
|
||||
|
||||
if (ps) {
|
||||
SavedUnrealizeGlyph = ps->UnrealizeGlyph;
|
||||
info->glamor.SavedGlyphs = ps->Glyphs;
|
||||
info->glamor.SavedTriangles = ps->Triangles;
|
||||
info->glamor.SavedTrapezoids = ps->Trapezoids;
|
||||
}
|
||||
}
|
||||
#endif /* RENDER */
|
||||
|
||||
if (!glamor_init(screen, GLAMOR_USE_EGL_SCREEN | GLAMOR_USE_SCREEN |
|
||||
GLAMOR_USE_PICTURE_SCREEN | GLAMOR_INVERTED_Y_AXIS |
|
||||
GLAMOR_NO_DRI3)) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
|
||||
"Failed to initialize glamor.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (!dixRegisterPrivateKey(&glamor_pixmap_index, PRIVATE_PIXMAP, 0))
|
||||
return FALSE;
|
||||
|
||||
if (info->shadow_primary)
|
||||
radeon_glamor_screen_init(screen);
|
||||
|
||||
#if defined(RENDER)
|
||||
/* For ShadowPrimary, we need fbUnrealizeGlyph instead of
|
||||
* glamor_unrealize_glyph
|
||||
*/
|
||||
if (ps)
|
||||
ps->UnrealizeGlyph = SavedUnrealizeGlyph;
|
||||
#endif
|
||||
|
||||
info->glamor.SavedCreatePixmap = screen->CreatePixmap;
|
||||
screen->CreatePixmap = radeon_glamor_create_pixmap;
|
||||
info->glamor.SavedDestroyPixmap = screen->DestroyPixmap;
|
||||
screen->DestroyPixmap = radeon_glamor_destroy_pixmap;
|
||||
info->glamor.SavedSharePixmapBacking = screen->SharePixmapBacking;
|
||||
screen->SharePixmapBacking = radeon_glamor_share_pixmap_backing;
|
||||
info->glamor.SavedSetSharedPixmapBacking = screen->SetSharedPixmapBacking;
|
||||
screen->SetSharedPixmapBacking = radeon_glamor_set_shared_pixmap_backing;
|
||||
|
||||
xf86DrvMsg(scrn->scrnIndex, X_INFO,
|
||||
"Use GLAMOR acceleration.\n");
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void
|
||||
radeon_glamor_fini(ScreenPtr screen)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen));
|
||||
|
||||
if (!info->use_glamor)
|
||||
return;
|
||||
|
||||
screen->CreatePixmap = info->glamor.SavedCreatePixmap;
|
||||
screen->DestroyPixmap = info->glamor.SavedDestroyPixmap;
|
||||
screen->SharePixmapBacking = info->glamor.SavedSharePixmapBacking;
|
||||
screen->SetSharedPixmapBacking = info->glamor.SavedSetSharedPixmapBacking;
|
||||
}
|
||||
|
||||
XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt)
|
||||
{
|
||||
return glamor_xv_init(pScreen, num_adapt);
|
||||
}
|
||||
116
src/radeon_glamor.h
Normal file
116
src/radeon_glamor.h
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Copyright © 2011 Intel Corporation.
|
||||
* 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including
|
||||
* the next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef RADEON_GLAMOR_H
|
||||
#define RADEON_GLAMOR_H
|
||||
|
||||
#include "xf86xv.h"
|
||||
|
||||
struct radeon_pixmap;
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
|
||||
#ifndef HAVE_GLAMOR_FINISH
|
||||
#include <GL/gl.h>
|
||||
#endif
|
||||
|
||||
#include <gbm.h>
|
||||
|
||||
#define GLAMOR_FOR_XORG 1
|
||||
#include <glamor.h>
|
||||
|
||||
#include "radeon_surface.h"
|
||||
|
||||
#define RADEON_CREATE_PIXMAP_SHARED(usage) \
|
||||
(((usage) & ~RADEON_CREATE_PIXMAP_TILING_FLAGS) == RADEON_CREATE_PIXMAP_DRI2 || \
|
||||
(usage) == CREATE_PIXMAP_USAGE_SHARED)
|
||||
|
||||
#ifndef GLAMOR_NO_DRI3
|
||||
#define GLAMOR_NO_DRI3 0
|
||||
#define glamor_fd_from_pixmap glamor_dri3_fd_from_pixmap
|
||||
#define glamor_pixmap_from_fd glamor_egl_dri3_pixmap_from_fd
|
||||
#endif
|
||||
|
||||
#ifndef GLAMOR_INVERTED_Y_AXIS
|
||||
#define GLAMOR_INVERTED_Y_AXIS 0
|
||||
#endif
|
||||
#ifndef GLAMOR_USE_SCREEN
|
||||
#define GLAMOR_USE_SCREEN 0
|
||||
#endif
|
||||
#ifndef GLAMOR_USE_PICTURE_SCREEN
|
||||
#define GLAMOR_USE_PICTURE_SCREEN 0
|
||||
#endif
|
||||
|
||||
Bool radeon_glamor_pre_init(ScrnInfoPtr scrn);
|
||||
Bool radeon_glamor_init(ScreenPtr screen);
|
||||
void radeon_glamor_fini(ScreenPtr screen);
|
||||
void radeon_glamor_screen_init(ScreenPtr screen);
|
||||
Bool radeon_glamor_create_screen_resources(ScreenPtr screen);
|
||||
void radeon_glamor_free_screen(int scrnIndex, int flags);
|
||||
|
||||
Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo);
|
||||
void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
|
||||
PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap);
|
||||
|
||||
XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt);
|
||||
|
||||
static inline void
|
||||
radeon_glamor_finish(ScrnInfoPtr scrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
#if HAVE_GLAMOR_FINISH
|
||||
glamor_finish(scrn->pScreen);
|
||||
#else
|
||||
glamor_block_handler(scrn->pScreen);
|
||||
glFinish();
|
||||
#endif
|
||||
|
||||
info->gpu_flushed++;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { return FALSE; }
|
||||
static inline Bool radeon_glamor_init(ScreenPtr screen) { return FALSE; }
|
||||
static inline void radeon_glamor_fini(ScreenPtr screen) { }
|
||||
static inline Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { return FALSE; }
|
||||
static inline void radeon_glamor_free_screen(int scrnIndex, int flags) { }
|
||||
|
||||
static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo) { return TRUE; }
|
||||
|
||||
static inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {}
|
||||
static inline PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap) { return pixmap; }
|
||||
|
||||
static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
|
||||
|
||||
static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; }
|
||||
|
||||
static inline void radeon_glamor_finish(ScrnInfoPtr pScrn) { }
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* RADEON_GLAMOR_H */
|
||||
970
src/radeon_glamor_wrappers.c
Normal file
970
src/radeon_glamor_wrappers.c
Normal file
|
|
@ -0,0 +1,970 @@
|
|||
/*
|
||||
* Copyright © 2001 Keith Packard
|
||||
* 2010 Intel Corporation
|
||||
* 2012,2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Partly based on code Copyright © 2008 Red Hat, Inc.
|
||||
* Partly based on code Copyright © 2000 SuSE, Inc.
|
||||
*
|
||||
* Partly based on code that is Copyright © The XFree86 Project Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that
|
||||
* copyright notice and this permission notice appear in supporting
|
||||
* documentation, and that the name of the opyright holders not be used in
|
||||
* advertising or publicity pertaining to distribution of the software without
|
||||
* specific, written prior permission. The copyright holders make no
|
||||
* representations about the suitability of this software for any purpose. It
|
||||
* is provided "as is" without express or implied warranty.
|
||||
*
|
||||
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#include <config.h>
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
|
||||
#include <fb.h>
|
||||
#include <fbpict.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_bo_helper.h"
|
||||
#include "radeon_glamor.h"
|
||||
|
||||
|
||||
/* Are there any outstanding GPU operations for this pixmap? */
|
||||
static Bool
|
||||
radeon_glamor_gpu_pending(uint_fast32_t gpu_synced, uint_fast32_t gpu_access)
|
||||
{
|
||||
return (int_fast32_t)(gpu_access - gpu_synced) > 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Pixmap CPU access wrappers
|
||||
*/
|
||||
|
||||
static Bool
|
||||
radeon_glamor_prepare_access_cpu(ScrnInfoPtr scrn, RADEONInfoPtr info,
|
||||
PixmapPtr pixmap, struct radeon_pixmap *priv,
|
||||
Bool need_sync)
|
||||
{
|
||||
struct radeon_buffer *bo = priv->bo;
|
||||
int ret;
|
||||
|
||||
if (!pixmap->devPrivate.ptr) {
|
||||
/* When falling back to swrast, flush all pending operations */
|
||||
if (need_sync) {
|
||||
glamor_block_handler(scrn->pScreen);
|
||||
info->gpu_flushed++;
|
||||
}
|
||||
|
||||
ret = radeon_bo_map(bo->bo.radeon, 1);
|
||||
if (ret) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"%s: bo map (tiling_flags %d) failed: %s\n",
|
||||
__FUNCTION__,
|
||||
priv->tiling_flags,
|
||||
strerror(-ret));
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pixmap->devPrivate.ptr = bo->bo.radeon->ptr;
|
||||
} else if (need_sync)
|
||||
radeon_finish(scrn, bo);
|
||||
|
||||
info->gpu_synced = info->gpu_flushed;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_glamor_prepare_access_cpu_ro(ScrnInfoPtr scrn, PixmapPtr pixmap,
|
||||
struct radeon_pixmap *priv)
|
||||
{
|
||||
RADEONInfoPtr info;
|
||||
Bool need_sync;
|
||||
|
||||
if (!priv)
|
||||
return TRUE;
|
||||
|
||||
info = RADEONPTR(scrn);
|
||||
need_sync = radeon_glamor_gpu_pending(info->gpu_synced, priv->gpu_write);
|
||||
return radeon_glamor_prepare_access_cpu(scrn, RADEONPTR(scrn), pixmap,
|
||||
priv, need_sync);
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_glamor_prepare_access_cpu_rw(ScrnInfoPtr scrn, PixmapPtr pixmap,
|
||||
struct radeon_pixmap *priv)
|
||||
{
|
||||
RADEONInfoPtr info;
|
||||
uint_fast32_t gpu_synced;
|
||||
Bool need_sync;
|
||||
|
||||
if (!priv)
|
||||
return TRUE;
|
||||
|
||||
info = RADEONPTR(scrn);
|
||||
gpu_synced = info->gpu_synced;
|
||||
need_sync = radeon_glamor_gpu_pending(gpu_synced, priv->gpu_write) |
|
||||
radeon_glamor_gpu_pending(gpu_synced, priv->gpu_read);
|
||||
return radeon_glamor_prepare_access_cpu(scrn, info, pixmap, priv,
|
||||
need_sync);
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_finish_access_cpu(PixmapPtr pixmap)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
/*
|
||||
* Pixmap GPU access wrappers
|
||||
*/
|
||||
|
||||
static Bool
|
||||
radeon_glamor_prepare_access_gpu(struct radeon_pixmap *priv)
|
||||
{
|
||||
return !!priv;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_finish_access_gpu_ro(RADEONInfoPtr info,
|
||||
struct radeon_pixmap *priv)
|
||||
{
|
||||
priv->gpu_read = info->gpu_flushed + 1;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_finish_access_gpu_rw(RADEONInfoPtr info,
|
||||
struct radeon_pixmap *priv)
|
||||
{
|
||||
priv->gpu_write = priv->gpu_read = info->gpu_flushed + 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* GC CPU access wrappers
|
||||
*/
|
||||
|
||||
static Bool
|
||||
radeon_glamor_prepare_access_gc(ScrnInfoPtr scrn, GCPtr pGC)
|
||||
{
|
||||
struct radeon_pixmap *priv;
|
||||
|
||||
if (pGC->stipple) {
|
||||
priv = radeon_get_pixmap_private(pGC->stipple);
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, pGC->stipple, priv))
|
||||
return FALSE;
|
||||
}
|
||||
if (pGC->fillStyle == FillTiled) {
|
||||
priv = radeon_get_pixmap_private(pGC->tile.pixmap);
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, pGC->tile.pixmap,
|
||||
priv)) {
|
||||
if (pGC->stipple)
|
||||
radeon_glamor_finish_access_cpu(pGC->stipple);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_finish_access_gc(GCPtr pGC)
|
||||
{
|
||||
if (pGC->fillStyle == FillTiled)
|
||||
radeon_glamor_finish_access_cpu(pGC->tile.pixmap);
|
||||
if (pGC->stipple)
|
||||
radeon_glamor_finish_access_cpu(pGC->stipple);
|
||||
}
|
||||
|
||||
/*
|
||||
* Picture CPU access wrappers
|
||||
*/
|
||||
|
||||
static void
|
||||
radeon_glamor_picture_finish_access_cpu(PicturePtr picture)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_glamor_picture_prepare_access_cpu_ro(ScrnInfoPtr scrn,
|
||||
PicturePtr picture)
|
||||
{
|
||||
PixmapPtr pixmap;
|
||||
struct radeon_pixmap *priv;
|
||||
|
||||
if (!picture->pDrawable)
|
||||
return TRUE;
|
||||
|
||||
pixmap = get_drawable_pixmap(picture->pDrawable);
|
||||
priv = radeon_get_pixmap_private(pixmap);
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv))
|
||||
return FALSE;
|
||||
|
||||
if (picture->alphaMap) {
|
||||
pixmap = get_drawable_pixmap(picture->alphaMap->pDrawable);
|
||||
priv = radeon_get_pixmap_private(pixmap);
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) {
|
||||
radeon_glamor_picture_finish_access_cpu(picture);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_glamor_picture_prepare_access_cpu_rw(ScrnInfoPtr scrn,
|
||||
PicturePtr picture)
|
||||
{
|
||||
PixmapPtr pixmap;
|
||||
struct radeon_pixmap *priv;
|
||||
|
||||
pixmap = get_drawable_pixmap(picture->pDrawable);
|
||||
priv = radeon_get_pixmap_private(pixmap);
|
||||
if (!radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv))
|
||||
return FALSE;
|
||||
|
||||
if (picture->alphaMap) {
|
||||
pixmap = get_drawable_pixmap(picture->alphaMap->pDrawable);
|
||||
priv = radeon_get_pixmap_private(pixmap);
|
||||
if (!radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
radeon_glamor_picture_finish_access_cpu(picture);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* GC rendering wrappers
|
||||
*/
|
||||
|
||||
static void
|
||||
radeon_glamor_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int nspans,
|
||||
DDXPointPtr ppt, int *pwidth, int fSorted)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbFillSpans(pDrawable, pGC, nspans, ppt, pwidth,
|
||||
fSorted);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_set_spans(DrawablePtr pDrawable, GCPtr pGC, char *psrc,
|
||||
DDXPointPtr ppt, int *pwidth, int nspans, int fSorted)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
fbSetSpans(pDrawable, pGC, psrc, ppt, pwidth, nspans, fSorted);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_put_image(DrawablePtr pDrawable, GCPtr pGC, int depth,
|
||||
int x, int y, int w, int h, int leftPad, int format,
|
||||
char *bits)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
fbPutImage(pDrawable, pGC, depth, x, y, w, h, leftPad, format,
|
||||
bits);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static RegionPtr
|
||||
radeon_glamor_copy_plane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC,
|
||||
int srcx, int srcy, int w, int h, int dstx, int dsty,
|
||||
unsigned long bitPlane)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pScreen);
|
||||
PixmapPtr dst_pix = get_drawable_pixmap(pDst);
|
||||
struct radeon_pixmap *dst_priv = radeon_get_pixmap_private(dst_pix);
|
||||
RegionPtr ret = NULL;
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, dst_pix, dst_priv)) {
|
||||
PixmapPtr src_pix = get_drawable_pixmap(pSrc);
|
||||
struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pix);
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, src_pix, src_priv)) {
|
||||
ret =
|
||||
fbCopyPlane(pSrc, pDst, pGC, srcx, srcy, w, h, dstx,
|
||||
dsty, bitPlane);
|
||||
radeon_glamor_finish_access_cpu(src_pix);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(dst_pix);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static RegionPtr
|
||||
radeon_glamor_copy_plane_nodstbo(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC,
|
||||
int srcx, int srcy, int w, int h,
|
||||
int dstx, int dsty, unsigned long bitPlane)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pScreen);
|
||||
PixmapPtr src_pix = get_drawable_pixmap(pSrc);
|
||||
struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pix);
|
||||
RegionPtr ret = NULL;
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, src_pix, src_priv)) {
|
||||
ret = fbCopyPlane(pSrc, pDst, pGC, srcx, srcy, w, h,
|
||||
dstx, dsty, bitPlane);
|
||||
radeon_glamor_finish_access_cpu(src_pix);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_poly_point(DrawablePtr pDrawable, GCPtr pGC, int mode, int npt,
|
||||
DDXPointPtr pptInit)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
fbPolyPoint(pDrawable, pGC, mode, npt, pptInit);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_poly_lines(DrawablePtr pDrawable, GCPtr pGC,
|
||||
int mode, int npt, DDXPointPtr ppt)
|
||||
{
|
||||
if (pGC->lineWidth == 0) {
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbPolyLine(pDrawable, pGC, mode, npt, ppt);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
return;
|
||||
}
|
||||
/* fb calls mi functions in the lineWidth != 0 case. */
|
||||
fbPolyLine(pDrawable, pGC, mode, npt, ppt);
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_poly_segment(DrawablePtr pDrawable, GCPtr pGC,
|
||||
int nsegInit, xSegment *pSegInit)
|
||||
{
|
||||
if (pGC->lineWidth == 0) {
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbPolySegment(pDrawable, pGC, nsegInit,
|
||||
pSegInit);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
return;
|
||||
}
|
||||
/* fb calls mi functions in the lineWidth != 0 case. */
|
||||
fbPolySegment(pDrawable, pGC, nsegInit, pSegInit);
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_poly_fill_rect(DrawablePtr pDrawable, GCPtr pGC,
|
||||
int nrect, xRectangle *prect)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if ((info->accel_state->force || (priv && !priv->bo)) &&
|
||||
radeon_glamor_prepare_access_gpu(priv)) {
|
||||
info->glamor.SavedPolyFillRect(pDrawable, pGC, nrect, prect);
|
||||
radeon_glamor_finish_access_gpu_rw(info, priv);
|
||||
return;
|
||||
}
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbPolyFillRect(pDrawable, pGC, nrect, prect);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_image_glyph_blt(DrawablePtr pDrawable, GCPtr pGC,
|
||||
int x, int y, unsigned int nglyph,
|
||||
CharInfoPtr *ppci, void *pglyphBase)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbImageGlyphBlt(pDrawable, pGC, x, y, nglyph, ppci,
|
||||
pglyphBase);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_poly_glyph_blt(DrawablePtr pDrawable, GCPtr pGC,
|
||||
int x, int y, unsigned int nglyph,
|
||||
CharInfoPtr *ppci, void *pglyphBase)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbPolyGlyphBlt(pDrawable, pGC, x, y, nglyph, ppci,
|
||||
pglyphBase);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_push_pixels(GCPtr pGC, PixmapPtr pBitmap,
|
||||
DrawablePtr pDrawable, int w, int h, int x, int y)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
priv = radeon_get_pixmap_private(pBitmap);
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, pBitmap, priv)) {
|
||||
if (radeon_glamor_prepare_access_gc(scrn, pGC)) {
|
||||
fbPushPixels(pGC, pBitmap, pDrawable, w, h, x,
|
||||
y);
|
||||
radeon_glamor_finish_access_gc(pGC);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pBitmap);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_push_pixels_nodstbo(GCPtr pGC, PixmapPtr pBitmap,
|
||||
DrawablePtr pDrawable, int w, int h,
|
||||
int x, int y)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pBitmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, pBitmap, priv)) {
|
||||
fbPushPixels(pGC, pBitmap, pDrawable, w, h, x, y);
|
||||
radeon_glamor_finish_access_cpu(pBitmap);
|
||||
}
|
||||
}
|
||||
|
||||
static RegionPtr
|
||||
radeon_glamor_copy_area(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable,
|
||||
GCPtr pGC, int srcx, int srcy, int width, int height,
|
||||
int dstx, int dsty)
|
||||
{
|
||||
ScreenPtr screen = pDstDrawable->pScreen;
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
PixmapPtr src_pixmap = get_drawable_pixmap(pSrcDrawable);
|
||||
PixmapPtr dst_pixmap = get_drawable_pixmap(pDstDrawable);
|
||||
struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pixmap);
|
||||
struct radeon_pixmap *dst_priv = radeon_get_pixmap_private(dst_pixmap);
|
||||
RegionPtr ret = NULL;
|
||||
|
||||
if (info->accel_state->force || (src_priv && !src_priv->bo) ||
|
||||
(dst_priv && !dst_priv->bo)) {
|
||||
if (!radeon_glamor_prepare_access_gpu(dst_priv))
|
||||
goto fallback;
|
||||
if (src_priv != dst_priv &&
|
||||
!radeon_glamor_prepare_access_gpu(src_priv))
|
||||
goto fallback;
|
||||
|
||||
ret = info->glamor.SavedCopyArea(pSrcDrawable, pDstDrawable,
|
||||
pGC, srcx, srcy,
|
||||
width, height, dstx, dsty);
|
||||
radeon_glamor_finish_access_gpu_rw(info, dst_priv);
|
||||
if (src_priv != dst_priv)
|
||||
radeon_glamor_finish_access_gpu_ro(info, src_priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
fallback:
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, dst_pixmap, dst_priv)) {
|
||||
if (pSrcDrawable == pDstDrawable ||
|
||||
radeon_glamor_prepare_access_cpu_ro(scrn, src_pixmap,
|
||||
src_priv)) {
|
||||
ret = fbCopyArea(pSrcDrawable, pDstDrawable, pGC,
|
||||
srcx, srcy, width, height, dstx, dsty);
|
||||
if (pSrcDrawable != pDstDrawable)
|
||||
radeon_glamor_finish_access_cpu(src_pixmap);
|
||||
}
|
||||
radeon_glamor_finish_access_cpu(dst_pixmap);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static RegionPtr
|
||||
radeon_glamor_copy_area_nodstbo(DrawablePtr pSrcDrawable,
|
||||
DrawablePtr pDstDrawable, GCPtr pGC,
|
||||
int srcx, int srcy, int width, int height,
|
||||
int dstx, int dsty)
|
||||
{
|
||||
ScreenPtr screen = pDstDrawable->pScreen;
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
PixmapPtr src_pixmap = get_drawable_pixmap(pSrcDrawable);
|
||||
PixmapPtr dst_pixmap = get_drawable_pixmap(pDstDrawable);
|
||||
struct radeon_pixmap *src_priv;
|
||||
RegionPtr ret = NULL;
|
||||
|
||||
if (src_pixmap != dst_pixmap) {
|
||||
src_priv = radeon_get_pixmap_private(src_pixmap);
|
||||
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, src_pixmap,
|
||||
src_priv))
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fbCopyArea(pSrcDrawable, pDstDrawable, pGC, srcx, srcy,
|
||||
width, height, dstx, dsty);
|
||||
|
||||
if (src_pixmap != dst_pixmap)
|
||||
radeon_glamor_finish_access_cpu(src_pixmap);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const GCOps radeon_glamor_ops = {
|
||||
radeon_glamor_fill_spans,
|
||||
radeon_glamor_set_spans,
|
||||
radeon_glamor_put_image,
|
||||
radeon_glamor_copy_area,
|
||||
radeon_glamor_copy_plane,
|
||||
radeon_glamor_poly_point,
|
||||
radeon_glamor_poly_lines,
|
||||
radeon_glamor_poly_segment,
|
||||
miPolyRectangle,
|
||||
miPolyArc,
|
||||
miFillPolygon,
|
||||
radeon_glamor_poly_fill_rect,
|
||||
miPolyFillArc,
|
||||
miPolyText8,
|
||||
miPolyText16,
|
||||
miImageText8,
|
||||
miImageText16,
|
||||
radeon_glamor_image_glyph_blt,
|
||||
radeon_glamor_poly_glyph_blt,
|
||||
radeon_glamor_push_pixels,
|
||||
};
|
||||
|
||||
static GCOps radeon_glamor_nodstbo_ops;
|
||||
|
||||
/**
|
||||
* radeon_glamor_validate_gc() sets the ops to our implementations, which may be
|
||||
* accelerated or may sync the card and fall back to fb.
|
||||
*/
|
||||
static void
|
||||
radeon_glamor_validate_gc(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pGC->pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
glamor_validate_gc(pGC, changes, pDrawable);
|
||||
info->glamor.SavedCopyArea = pGC->ops->CopyArea;
|
||||
info->glamor.SavedPolyFillRect = pGC->ops->PolyFillRect;
|
||||
|
||||
if (radeon_get_pixmap_private(get_drawable_pixmap(pDrawable)) ||
|
||||
(pGC->stipple && radeon_get_pixmap_private(pGC->stipple)) ||
|
||||
(pGC->fillStyle == FillTiled &&
|
||||
radeon_get_pixmap_private(pGC->tile.pixmap)))
|
||||
pGC->ops = (GCOps *)&radeon_glamor_ops;
|
||||
else
|
||||
pGC->ops = &radeon_glamor_nodstbo_ops;
|
||||
}
|
||||
|
||||
static GCFuncs glamorGCFuncs = {
|
||||
radeon_glamor_validate_gc,
|
||||
miChangeGC,
|
||||
miCopyGC,
|
||||
miDestroyGC,
|
||||
miChangeClip,
|
||||
miDestroyClip,
|
||||
miCopyClip
|
||||
};
|
||||
|
||||
/**
|
||||
* radeon_glamor_create_gc makes a new GC and hooks up its funcs handler, so that
|
||||
* radeon_glamor_validate_gc() will get called.
|
||||
*/
|
||||
static int
|
||||
radeon_glamor_create_gc(GCPtr pGC)
|
||||
{
|
||||
static Bool nodstbo_ops_initialized;
|
||||
|
||||
if (!fbCreateGC(pGC))
|
||||
return FALSE;
|
||||
|
||||
if (!nodstbo_ops_initialized) {
|
||||
radeon_glamor_nodstbo_ops = radeon_glamor_ops;
|
||||
|
||||
radeon_glamor_nodstbo_ops.FillSpans = pGC->ops->FillSpans;
|
||||
radeon_glamor_nodstbo_ops.SetSpans = pGC->ops->SetSpans;
|
||||
radeon_glamor_nodstbo_ops.PutImage = pGC->ops->PutImage;
|
||||
radeon_glamor_nodstbo_ops.CopyArea = radeon_glamor_copy_area_nodstbo;
|
||||
radeon_glamor_nodstbo_ops.CopyPlane = radeon_glamor_copy_plane_nodstbo;
|
||||
radeon_glamor_nodstbo_ops.PolyPoint = pGC->ops->PolyPoint;
|
||||
radeon_glamor_nodstbo_ops.Polylines = pGC->ops->Polylines;
|
||||
radeon_glamor_nodstbo_ops.PolySegment = pGC->ops->PolySegment;
|
||||
radeon_glamor_nodstbo_ops.PolyFillRect = pGC->ops->PolyFillRect;
|
||||
radeon_glamor_nodstbo_ops.ImageGlyphBlt = pGC->ops->ImageGlyphBlt;
|
||||
radeon_glamor_nodstbo_ops.PolyGlyphBlt = pGC->ops->PolyGlyphBlt;
|
||||
radeon_glamor_nodstbo_ops.PushPixels = radeon_glamor_push_pixels_nodstbo;
|
||||
|
||||
nodstbo_ops_initialized = TRUE;
|
||||
}
|
||||
|
||||
pGC->funcs = &glamorGCFuncs;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Screen rendering wrappers
|
||||
*/
|
||||
|
||||
static RegionPtr
|
||||
radeon_glamor_bitmap_to_region(PixmapPtr pPix)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pPix->drawable.pScreen);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pPix);
|
||||
RegionPtr ret;
|
||||
|
||||
if (!radeon_glamor_prepare_access_cpu_ro(scrn, pPix, priv))
|
||||
return NULL;
|
||||
ret = fbPixmapToRegion(pPix);
|
||||
radeon_glamor_finish_access_cpu(pPix);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_copy_window(WindowPtr pWin, DDXPointRec ptOldOrg,
|
||||
RegionPtr prgnSrc)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pWin->drawable.pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(&pWin->drawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) {
|
||||
fbCopyWindow(pWin, ptOldOrg, prgnSrc);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_get_image(DrawablePtr pDrawable, int x, int y, int w, int h,
|
||||
unsigned int format, unsigned long planeMask, char *d)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) {
|
||||
fbGetImage(pDrawable, x, y, w, h, format, planeMask, d);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_get_spans(DrawablePtr pDrawable, int wMax, DDXPointPtr ppt,
|
||||
int *pwidth, int nspans, char *pdstStart)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen);
|
||||
PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) {
|
||||
fbGetSpans(pDrawable, wMax, ppt, pwidth, nspans, pdstStart);
|
||||
radeon_glamor_finish_access_cpu(pixmap);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Picture screen rendering wrappers
|
||||
*/
|
||||
|
||||
#ifdef RENDER
|
||||
|
||||
static void
|
||||
radeon_glamor_composite(CARD8 op,
|
||||
PicturePtr pSrc,
|
||||
PicturePtr pMask,
|
||||
PicturePtr pDst,
|
||||
INT16 xSrc, INT16 ySrc,
|
||||
INT16 xMask, INT16 yMask,
|
||||
INT16 xDst, INT16 yDst,
|
||||
CARD16 width, CARD16 height)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pDrawable->pScreen);
|
||||
RADEONInfoPtr info;
|
||||
PixmapPtr pixmap;
|
||||
struct radeon_pixmap *dst_priv, *src_priv = NULL, *mask_priv = NULL;
|
||||
Bool gpu_done = FALSE;
|
||||
|
||||
if (pDst->alphaMap || pSrc->alphaMap || (pMask && pMask->alphaMap))
|
||||
goto fallback;
|
||||
|
||||
pixmap = get_drawable_pixmap(pDst->pDrawable);
|
||||
if (&pixmap->drawable != pDst->pDrawable ||
|
||||
pixmap->usage_hint != RADEON_CREATE_PIXMAP_SCANOUT)
|
||||
goto fallback;
|
||||
|
||||
dst_priv = radeon_get_pixmap_private(pixmap);
|
||||
if (!radeon_glamor_prepare_access_gpu(dst_priv))
|
||||
goto fallback;
|
||||
|
||||
info = RADEONPTR(scrn);
|
||||
if (!pSrc->pDrawable ||
|
||||
((pixmap = get_drawable_pixmap(pSrc->pDrawable)) &&
|
||||
(src_priv = radeon_get_pixmap_private(pixmap)) &&
|
||||
radeon_glamor_prepare_access_gpu(src_priv))) {
|
||||
if (!pMask || !pMask->pDrawable ||
|
||||
((pixmap = get_drawable_pixmap(pMask->pDrawable)) &&
|
||||
(mask_priv = radeon_get_pixmap_private(pixmap)) &&
|
||||
radeon_glamor_prepare_access_gpu(mask_priv))) {
|
||||
info->glamor.SavedComposite(op, pSrc, pMask, pDst,
|
||||
xSrc, ySrc, xMask, yMask,
|
||||
xDst, yDst, width, height);
|
||||
gpu_done = TRUE;
|
||||
|
||||
if (mask_priv)
|
||||
radeon_glamor_finish_access_gpu_ro(info, mask_priv);
|
||||
}
|
||||
|
||||
if (src_priv)
|
||||
radeon_glamor_finish_access_gpu_ro(info, src_priv);
|
||||
}
|
||||
radeon_glamor_finish_access_gpu_rw(info, dst_priv);
|
||||
|
||||
if (gpu_done)
|
||||
return;
|
||||
|
||||
fallback:
|
||||
if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, pDst)) {
|
||||
if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, pSrc)) {
|
||||
if (!pMask ||
|
||||
radeon_glamor_picture_prepare_access_cpu_ro(scrn, pMask)) {
|
||||
fbComposite(op, pSrc, pMask, pDst,
|
||||
xSrc, ySrc,
|
||||
xMask, yMask,
|
||||
xDst, yDst,
|
||||
width, height);
|
||||
if (pMask)
|
||||
radeon_glamor_picture_finish_access_cpu(pMask);
|
||||
}
|
||||
radeon_glamor_picture_finish_access_cpu(pSrc);
|
||||
}
|
||||
radeon_glamor_picture_finish_access_cpu(pDst);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_add_traps(PicturePtr pPicture,
|
||||
INT16 x_off, INT16 y_off, int ntrap, xTrap *traps)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(pPicture->pDrawable->pScreen);
|
||||
|
||||
if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, pPicture)) {
|
||||
fbAddTraps(pPicture, x_off, y_off, ntrap, traps);
|
||||
radeon_glamor_picture_finish_access_cpu(pPicture);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_glyphs(CARD8 op,
|
||||
PicturePtr src,
|
||||
PicturePtr dst,
|
||||
PictFormatPtr maskFormat,
|
||||
INT16 xSrc,
|
||||
INT16 ySrc, int nlist, GlyphListPtr list, GlyphPtr *glyphs)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen);
|
||||
|
||||
if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) {
|
||||
if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) {
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
info->glamor.SavedGlyphs(op, src, dst, maskFormat, xSrc,
|
||||
ySrc, nlist, list, glyphs);
|
||||
radeon_glamor_picture_finish_access_cpu(src);
|
||||
}
|
||||
radeon_glamor_picture_finish_access_cpu(dst);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_trapezoids(CARD8 op, PicturePtr src, PicturePtr dst,
|
||||
PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc,
|
||||
int ntrap, xTrapezoid *traps)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen);
|
||||
|
||||
if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) {
|
||||
if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) {
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
info->glamor.SavedTrapezoids(op, src, dst, maskFormat,
|
||||
xSrc, ySrc, ntrap, traps);
|
||||
radeon_glamor_picture_finish_access_cpu(src);
|
||||
}
|
||||
radeon_glamor_picture_finish_access_cpu(dst);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_glamor_triangles(CARD8 op, PicturePtr src, PicturePtr dst,
|
||||
PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc,
|
||||
int ntri, xTriangle *tri)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen);
|
||||
|
||||
if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) {
|
||||
if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) {
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
|
||||
info->glamor.SavedTriangles(op, src, dst, maskFormat,
|
||||
xSrc, ySrc, ntri, tri);
|
||||
radeon_glamor_picture_finish_access_cpu(src);
|
||||
}
|
||||
radeon_glamor_picture_finish_access_cpu(dst);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* RENDER */
|
||||
|
||||
|
||||
/**
|
||||
* radeon_glamor_close_screen() unwraps its wrapped screen functions and tears
|
||||
* down our screen private, before calling down to the next CloseScreen.
|
||||
*/
|
||||
static Bool
|
||||
radeon_glamor_close_screen(ScreenPtr pScreen)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pScreen));
|
||||
#ifdef RENDER
|
||||
PictureScreenPtr ps = GetPictureScreenIfSet(pScreen);
|
||||
#endif
|
||||
|
||||
pScreen->CreateGC = info->glamor.SavedCreateGC;
|
||||
pScreen->CloseScreen = info->glamor.SavedCloseScreen;
|
||||
pScreen->GetImage = info->glamor.SavedGetImage;
|
||||
pScreen->GetSpans = info->glamor.SavedGetSpans;
|
||||
pScreen->CopyWindow = info->glamor.SavedCopyWindow;
|
||||
pScreen->ChangeWindowAttributes =
|
||||
info->glamor.SavedChangeWindowAttributes;
|
||||
pScreen->BitmapToRegion = info->glamor.SavedBitmapToRegion;
|
||||
#ifdef RENDER
|
||||
if (ps) {
|
||||
ps->Composite = info->glamor.SavedComposite;
|
||||
ps->Glyphs = info->glamor.SavedGlyphs;
|
||||
ps->UnrealizeGlyph = info->glamor.SavedUnrealizeGlyph;
|
||||
ps->Trapezoids = info->glamor.SavedTrapezoids;
|
||||
ps->AddTraps = info->glamor.SavedAddTraps;
|
||||
ps->Triangles = info->glamor.SavedTriangles;
|
||||
|
||||
ps->UnrealizeGlyph = info->glamor.SavedUnrealizeGlyph;
|
||||
}
|
||||
#endif
|
||||
|
||||
return pScreen->CloseScreen(pScreen);
|
||||
}
|
||||
|
||||
/**
|
||||
* @param screen screen being initialized
|
||||
*/
|
||||
void
|
||||
radeon_glamor_screen_init(ScreenPtr screen)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen));
|
||||
|
||||
/*
|
||||
* Replace various fb screen functions
|
||||
*/
|
||||
info->glamor.SavedCloseScreen = screen->CloseScreen;
|
||||
screen->CloseScreen = radeon_glamor_close_screen;
|
||||
|
||||
info->glamor.SavedCreateGC = screen->CreateGC;
|
||||
screen->CreateGC = radeon_glamor_create_gc;
|
||||
|
||||
info->glamor.SavedGetImage = screen->GetImage;
|
||||
screen->GetImage = radeon_glamor_get_image;
|
||||
|
||||
info->glamor.SavedGetSpans = screen->GetSpans;
|
||||
screen->GetSpans = radeon_glamor_get_spans;
|
||||
|
||||
info->glamor.SavedCopyWindow = screen->CopyWindow;
|
||||
screen->CopyWindow = radeon_glamor_copy_window;
|
||||
|
||||
info->glamor.SavedBitmapToRegion = screen->BitmapToRegion;
|
||||
screen->BitmapToRegion = radeon_glamor_bitmap_to_region;
|
||||
|
||||
#ifdef RENDER
|
||||
{
|
||||
PictureScreenPtr ps = GetPictureScreenIfSet(screen);
|
||||
if (ps) {
|
||||
info->glamor.SavedComposite = ps->Composite;
|
||||
ps->Composite = radeon_glamor_composite;
|
||||
|
||||
info->glamor.SavedUnrealizeGlyph = ps->UnrealizeGlyph;
|
||||
|
||||
ps->Glyphs = radeon_glamor_glyphs;
|
||||
ps->Triangles = radeon_glamor_triangles;
|
||||
ps->Trapezoids = radeon_glamor_trapezoids;
|
||||
|
||||
info->glamor.SavedAddTraps = ps->AddTraps;
|
||||
ps->AddTraps = radeon_glamor_add_traps;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* USE_GLAMOR */
|
||||
2905
src/radeon_kms.c
Normal file
2905
src/radeon_kms.c
Normal file
File diff suppressed because it is too large
Load diff
75
src/radeon_misc.c
Normal file
75
src/radeon_misc.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_version.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
/* Module loader interface for subsidiary driver module */
|
||||
|
||||
static XF86ModuleVersionInfo RADEONVersionRec =
|
||||
{
|
||||
RADEON_DRIVER_NAME,
|
||||
MODULEVENDORSTRING,
|
||||
MODINFOSTRING1,
|
||||
MODINFOSTRING2,
|
||||
XORG_VERSION_CURRENT,
|
||||
RADEON_VERSION_MAJOR, RADEON_VERSION_MINOR, RADEON_VERSION_PATCH,
|
||||
ABI_CLASS_VIDEODRV,
|
||||
ABI_VIDEODRV_VERSION,
|
||||
MOD_CLASS_VIDEODRV,
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
/*
|
||||
* RADEONSetup --
|
||||
*
|
||||
* This function is called every time the module is loaded.
|
||||
*/
|
||||
static void *
|
||||
RADEONSetup
|
||||
(
|
||||
void *Module,
|
||||
void *Options,
|
||||
int *ErrorMajor,
|
||||
int *ErrorMinor
|
||||
)
|
||||
{
|
||||
static Bool Inited = FALSE;
|
||||
|
||||
if (!Inited) {
|
||||
Inited = TRUE;
|
||||
xf86AddDriver(&RADEON, Module, HaveDriverFuncs);
|
||||
}
|
||||
|
||||
return (void*)TRUE;
|
||||
}
|
||||
|
||||
/* The following record must be called radeonModuleData */
|
||||
_X_EXPORT XF86ModuleData radeonModuleData =
|
||||
{
|
||||
&RADEONVersionRec,
|
||||
RADEONSetup,
|
||||
NULL
|
||||
};
|
||||
704
src/radeon_pci_chipset_gen.h
Normal file
704
src/radeon_pci_chipset_gen.h
Normal file
|
|
@ -0,0 +1,704 @@
|
|||
/* This file is autogenerated please do not edit */
|
||||
static PciChipsets RADEONPciChipsets[] = {
|
||||
{ PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3151, PCI_CHIP_RV380_3151, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3155, PCI_CHIP_RV380_3155, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R420_JT, PCI_CHIP_R420_JT, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R481_4B48, PCI_CHIP_R481_4B48, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_4C6E, PCI_CHIP_RV280_4C6E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7200, PCI_CHIP_RV515_7200, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7210, PCI_CHIP_RV515_7210, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV515_7211, PCI_CHIP_RV515_7211, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS600_793F, PCI_CHIP_RS600_793F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS600_7941, PCI_CHIP_RS600_7941, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS600_7942, PCI_CHIP_RS600_7942, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9441, PCI_CHIP_RV770_9441, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9443, PCI_CHIP_RV770_9443, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9444, PCI_CHIP_RV770_9444, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9446, PCI_CHIP_RV770_9446, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_944A, PCI_CHIP_RV770_944A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_944B, PCI_CHIP_RV770_944B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_944C, PCI_CHIP_RV770_944C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_944E, PCI_CHIP_RV770_944E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9450, PCI_CHIP_RV770_9450, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9452, PCI_CHIP_RV770_9452, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_945E, PCI_CHIP_RV770_945E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV790_9460, PCI_CHIP_RV790_9460, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV790_9462, PCI_CHIP_RV790_9462, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV770_947B, PCI_CHIP_RV770_947B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9480, PCI_CHIP_RV730_9480, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9488, PCI_CHIP_RV730_9488, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9489, PCI_CHIP_RV730_9489, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_948A, PCI_CHIP_RV730_948A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9491, PCI_CHIP_RV730_9491, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9495, PCI_CHIP_RV730_9495, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV730_949F, PCI_CHIP_RV730_949F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94A0, PCI_CHIP_RV740_94A0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94A1, PCI_CHIP_RV740_94A1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94A3, PCI_CHIP_RV740_94A3, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94B1, PCI_CHIP_RV740_94B1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94B3, PCI_CHIP_RV740_94B3, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94B4, PCI_CHIP_RV740_94B4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94B5, PCI_CHIP_RV740_94B5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV740_94B9, PCI_CHIP_RV740_94B9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV610_94CD, PCI_CHIP_RV610_94CD, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9504, PCI_CHIP_RV670_9504, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9506, PCI_CHIP_RV670_9506, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9508, PCI_CHIP_RV670_9508, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9509, PCI_CHIP_RV670_9509, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9517, PCI_CHIP_RV670_9517, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV670_9519, PCI_CHIP_RV670_9519, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9542, PCI_CHIP_RV710_9542, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9555, PCI_CHIP_RV710_9555, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_9557, PCI_CHIP_RV710_9557, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV710_955F, PCI_CHIP_RV710_955F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV630_958F, PCI_CHIP_RV630_958F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C6, PCI_CHIP_RV620_95C6, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95C9, PCI_CHIP_RV620_95C9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95CC, PCI_CHIP_RV620_95CC, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9590, PCI_CHIP_RV635_9590, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9596, PCI_CHIP_RV635_9596, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9597, PCI_CHIP_RV635_9597, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9598, PCI_CHIP_RV635_9598, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9599, PCI_CHIP_RV635_9599, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9591, PCI_CHIP_RV635_9591, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9593, PCI_CHIP_RV635_9593, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_9595, PCI_CHIP_RV635_9595, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RV635_959B, PCI_CHIP_RV635_959B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9610, PCI_CHIP_RS780_9610, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9615, PCI_CHIP_RS780_9615, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS780_9616, PCI_CHIP_RS780_9616, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9640, PCI_CHIP_SUMO_9640, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9641, PCI_CHIP_SUMO_9641, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9642, PCI_CHIP_SUMO2_9642, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9643, PCI_CHIP_SUMO2_9643, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9644, PCI_CHIP_SUMO2_9644, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9645, PCI_CHIP_SUMO2_9645, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9649, PCI_CHIP_SUMO2_9649, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964E, PCI_CHIP_SUMO_964E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964F, PCI_CHIP_SUMO_964F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9710, PCI_CHIP_RS880_9710, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9711, PCI_CHIP_RS880_9711, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_RS880_9715, PCI_CHIP_RS880_9715, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9802, PCI_CHIP_PALM_9802, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9803, PCI_CHIP_PALM_9803, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9804, PCI_CHIP_PALM_9804, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9805, PCI_CHIP_PALM_9805, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9806, PCI_CHIP_PALM_9806, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9807, PCI_CHIP_PALM_9807, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9808, PCI_CHIP_PALM_9808, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_9809, PCI_CHIP_PALM_9809, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PALM_980A, PCI_CHIP_PALM_980A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_688A, PCI_CHIP_CYPRESS_688A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_688C, PCI_CHIP_CYPRESS_688C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_688D, PCI_CHIP_CYPRESS_688D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_6898, PCI_CHIP_CYPRESS_6898, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_6899, PCI_CHIP_CYPRESS_6899, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_689B, PCI_CHIP_CYPRESS_689B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CYPRESS_689E, PCI_CHIP_CYPRESS_689E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HEMLOCK_689C, PCI_CHIP_HEMLOCK_689C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HEMLOCK_689D, PCI_CHIP_HEMLOCK_689D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68A0, PCI_CHIP_JUNIPER_68A0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68A1, PCI_CHIP_JUNIPER_68A1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68A8, PCI_CHIP_JUNIPER_68A8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68A9, PCI_CHIP_JUNIPER_68A9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68B0, PCI_CHIP_JUNIPER_68B0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68B8, PCI_CHIP_JUNIPER_68B8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68B9, PCI_CHIP_JUNIPER_68B9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68BA, PCI_CHIP_JUNIPER_68BA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68BE, PCI_CHIP_JUNIPER_68BE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_JUNIPER_68BF, PCI_CHIP_JUNIPER_68BF, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68C0, PCI_CHIP_REDWOOD_68C0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68C1, PCI_CHIP_REDWOOD_68C1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68C7, PCI_CHIP_REDWOOD_68C7, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68C8, PCI_CHIP_REDWOOD_68C8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68C9, PCI_CHIP_REDWOOD_68C9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68D8, PCI_CHIP_REDWOOD_68D8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68D9, PCI_CHIP_REDWOOD_68D9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68DA, PCI_CHIP_REDWOOD_68DA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_REDWOOD_68DE, PCI_CHIP_REDWOOD_68DE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E0, PCI_CHIP_CEDAR_68E0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E1, PCI_CHIP_CEDAR_68E1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E4, PCI_CHIP_CEDAR_68E4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E5, PCI_CHIP_CEDAR_68E5, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E8, PCI_CHIP_CEDAR_68E8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68E9, PCI_CHIP_CEDAR_68E9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68F1, PCI_CHIP_CEDAR_68F1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68F2, PCI_CHIP_CEDAR_68F2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68FA, PCI_CHIP_CEDAR_68FA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6700, PCI_CHIP_CAYMAN_6700, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6701, PCI_CHIP_CAYMAN_6701, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6702, PCI_CHIP_CAYMAN_6702, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6703, PCI_CHIP_CAYMAN_6703, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6704, PCI_CHIP_CAYMAN_6704, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6705, PCI_CHIP_CAYMAN_6705, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6706, PCI_CHIP_CAYMAN_6706, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6707, PCI_CHIP_CAYMAN_6707, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6708, PCI_CHIP_CAYMAN_6708, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6709, PCI_CHIP_CAYMAN_6709, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6718, PCI_CHIP_CAYMAN_6718, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_6719, PCI_CHIP_CAYMAN_6719, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_671C, PCI_CHIP_CAYMAN_671C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_671D, PCI_CHIP_CAYMAN_671D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAYMAN_671F, PCI_CHIP_CAYMAN_671F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6720, PCI_CHIP_BARTS_6720, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6721, PCI_CHIP_BARTS_6721, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6722, PCI_CHIP_BARTS_6722, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6723, PCI_CHIP_BARTS_6723, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6724, PCI_CHIP_BARTS_6724, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6725, PCI_CHIP_BARTS_6725, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6726, PCI_CHIP_BARTS_6726, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6727, PCI_CHIP_BARTS_6727, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6728, PCI_CHIP_BARTS_6728, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6729, PCI_CHIP_BARTS_6729, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6738, PCI_CHIP_BARTS_6738, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_6739, PCI_CHIP_BARTS_6739, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BARTS_673E, PCI_CHIP_BARTS_673E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6740, PCI_CHIP_TURKS_6740, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6741, PCI_CHIP_TURKS_6741, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6742, PCI_CHIP_TURKS_6742, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6743, PCI_CHIP_TURKS_6743, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6744, PCI_CHIP_TURKS_6744, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6745, PCI_CHIP_TURKS_6745, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6746, PCI_CHIP_TURKS_6746, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6747, PCI_CHIP_TURKS_6747, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6748, PCI_CHIP_TURKS_6748, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6749, PCI_CHIP_TURKS_6749, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_674A, PCI_CHIP_TURKS_674A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6750, PCI_CHIP_TURKS_6750, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6751, PCI_CHIP_TURKS_6751, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6758, PCI_CHIP_TURKS_6758, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6759, PCI_CHIP_TURKS_6759, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_675B, PCI_CHIP_TURKS_675B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_675D, PCI_CHIP_TURKS_675D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_675F, PCI_CHIP_TURKS_675F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6840, PCI_CHIP_TURKS_6840, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6841, PCI_CHIP_TURKS_6841, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6842, PCI_CHIP_TURKS_6842, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6843, PCI_CHIP_TURKS_6843, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6849, PCI_CHIP_TURKS_6849, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6850, PCI_CHIP_TURKS_6850, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6858, PCI_CHIP_TURKS_6858, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TURKS_6859, PCI_CHIP_TURKS_6859, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6760, PCI_CHIP_CAICOS_6760, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6761, PCI_CHIP_CAICOS_6761, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6762, PCI_CHIP_CAICOS_6762, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6763, PCI_CHIP_CAICOS_6763, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6764, PCI_CHIP_CAICOS_6764, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6765, PCI_CHIP_CAICOS_6765, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6766, PCI_CHIP_CAICOS_6766, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6767, PCI_CHIP_CAICOS_6767, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6768, PCI_CHIP_CAICOS_6768, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6770, PCI_CHIP_CAICOS_6770, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6771, PCI_CHIP_CAICOS_6771, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6772, PCI_CHIP_CAICOS_6772, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6778, PCI_CHIP_CAICOS_6778, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_6779, PCI_CHIP_CAICOS_6779, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_CAICOS_677B, PCI_CHIP_CAICOS_677B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9900, PCI_CHIP_ARUBA_9900, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9901, PCI_CHIP_ARUBA_9901, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9903, PCI_CHIP_ARUBA_9903, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9904, PCI_CHIP_ARUBA_9904, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9905, PCI_CHIP_ARUBA_9905, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9906, PCI_CHIP_ARUBA_9906, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9907, PCI_CHIP_ARUBA_9907, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9908, PCI_CHIP_ARUBA_9908, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9909, PCI_CHIP_ARUBA_9909, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990A, PCI_CHIP_ARUBA_990A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990B, PCI_CHIP_ARUBA_990B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990C, PCI_CHIP_ARUBA_990C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990D, PCI_CHIP_ARUBA_990D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990E, PCI_CHIP_ARUBA_990E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_990F, PCI_CHIP_ARUBA_990F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9910, PCI_CHIP_ARUBA_9910, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9913, PCI_CHIP_ARUBA_9913, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9917, PCI_CHIP_ARUBA_9917, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9918, PCI_CHIP_ARUBA_9918, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9919, PCI_CHIP_ARUBA_9919, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9990, PCI_CHIP_ARUBA_9990, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9991, PCI_CHIP_ARUBA_9991, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9992, PCI_CHIP_ARUBA_9992, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9993, PCI_CHIP_ARUBA_9993, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9994, PCI_CHIP_ARUBA_9994, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9995, PCI_CHIP_ARUBA_9995, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9996, PCI_CHIP_ARUBA_9996, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9997, PCI_CHIP_ARUBA_9997, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9998, PCI_CHIP_ARUBA_9998, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_9999, PCI_CHIP_ARUBA_9999, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_999A, PCI_CHIP_ARUBA_999A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_999B, PCI_CHIP_ARUBA_999B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_999C, PCI_CHIP_ARUBA_999C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_999D, PCI_CHIP_ARUBA_999D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_99A0, PCI_CHIP_ARUBA_99A0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_99A2, PCI_CHIP_ARUBA_99A2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_ARUBA_99A4, PCI_CHIP_ARUBA_99A4, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6780, PCI_CHIP_TAHITI_6780, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6784, PCI_CHIP_TAHITI_6784, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6788, PCI_CHIP_TAHITI_6788, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_678A, PCI_CHIP_TAHITI_678A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6790, PCI_CHIP_TAHITI_6790, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6791, PCI_CHIP_TAHITI_6791, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6792, PCI_CHIP_TAHITI_6792, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6798, PCI_CHIP_TAHITI_6798, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_6799, PCI_CHIP_TAHITI_6799, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_679A, PCI_CHIP_TAHITI_679A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_679B, PCI_CHIP_TAHITI_679B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_679E, PCI_CHIP_TAHITI_679E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_TAHITI_679F, PCI_CHIP_TAHITI_679F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6800, PCI_CHIP_PITCAIRN_6800, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6801, PCI_CHIP_PITCAIRN_6801, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6802, PCI_CHIP_PITCAIRN_6802, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6806, PCI_CHIP_PITCAIRN_6806, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6808, PCI_CHIP_PITCAIRN_6808, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6809, PCI_CHIP_PITCAIRN_6809, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6810, PCI_CHIP_PITCAIRN_6810, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6811, PCI_CHIP_PITCAIRN_6811, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6816, PCI_CHIP_PITCAIRN_6816, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6817, PCI_CHIP_PITCAIRN_6817, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6818, PCI_CHIP_PITCAIRN_6818, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_6819, PCI_CHIP_PITCAIRN_6819, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_PITCAIRN_684C, PCI_CHIP_PITCAIRN_684C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6820, PCI_CHIP_VERDE_6820, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6821, PCI_CHIP_VERDE_6821, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6822, PCI_CHIP_VERDE_6822, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6823, PCI_CHIP_VERDE_6823, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6824, PCI_CHIP_VERDE_6824, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6825, PCI_CHIP_VERDE_6825, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6826, PCI_CHIP_VERDE_6826, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6827, PCI_CHIP_VERDE_6827, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6828, PCI_CHIP_VERDE_6828, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6829, PCI_CHIP_VERDE_6829, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_682A, PCI_CHIP_VERDE_682A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_682B, PCI_CHIP_VERDE_682B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_682C, PCI_CHIP_VERDE_682C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_682D, PCI_CHIP_VERDE_682D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_682F, PCI_CHIP_VERDE_682F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6830, PCI_CHIP_VERDE_6830, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6831, PCI_CHIP_VERDE_6831, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6835, PCI_CHIP_VERDE_6835, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6837, PCI_CHIP_VERDE_6837, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6838, PCI_CHIP_VERDE_6838, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_6839, PCI_CHIP_VERDE_6839, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_683B, PCI_CHIP_VERDE_683B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_683D, PCI_CHIP_VERDE_683D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_VERDE_683F, PCI_CHIP_VERDE_683F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6600, PCI_CHIP_OLAND_6600, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6601, PCI_CHIP_OLAND_6601, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6602, PCI_CHIP_OLAND_6602, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6603, PCI_CHIP_OLAND_6603, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6604, PCI_CHIP_OLAND_6604, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6605, PCI_CHIP_OLAND_6605, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6606, PCI_CHIP_OLAND_6606, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6607, PCI_CHIP_OLAND_6607, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6608, PCI_CHIP_OLAND_6608, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6610, PCI_CHIP_OLAND_6610, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6611, PCI_CHIP_OLAND_6611, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6613, PCI_CHIP_OLAND_6613, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6617, PCI_CHIP_OLAND_6617, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6620, PCI_CHIP_OLAND_6620, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6621, PCI_CHIP_OLAND_6621, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6623, PCI_CHIP_OLAND_6623, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_OLAND_6631, PCI_CHIP_OLAND_6631, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_6660, PCI_CHIP_HAINAN_6660, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_6663, PCI_CHIP_HAINAN_6663, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_6664, PCI_CHIP_HAINAN_6664, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_6665, PCI_CHIP_HAINAN_6665, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_6667, PCI_CHIP_HAINAN_6667, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAINAN_666F, PCI_CHIP_HAINAN_666F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6640, PCI_CHIP_BONAIRE_6640, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6641, PCI_CHIP_BONAIRE_6641, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6646, PCI_CHIP_BONAIRE_6646, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6647, PCI_CHIP_BONAIRE_6647, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6649, PCI_CHIP_BONAIRE_6649, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6650, PCI_CHIP_BONAIRE_6650, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6651, PCI_CHIP_BONAIRE_6651, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_6658, PCI_CHIP_BONAIRE_6658, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_665C, PCI_CHIP_BONAIRE_665C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_665D, PCI_CHIP_BONAIRE_665D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_BONAIRE_665F, PCI_CHIP_BONAIRE_665F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9830, PCI_CHIP_KABINI_9830, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9831, PCI_CHIP_KABINI_9831, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9832, PCI_CHIP_KABINI_9832, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9833, PCI_CHIP_KABINI_9833, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9834, PCI_CHIP_KABINI_9834, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9835, PCI_CHIP_KABINI_9835, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9836, PCI_CHIP_KABINI_9836, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9837, PCI_CHIP_KABINI_9837, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9838, PCI_CHIP_KABINI_9838, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_9839, PCI_CHIP_KABINI_9839, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983A, PCI_CHIP_KABINI_983A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983B, PCI_CHIP_KABINI_983B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983C, PCI_CHIP_KABINI_983C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983D, PCI_CHIP_KABINI_983D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983E, PCI_CHIP_KABINI_983E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983F, PCI_CHIP_KABINI_983F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9850, PCI_CHIP_MULLINS_9850, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9851, PCI_CHIP_MULLINS_9851, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9852, PCI_CHIP_MULLINS_9852, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9853, PCI_CHIP_MULLINS_9853, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9854, PCI_CHIP_MULLINS_9854, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9855, PCI_CHIP_MULLINS_9855, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9856, PCI_CHIP_MULLINS_9856, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9857, PCI_CHIP_MULLINS_9857, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9858, PCI_CHIP_MULLINS_9858, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_9859, PCI_CHIP_MULLINS_9859, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985A, PCI_CHIP_MULLINS_985A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985B, PCI_CHIP_MULLINS_985B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985C, PCI_CHIP_MULLINS_985C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1307, PCI_CHIP_KAVERI_1307, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1309, PCI_CHIP_KAVERI_1309, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130A, PCI_CHIP_KAVERI_130A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130B, PCI_CHIP_KAVERI_130B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130C, PCI_CHIP_KAVERI_130C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130D, PCI_CHIP_KAVERI_130D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130E, PCI_CHIP_KAVERI_130E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130F, PCI_CHIP_KAVERI_130F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1310, PCI_CHIP_KAVERI_1310, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1311, PCI_CHIP_KAVERI_1311, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1312, PCI_CHIP_KAVERI_1312, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1313, PCI_CHIP_KAVERI_1313, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1315, PCI_CHIP_KAVERI_1315, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1316, PCI_CHIP_KAVERI_1316, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1317, PCI_CHIP_KAVERI_1317, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1318, PCI_CHIP_KAVERI_1318, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A0, PCI_CHIP_HAWAII_67A0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A1, PCI_CHIP_HAWAII_67A1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A2, PCI_CHIP_HAWAII_67A2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A8, PCI_CHIP_HAWAII_67A8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A9, PCI_CHIP_HAWAII_67A9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67AA, PCI_CHIP_HAWAII_67AA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B0, PCI_CHIP_HAWAII_67B0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B1, PCI_CHIP_HAWAII_67B1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B8, PCI_CHIP_HAWAII_67B8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B9, PCI_CHIP_HAWAII_67B9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67BA, PCI_CHIP_HAWAII_67BA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67BE, PCI_CHIP_HAWAII_67BE, RES_SHARED_VGA },
|
||||
{ -1, -1, RES_UNDEFINED }
|
||||
};
|
||||
704
src/radeon_pci_device_match_gen.h
Normal file
704
src/radeon_pci_device_match_gen.h
Normal file
|
|
@ -0,0 +1,704 @@
|
|||
/* This file is autogenerated please do not edit */
|
||||
static const struct pci_id_match radeon_device_match[] = {
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3151, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3155, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E54, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS100_4136, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS200_4137, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_AD, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_AE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_AF, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_AG, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_AH, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_AI, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_AJ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_AK, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_AP, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_AQ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV360_AR, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_AS, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_AT, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_4155, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_AV, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS250_4237, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R200_BB, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS100_4336, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS200_4337, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS250_4437, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV250_If, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ig, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JH, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JI, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JJ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JK, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JL, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JM, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JN, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_4A4F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JP, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R420_JT, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R481_4B48, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R481_4B49, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LW, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LX, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LY, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LZ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ld, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lf, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lg, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_4C6E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_ND, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_NE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_NF, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R300_NG, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_NH, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_NI, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R360_NJ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R350_NK, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NP, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NQ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NR, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NS, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NT, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV350_NV, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QD, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QF, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QG, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R200_QH, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R200_QL, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R200_QM, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV200_QW, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV200_QX, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV100_QY, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV100_QZ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RN50_515E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5460, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5462, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5464, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UH, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UI, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UJ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UK, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_554C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_554D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_554E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_554F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_5550, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UQ, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UR, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_UT, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_564A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_564B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS480_5955, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5960, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5961, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5962, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5964, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5965, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RN50_5969, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS482_5974, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS485_5975, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A41, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A42, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A61, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A62, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C63, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_5D48, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_5D49, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R430_5D4A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D50, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R480_5D52, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R423_5D57, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E48, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7100, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7101, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7102, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7103, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7104, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7105, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7106, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7108, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_7109, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_710A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_710B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_710C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_710E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R520_710F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7140, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7141, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7142, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7143, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7144, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7145, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7146, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7147, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7149, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_714F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7151, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7152, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7153, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_715E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_715F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7180, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7181, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7183, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7186, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7187, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7188, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_718A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_718B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_718C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_718D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_718F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7193, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7196, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_719B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_719F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C3, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C6, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C7, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CD, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7200, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7210, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV515_7211, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7245, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7246, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7247, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7248, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7249, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_724F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV570_7280, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7281, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7283, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R580_7284, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7287, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV570_7288, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV570_7289, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV570_728B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV570_728C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7290, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7291, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7293, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV560_7297, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS350_7834, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS600_793F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS600_7941, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS600_7942, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS740_796F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_9400, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_9401, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_9402, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_9403, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_9405, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9441, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9443, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9444, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9446, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_944A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_944B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_944C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_944E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9450, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9452, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV790_9460, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV790_9462, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV770_947B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9480, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9488, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9489, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_948A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9491, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9495, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A3, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B3, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C6, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C7, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CD, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9504, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9506, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9508, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9509, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9517, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9519, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9542, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9555, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9557, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV710_955F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9586, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9587, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9588, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9589, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C6, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CC, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9590, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9596, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9597, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9598, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9599, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9591, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9593, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9595, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RV635_959B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9610, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9615, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9616, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9640, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9641, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9642, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9643, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9644, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9645, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9649, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9710, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9711, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9715, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9802, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9803, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9804, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9805, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9806, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9807, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9808, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9809, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PALM_980A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6898, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6899, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BF, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C7, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E5, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6700, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6701, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6702, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6703, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6704, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6705, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6706, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6707, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6708, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6709, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6718, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6719, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6720, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6721, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6722, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6723, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6724, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6725, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6726, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6727, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6728, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6729, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6738, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6739, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_673E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6740, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6741, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6742, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6743, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6744, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6745, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6746, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6747, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6748, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6749, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_674A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6750, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6751, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6758, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6759, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6840, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6841, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6842, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6843, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6849, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6850, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6858, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6859, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6760, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6761, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6762, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6763, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6764, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6765, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6766, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6767, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6768, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6770, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6771, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6772, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6778, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6779, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_677B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9900, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9901, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9903, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9904, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9905, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9906, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9907, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9908, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9909, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9910, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9913, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9917, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9918, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9919, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9990, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9991, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9992, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9993, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9994, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9995, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9996, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9997, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9998, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9999, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A4, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6780, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6784, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6788, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_678A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6790, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6791, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6792, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6798, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6799, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6800, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6801, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6802, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6806, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6808, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6809, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6810, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6811, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6816, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6817, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6818, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6819, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_684C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6820, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6821, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6822, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6823, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6824, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6825, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6826, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6827, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6828, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6829, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6830, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6831, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6835, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6837, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6838, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6839, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6600, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6601, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6602, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6603, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6604, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6605, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6606, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6607, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6608, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6610, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6611, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6613, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6617, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6620, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6621, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6623, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6631, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6660, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6663, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6664, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6665, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6667, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_666F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6640, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6641, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6646, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6647, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6649, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6650, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6651, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6658, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9830, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9831, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9832, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9833, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9834, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9835, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9836, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9837, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9838, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9839, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9850, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9851, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9852, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9853, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9854, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9855, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9856, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9857, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9858, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9859, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1307, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1309, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1310, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1311, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1312, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1313, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1315, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1316, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1317, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1318, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67AA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BE, 0 ),
|
||||
{ 0, 0, 0 }
|
||||
};
|
||||
483
src/radeon_present.c
Normal file
483
src/radeon_present.c
Normal file
|
|
@ -0,0 +1,483 @@
|
|||
/*
|
||||
* Copyright © 2014 Intel Corporation
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of the copyright holders not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. The copyright holders make no representations
|
||||
* about the suitability of this software for any purpose. It is provided "as
|
||||
* is" without express or implied warranty.
|
||||
*
|
||||
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
|
||||
* OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <poll.h>
|
||||
#include <sys/time.h>
|
||||
#include <time.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "radeon_bo_helper.h"
|
||||
#include "radeon_glamor.h"
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include "present.h"
|
||||
|
||||
static present_screen_info_rec radeon_present_screen_info;
|
||||
|
||||
struct radeon_present_vblank_event {
|
||||
uint64_t event_id;
|
||||
Bool unflip;
|
||||
};
|
||||
|
||||
static RRCrtcPtr
|
||||
radeon_present_get_crtc(WindowPtr window)
|
||||
{
|
||||
ScreenPtr screen = window->drawable.pScreen;
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(screen);
|
||||
xf86CrtcPtr crtc;
|
||||
RRCrtcPtr randr_crtc = NULL;
|
||||
|
||||
crtc = radeon_pick_best_crtc(pScrn, FALSE,
|
||||
window->drawable.x,
|
||||
window->drawable.x + window->drawable.width,
|
||||
window->drawable.y,
|
||||
window->drawable.y + window->drawable.height);
|
||||
|
||||
if (crtc)
|
||||
randr_crtc = crtc->randr_crtc;
|
||||
|
||||
return randr_crtc;
|
||||
}
|
||||
|
||||
static int
|
||||
radeon_present_get_ust_msc(RRCrtcPtr crtc, CARD64 *ust, CARD64 *msc)
|
||||
{
|
||||
xf86CrtcPtr xf86_crtc = crtc->devPrivate;
|
||||
drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
|
||||
|
||||
if (drmmode_crtc->dpms_mode != DPMSModeOn)
|
||||
return BadAlloc;
|
||||
|
||||
return drmmode_crtc_get_ust_msc(xf86_crtc, ust, msc);
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush the DRM event queue when full; this
|
||||
* makes space for new requests
|
||||
*/
|
||||
static Bool
|
||||
radeon_present_flush_drm_events(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
|
||||
drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[0]->driver_private;
|
||||
drmmode_ptr drmmode = drmmode_crtc->drmmode;
|
||||
struct pollfd p = { .fd = pRADEONEnt->fd, .events = POLLIN };
|
||||
int r;
|
||||
|
||||
do {
|
||||
r = poll(&p, 1, 0);
|
||||
} while (r == -1 && (errno == EINTR || errno == EAGAIN));
|
||||
|
||||
if (r <= 0)
|
||||
return 0;
|
||||
|
||||
return radeon_drm_handle_event(pRADEONEnt->fd, &drmmode->event_context) >= 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Called when the queued vblank event has occurred
|
||||
*/
|
||||
static void
|
||||
radeon_present_vblank_handler(xf86CrtcPtr crtc, unsigned int msc,
|
||||
uint64_t usec, void *data)
|
||||
{
|
||||
struct radeon_present_vblank_event *event = data;
|
||||
|
||||
present_event_notify(event->event_id, usec, msc);
|
||||
free(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* Called when the queued vblank is aborted
|
||||
*/
|
||||
static void
|
||||
radeon_present_vblank_abort(xf86CrtcPtr crtc, void *data)
|
||||
{
|
||||
struct radeon_present_vblank_event *event = data;
|
||||
|
||||
free(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* Queue an event to report back to the Present extension when the specified
|
||||
* MSC has past
|
||||
*/
|
||||
static int
|
||||
radeon_present_queue_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc)
|
||||
{
|
||||
xf86CrtcPtr xf86_crtc = crtc->devPrivate;
|
||||
ScreenPtr screen = crtc->pScreen;
|
||||
struct radeon_present_vblank_event *event;
|
||||
uintptr_t drm_queue_seq;
|
||||
|
||||
event = calloc(sizeof(struct radeon_present_vblank_event), 1);
|
||||
if (!event)
|
||||
return BadAlloc;
|
||||
event->event_id = event_id;
|
||||
|
||||
drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
|
||||
RADEON_DRM_QUEUE_CLIENT_DEFAULT,
|
||||
event_id, event,
|
||||
radeon_present_vblank_handler,
|
||||
radeon_present_vblank_abort,
|
||||
FALSE);
|
||||
if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) {
|
||||
free(event);
|
||||
return BadAlloc;
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
if (drmmode_wait_vblank(xf86_crtc,
|
||||
DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT, msc,
|
||||
drm_queue_seq, NULL, NULL))
|
||||
break;
|
||||
if (errno != EBUSY || !radeon_present_flush_drm_events(screen)) {
|
||||
radeon_drm_abort_entry(drm_queue_seq);
|
||||
return BadAlloc;
|
||||
}
|
||||
}
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove a pending vblank event from the DRM queue so that it is not reported
|
||||
* to the extension
|
||||
*/
|
||||
static void
|
||||
radeon_present_abort_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc)
|
||||
{
|
||||
radeon_drm_abort_id(event_id);
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush our batch buffer when requested by the Present extension.
|
||||
*/
|
||||
static void
|
||||
radeon_present_flush(WindowPtr window)
|
||||
{
|
||||
radeon_cs_flush_indirect(xf86ScreenToScrn(window->drawable.pScreen));
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
radeon_present_get_pixmap_tiling_flags(RADEONInfoPtr info, PixmapPtr pixmap)
|
||||
{
|
||||
uint32_t tiling_flags = radeon_get_pixmap_tiling_flags(pixmap);
|
||||
|
||||
/* Micro tiling is always enabled with macro tiling on >= R600, so we
|
||||
* can ignore the micro tiling bit in that case
|
||||
*/
|
||||
if ((tiling_flags & RADEON_TILING_MACRO) &&
|
||||
info->ChipFamily >= CHIP_FAMILY_R600)
|
||||
tiling_flags &= ~RADEON_TILING_MICRO;
|
||||
|
||||
return tiling_flags;
|
||||
}
|
||||
|
||||
/*
|
||||
* Test to see if unflipping is possible
|
||||
*
|
||||
* These tests have to pass for flips as well
|
||||
*/
|
||||
static Bool
|
||||
radeon_present_check_unflip(ScrnInfoPtr scrn)
|
||||
{
|
||||
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
|
||||
int num_crtcs_on;
|
||||
int i;
|
||||
|
||||
if (!scrn->vtSema)
|
||||
return FALSE;
|
||||
|
||||
for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) {
|
||||
xf86CrtcPtr crtc = config->crtc[i];
|
||||
|
||||
if (drmmode_crtc_can_flip(crtc)) {
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
|
||||
if (drmmode_crtc->flip_pending)
|
||||
return FALSE;
|
||||
|
||||
if (!drmmode_crtc->tear_free)
|
||||
num_crtcs_on++;
|
||||
}
|
||||
}
|
||||
|
||||
return num_crtcs_on > 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Test to see if page flipping is possible on the target crtc
|
||||
*/
|
||||
static Bool
|
||||
radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
|
||||
Bool sync_flip)
|
||||
{
|
||||
xf86CrtcPtr xf86_crtc = crtc->devPrivate;
|
||||
ScreenPtr screen = window->drawable.pScreen;
|
||||
ScrnInfoPtr scrn = xf86_crtc->scrn;
|
||||
#ifdef USE_GLAMOR
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
#endif
|
||||
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
PixmapPtr screen_pixmap = screen->GetScreenPixmap(screen);
|
||||
int num_crtcs_on;
|
||||
int i;
|
||||
|
||||
if (!scrn->vtSema)
|
||||
return FALSE;
|
||||
|
||||
if (!info->allowPageFlip)
|
||||
return FALSE;
|
||||
|
||||
if (info->sprites_visible > 0)
|
||||
return FALSE;
|
||||
|
||||
if (info->drmmode.dri2_flipping)
|
||||
return FALSE;
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
if (priv && priv->fb_failed)
|
||||
return FALSE;
|
||||
#endif
|
||||
|
||||
if (!radeon_pixmap_get_fb(pixmap)) {
|
||||
#ifdef USE_GLAMOR
|
||||
if (!priv)
|
||||
priv = radeon_get_pixmap_private(pixmap);
|
||||
|
||||
if (priv && !priv->fb_failed) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"Cannot get FB for Present flip (may be "
|
||||
"normal if using PRIME render offloading)\n");
|
||||
priv->fb_failed = TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* The kernel driver doesn't handle flipping between BOs with different
|
||||
* tiling parameters correctly yet
|
||||
*/
|
||||
if (radeon_present_get_pixmap_tiling_flags(info, pixmap) !=
|
||||
radeon_present_get_pixmap_tiling_flags(info, screen_pixmap))
|
||||
return FALSE;
|
||||
|
||||
for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) {
|
||||
if (drmmode_crtc_can_flip(config->crtc[i]))
|
||||
num_crtcs_on++;
|
||||
else if (config->crtc[i] == crtc->devPrivate)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (num_crtcs_on == 0)
|
||||
return FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Once the flip has been completed on all CRTCs, notify the
|
||||
* extension code telling it when that happened
|
||||
*/
|
||||
static void
|
||||
radeon_present_flip_event(xf86CrtcPtr crtc, uint32_t msc, uint64_t ust, void *pageflip_data)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
|
||||
struct radeon_present_vblank_event *event = pageflip_data;
|
||||
|
||||
if (event->unflip)
|
||||
info->drmmode.present_flipping = FALSE;
|
||||
|
||||
present_event_notify(event->event_id, ust, msc);
|
||||
free(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* The flip has been aborted, free the structure
|
||||
*/
|
||||
static void
|
||||
radeon_present_flip_abort(xf86CrtcPtr crtc, void *pageflip_data)
|
||||
{
|
||||
struct radeon_present_vblank_event *event = pageflip_data;
|
||||
|
||||
free(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* Queue a flip on 'crtc' to 'pixmap' at 'target_msc'. If 'sync_flip' is true,
|
||||
* then wait for vblank. Otherwise, flip immediately
|
||||
*/
|
||||
static Bool
|
||||
radeon_present_flip(RRCrtcPtr crtc, uint64_t event_id, uint64_t target_msc,
|
||||
PixmapPtr pixmap, Bool sync_flip)
|
||||
{
|
||||
xf86CrtcPtr xf86_crtc = crtc->devPrivate;
|
||||
ScreenPtr screen = crtc->pScreen;
|
||||
ScrnInfoPtr scrn = xf86_crtc->scrn;
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
struct radeon_present_vblank_event *event;
|
||||
Bool ret = FALSE;
|
||||
|
||||
if (!radeon_present_check_flip(crtc, screen->root, pixmap, sync_flip))
|
||||
return ret;
|
||||
|
||||
event = calloc(1, sizeof(struct radeon_present_vblank_event));
|
||||
if (!event)
|
||||
return ret;
|
||||
|
||||
event->event_id = event_id;
|
||||
|
||||
radeon_cs_flush_indirect(scrn);
|
||||
|
||||
ret = radeon_do_pageflip(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, pixmap,
|
||||
event_id, event, crtc->devPrivate,
|
||||
radeon_present_flip_event,
|
||||
radeon_present_flip_abort,
|
||||
sync_flip ? FLIP_VSYNC : FLIP_ASYNC,
|
||||
target_msc);
|
||||
if (!ret)
|
||||
xf86DrvMsg(scrn->scrnIndex, X_ERROR, "present flip failed\n");
|
||||
else
|
||||
info->drmmode.present_flipping = TRUE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Queue a flip back to the normal frame buffer
|
||||
*/
|
||||
static void
|
||||
radeon_present_unflip(ScreenPtr screen, uint64_t event_id)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
|
||||
struct radeon_present_vblank_event *event;
|
||||
PixmapPtr pixmap = screen->GetScreenPixmap(screen);
|
||||
enum drmmode_flip_sync flip_sync =
|
||||
(radeon_present_screen_info.capabilities & PresentCapabilityAsync) ?
|
||||
FLIP_ASYNC : FLIP_VSYNC;
|
||||
int i;
|
||||
|
||||
if (!radeon_present_check_unflip(scrn))
|
||||
goto modeset;
|
||||
|
||||
event = calloc(1, sizeof(struct radeon_present_vblank_event));
|
||||
if (!event) {
|
||||
ErrorF("%s: calloc failed, display might freeze\n", __func__);
|
||||
goto modeset;
|
||||
}
|
||||
|
||||
event->event_id = event_id;
|
||||
event->unflip = TRUE;
|
||||
|
||||
if (radeon_do_pageflip(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, pixmap,
|
||||
event_id, event, NULL, radeon_present_flip_event,
|
||||
radeon_present_flip_abort, flip_sync, 0))
|
||||
return;
|
||||
|
||||
modeset:
|
||||
radeon_finish(scrn, info->front_buffer);
|
||||
for (i = 0; i < config->num_crtc; i++) {
|
||||
xf86CrtcPtr crtc = config->crtc[i];
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
|
||||
if (!crtc->enabled || drmmode_crtc->tear_free)
|
||||
continue;
|
||||
|
||||
if (drmmode_crtc->dpms_mode == DPMSModeOn)
|
||||
crtc->funcs->set_mode_major(crtc, &crtc->mode, crtc->rotation,
|
||||
crtc->x, crtc->y);
|
||||
else
|
||||
drmmode_crtc->need_modeset = TRUE;
|
||||
}
|
||||
|
||||
present_event_notify(event_id, 0, 0);
|
||||
|
||||
info->drmmode.present_flipping = FALSE;
|
||||
}
|
||||
|
||||
static present_screen_info_rec radeon_present_screen_info = {
|
||||
.version = 0,
|
||||
|
||||
.get_crtc = radeon_present_get_crtc,
|
||||
.get_ust_msc = radeon_present_get_ust_msc,
|
||||
.queue_vblank = radeon_present_queue_vblank,
|
||||
.abort_vblank = radeon_present_abort_vblank,
|
||||
.flush = radeon_present_flush,
|
||||
|
||||
.capabilities = PresentCapabilityNone,
|
||||
.check_flip = radeon_present_check_flip,
|
||||
.flip = radeon_present_flip,
|
||||
.unflip = radeon_present_unflip,
|
||||
};
|
||||
|
||||
static Bool
|
||||
radeon_present_has_async_flip(ScreenPtr screen)
|
||||
{
|
||||
#ifdef DRM_CAP_ASYNC_PAGE_FLIP
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
|
||||
int ret;
|
||||
uint64_t value;
|
||||
|
||||
ret = drmGetCap(pRADEONEnt->fd, DRM_CAP_ASYNC_PAGE_FLIP, &value);
|
||||
if (ret == 0)
|
||||
return value == 1;
|
||||
#endif
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
Bool
|
||||
radeon_present_screen_init(ScreenPtr screen)
|
||||
{
|
||||
if (radeon_present_has_async_flip(screen))
|
||||
radeon_present_screen_info.capabilities |= PresentCapabilityAsync;
|
||||
|
||||
if (!present_screen_init(screen, &radeon_present_screen_info)) {
|
||||
xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_WARNING,
|
||||
"Present extension disabled because present_screen_init failed\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO,
|
||||
"Present extension enabled\n");
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
287
src/radeon_probe.c
Normal file
287
src/radeon_probe.c
Normal file
|
|
@ -0,0 +1,287 @@
|
|||
/*
|
||||
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
|
||||
* VA Linux Systems Inc., Fremont, California.
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation on the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
|
||||
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@xfree86.org>
|
||||
* Rickard E. Faith <faith@valinux.com>
|
||||
* KMS support - Dave Airlie <airlied@redhat.com>
|
||||
*/
|
||||
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_version.h"
|
||||
#include "atipciids.h"
|
||||
#include "atipcirename.h"
|
||||
|
||||
#include "xf86.h"
|
||||
|
||||
#include "xf86drmMode.h"
|
||||
|
||||
#include <xf86Pci.h>
|
||||
|
||||
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
|
||||
#include <xf86_OSproc.h>
|
||||
#endif
|
||||
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
#include <xf86platformBus.h>
|
||||
#endif
|
||||
|
||||
#include "radeon_chipset_gen.h"
|
||||
|
||||
#include "radeon_pci_chipset_gen.h"
|
||||
|
||||
#include "radeon_pci_device_match_gen.h"
|
||||
|
||||
_X_EXPORT int gRADEONEntityIndex = -1;
|
||||
|
||||
/* Return the options for supported chipset 'n'; NULL otherwise */
|
||||
static const OptionInfoRec *
|
||||
RADEONAvailableOptions(int chipid, int busid)
|
||||
{
|
||||
return RADEONOptionsWeak();
|
||||
}
|
||||
|
||||
/* Return the string name for supported chipset 'n'; NULL otherwise. */
|
||||
static void
|
||||
RADEONIdentify(int flags)
|
||||
{
|
||||
xf86PrintChipsets(RADEON_NAME,
|
||||
"Driver for ATI/AMD Radeon chipsets",
|
||||
RADEONUniqueChipsets);
|
||||
}
|
||||
|
||||
|
||||
static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci_dev)
|
||||
{
|
||||
char *busIdString;
|
||||
int ret;
|
||||
|
||||
if (!xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
|
||||
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
|
||||
"[KMS] No DRICreatePCIBusID symbol, no kernel modesetting.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
busIdString = DRICreatePCIBusID(pci_dev);
|
||||
ret = drmCheckModesettingSupported(busIdString);
|
||||
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
|
||||
if (ret) {
|
||||
if (xf86LoadKernelModule("radeonkms"))
|
||||
ret = drmCheckModesettingSupported(busIdString);
|
||||
}
|
||||
#endif
|
||||
free(busIdString);
|
||||
if (ret) {
|
||||
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
|
||||
"[KMS] drm report modesetting isn't supported.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
|
||||
"[KMS] Kernel modesetting enabled.\n");
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_get_scrninfo(int entity_num, void *pci_dev)
|
||||
{
|
||||
ScrnInfoPtr pScrn = NULL;
|
||||
EntityInfoPtr pEnt;
|
||||
|
||||
pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets,
|
||||
NULL,
|
||||
NULL, NULL, NULL, NULL);
|
||||
|
||||
if (!pScrn)
|
||||
return FALSE;
|
||||
|
||||
if (!radeon_kernel_mode_enabled(pScrn, pci_dev))
|
||||
return FALSE;
|
||||
|
||||
pScrn->driverVersion = RADEON_VERSION_CURRENT;
|
||||
pScrn->driverName = RADEON_DRIVER_NAME;
|
||||
pScrn->name = RADEON_NAME;
|
||||
pScrn->Probe = NULL;
|
||||
|
||||
pScrn->PreInit = RADEONPreInit_KMS;
|
||||
pScrn->ScreenInit = RADEONScreenInit_KMS;
|
||||
pScrn->SwitchMode = RADEONSwitchMode_KMS;
|
||||
pScrn->AdjustFrame = RADEONAdjustFrame_KMS;
|
||||
pScrn->EnterVT = RADEONEnterVT_KMS;
|
||||
pScrn->LeaveVT = RADEONLeaveVT_KMS;
|
||||
pScrn->FreeScreen = RADEONFreeScreen_KMS;
|
||||
pScrn->ValidMode = RADEONValidMode;
|
||||
|
||||
pEnt = xf86GetEntityInfo(entity_num);
|
||||
|
||||
/* Create a RADEONEntity for all chips, even with old single head
|
||||
* Radeon, need to use pRADEONEnt for new monitor detection routines.
|
||||
*/
|
||||
{
|
||||
DevUnion *pPriv;
|
||||
|
||||
xf86SetEntitySharable(entity_num);
|
||||
|
||||
if (gRADEONEntityIndex == -1)
|
||||
gRADEONEntityIndex = xf86AllocateEntityPrivateIndex();
|
||||
|
||||
pPriv = xf86GetEntityPrivate(pEnt->index,
|
||||
gRADEONEntityIndex);
|
||||
|
||||
xf86SetEntityInstanceForScreen(pScrn, pEnt->index, xf86GetNumEntityInstances(pEnt->index) - 1);
|
||||
|
||||
if (!pPriv->ptr)
|
||||
pPriv->ptr = XNFcallocarray(sizeof(RADEONEntRec), 1);
|
||||
}
|
||||
|
||||
free(pEnt);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static Bool
|
||||
radeon_pci_probe(
|
||||
DriverPtr pDriver,
|
||||
int entity_num,
|
||||
struct pci_device *device,
|
||||
intptr_t match_data
|
||||
)
|
||||
{
|
||||
return radeon_get_scrninfo(entity_num, (void *)device);
|
||||
}
|
||||
|
||||
static Bool
|
||||
RADEONDriverFunc(ScrnInfoPtr scrn, xorgDriverFuncOp op, void *data)
|
||||
{
|
||||
xorgHWFlags *flag;
|
||||
|
||||
switch (op) {
|
||||
case GET_REQUIRED_HW_INTERFACES:
|
||||
flag = (CARD32 *)data;
|
||||
(*flag) = 0;
|
||||
return TRUE;
|
||||
case SUPPORTS_SERVER_FDS:
|
||||
return TRUE;
|
||||
default:
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
static Bool
|
||||
radeon_platform_probe(DriverPtr pDriver,
|
||||
int entity_num, int flags,
|
||||
struct xf86_platform_device *dev,
|
||||
intptr_t match_data)
|
||||
{
|
||||
ScrnInfoPtr pScrn;
|
||||
int scr_flags = 0;
|
||||
EntityInfoPtr pEnt;
|
||||
|
||||
if (!dev->pdev)
|
||||
return FALSE;
|
||||
|
||||
if (flags & PLATFORM_PROBE_GPU_SCREEN)
|
||||
scr_flags = XF86_ALLOCATE_GPU_SCREEN;
|
||||
|
||||
pScrn = xf86AllocateScreen(pDriver, scr_flags);
|
||||
if (xf86IsEntitySharable(entity_num))
|
||||
xf86SetEntityShared(entity_num);
|
||||
xf86AddEntityToScreen(pScrn, entity_num);
|
||||
|
||||
if (!radeon_kernel_mode_enabled(pScrn, dev->pdev))
|
||||
return FALSE;
|
||||
|
||||
pScrn->driverVersion = RADEON_VERSION_CURRENT;
|
||||
pScrn->driverName = RADEON_DRIVER_NAME;
|
||||
pScrn->name = RADEON_NAME;
|
||||
pScrn->Probe = NULL;
|
||||
pScrn->PreInit = RADEONPreInit_KMS;
|
||||
pScrn->ScreenInit = RADEONScreenInit_KMS;
|
||||
pScrn->SwitchMode = RADEONSwitchMode_KMS;
|
||||
pScrn->AdjustFrame = RADEONAdjustFrame_KMS;
|
||||
pScrn->EnterVT = RADEONEnterVT_KMS;
|
||||
pScrn->LeaveVT = RADEONLeaveVT_KMS;
|
||||
pScrn->FreeScreen = RADEONFreeScreen_KMS;
|
||||
pScrn->ValidMode = RADEONValidMode;
|
||||
|
||||
pEnt = xf86GetEntityInfo(entity_num);
|
||||
|
||||
/* Create a RADEONEntity for all chips, even with old single head
|
||||
* Radeon, need to use pRADEONEnt for new monitor detection routines.
|
||||
*/
|
||||
{
|
||||
DevUnion *pPriv;
|
||||
RADEONEntPtr pRADEONEnt;
|
||||
|
||||
xf86SetEntitySharable(entity_num);
|
||||
|
||||
if (gRADEONEntityIndex == -1)
|
||||
gRADEONEntityIndex = xf86AllocateEntityPrivateIndex();
|
||||
|
||||
pPriv = xf86GetEntityPrivate(pEnt->index,
|
||||
gRADEONEntityIndex);
|
||||
|
||||
xf86SetEntityInstanceForScreen(pScrn, pEnt->index, xf86GetNumEntityInstances(pEnt->index) - 1);
|
||||
|
||||
if (!pPriv->ptr) {
|
||||
pPriv->ptr = XNFcallocarray(sizeof(RADEONEntRec), 1);
|
||||
pRADEONEnt = pPriv->ptr;
|
||||
} else {
|
||||
pRADEONEnt = pPriv->ptr;
|
||||
}
|
||||
pRADEONEnt->platform_dev = dev;
|
||||
}
|
||||
|
||||
free(pEnt);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
DriverRec RADEON =
|
||||
{
|
||||
RADEON_VERSION_CURRENT,
|
||||
RADEON_DRIVER_NAME,
|
||||
RADEONIdentify,
|
||||
NULL,
|
||||
RADEONAvailableOptions,
|
||||
NULL,
|
||||
0,
|
||||
RADEONDriverFunc,
|
||||
radeon_device_match,
|
||||
radeon_pci_probe,
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
radeon_platform_probe
|
||||
#endif
|
||||
};
|
||||
162
src/radeon_probe.h
Normal file
162
src/radeon_probe.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
|
||||
* VA Linux Systems Inc., Fremont, California.
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation on the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
|
||||
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@xfree86.org>
|
||||
*
|
||||
* Modified by Marc Aurele La France <tsi@xfree86.org> for ATI driver merge.
|
||||
*/
|
||||
|
||||
#ifndef _RADEON_PROBE_H_
|
||||
#define _RADEON_PROBE_H_ 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include "xorg-server.h"
|
||||
#include "xf86str.h"
|
||||
#include "xf86DDC.h"
|
||||
#include "randrstr.h"
|
||||
|
||||
#include "xf86Crtc.h"
|
||||
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
#include "xf86platformBus.h"
|
||||
#endif
|
||||
|
||||
#include "exa.h"
|
||||
|
||||
extern DriverRec RADEON;
|
||||
|
||||
typedef enum {
|
||||
CHIP_FAMILY_UNKNOW,
|
||||
CHIP_FAMILY_LEGACY,
|
||||
CHIP_FAMILY_RADEON,
|
||||
CHIP_FAMILY_RV100,
|
||||
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
|
||||
CHIP_FAMILY_RV200,
|
||||
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
|
||||
CHIP_FAMILY_R200,
|
||||
CHIP_FAMILY_RV250,
|
||||
CHIP_FAMILY_RS300, /* RS300/RS350 */
|
||||
CHIP_FAMILY_RV280,
|
||||
CHIP_FAMILY_R300,
|
||||
CHIP_FAMILY_R350,
|
||||
CHIP_FAMILY_RV350,
|
||||
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
|
||||
CHIP_FAMILY_R420, /* R420/R423/M18 */
|
||||
CHIP_FAMILY_RV410, /* RV410, M26 */
|
||||
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
|
||||
CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
|
||||
CHIP_FAMILY_RV515, /* rv515 */
|
||||
CHIP_FAMILY_R520, /* r520 */
|
||||
CHIP_FAMILY_RV530, /* rv530 */
|
||||
CHIP_FAMILY_R580, /* r580 */
|
||||
CHIP_FAMILY_RV560, /* rv560 */
|
||||
CHIP_FAMILY_RV570, /* rv570 */
|
||||
CHIP_FAMILY_RS600,
|
||||
CHIP_FAMILY_RS690,
|
||||
CHIP_FAMILY_RS740,
|
||||
CHIP_FAMILY_R600, /* r600 */
|
||||
CHIP_FAMILY_RV610,
|
||||
CHIP_FAMILY_RV630,
|
||||
CHIP_FAMILY_RV670,
|
||||
CHIP_FAMILY_RV620,
|
||||
CHIP_FAMILY_RV635,
|
||||
CHIP_FAMILY_RS780,
|
||||
CHIP_FAMILY_RS880,
|
||||
CHIP_FAMILY_RV770, /* r700 */
|
||||
CHIP_FAMILY_RV730,
|
||||
CHIP_FAMILY_RV710,
|
||||
CHIP_FAMILY_RV740,
|
||||
CHIP_FAMILY_CEDAR, /* evergreen */
|
||||
CHIP_FAMILY_REDWOOD,
|
||||
CHIP_FAMILY_JUNIPER,
|
||||
CHIP_FAMILY_CYPRESS,
|
||||
CHIP_FAMILY_HEMLOCK,
|
||||
CHIP_FAMILY_PALM,
|
||||
CHIP_FAMILY_SUMO,
|
||||
CHIP_FAMILY_SUMO2,
|
||||
CHIP_FAMILY_BARTS,
|
||||
CHIP_FAMILY_TURKS,
|
||||
CHIP_FAMILY_CAICOS,
|
||||
CHIP_FAMILY_CAYMAN,
|
||||
CHIP_FAMILY_ARUBA,
|
||||
CHIP_FAMILY_TAHITI,
|
||||
CHIP_FAMILY_PITCAIRN,
|
||||
CHIP_FAMILY_VERDE,
|
||||
CHIP_FAMILY_OLAND,
|
||||
CHIP_FAMILY_HAINAN,
|
||||
CHIP_FAMILY_BONAIRE,
|
||||
CHIP_FAMILY_KAVERI,
|
||||
CHIP_FAMILY_KABINI,
|
||||
CHIP_FAMILY_HAWAII,
|
||||
CHIP_FAMILY_MULLINS,
|
||||
CHIP_FAMILY_LAST
|
||||
} RADEONChipFamily;
|
||||
|
||||
typedef struct {
|
||||
uint32_t pci_device_id;
|
||||
RADEONChipFamily chip_family;
|
||||
int mobility;
|
||||
int igp;
|
||||
int nocrtc2;
|
||||
int nointtvout;
|
||||
int singledac;
|
||||
} RADEONCardInfo;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
Bool HasCRTC2; /* All cards except original Radeon */
|
||||
Bool has_page_flip_target;
|
||||
|
||||
int fd; /* for sharing across zaphod heads */
|
||||
int fd_ref;
|
||||
unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */
|
||||
int fd_wakeup_ref;
|
||||
unsigned int assigned_crtcs;
|
||||
unsigned int num_scrns;
|
||||
ScrnInfoPtr scrn[6];
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
struct xf86_platform_device *platform_dev;
|
||||
#endif
|
||||
char *render_node;
|
||||
} RADEONEntRec, *RADEONEntPtr;
|
||||
|
||||
extern const OptionInfoRec *RADEONOptionsWeak(void);
|
||||
|
||||
extern Bool RADEONPreInit_KMS(ScrnInfoPtr, int);
|
||||
extern Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv);
|
||||
extern Bool RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode);
|
||||
extern void RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y);
|
||||
extern Bool RADEONEnterVT_KMS(ScrnInfoPtr pScrn);
|
||||
extern void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn);
|
||||
extern void RADEONFreeScreen_KMS(ScrnInfoPtr pScrn);
|
||||
|
||||
extern ModeStatus RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode,
|
||||
Bool verbose, int flag);
|
||||
#endif /* _RADEON_PROBE_H_ */
|
||||
5679
src/radeon_reg.h
Normal file
5679
src/radeon_reg.h
Normal file
File diff suppressed because it is too large
Load diff
131
src/radeon_sync.c
Normal file
131
src/radeon_sync.c
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright © 2013-2014 Intel Corporation
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of the copyright holders not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. The copyright holders make no representations
|
||||
* about the suitability of this software for any purpose. It is provided "as
|
||||
* is" without express or implied warranty.
|
||||
*
|
||||
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
|
||||
* OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "radeon.h"
|
||||
|
||||
#include "misync.h"
|
||||
#include "misyncshm.h"
|
||||
#include "misyncstr.h"
|
||||
|
||||
/*
|
||||
* This whole file exists to wrap a sync fence trigger operation
|
||||
* so that we can flush the batch buffer to provide serialization
|
||||
* between the server and the shm fence client
|
||||
*/
|
||||
|
||||
static DevPrivateKeyRec radeon_sync_fence_private_key;
|
||||
|
||||
typedef struct _radeon_sync_fence_private {
|
||||
SyncFenceSetTriggeredFunc set_triggered;
|
||||
} radeon_sync_fence_private;
|
||||
|
||||
#define SYNC_FENCE_PRIV(pFence) \
|
||||
(radeon_sync_fence_private *) dixLookupPrivate(&pFence->devPrivates, &radeon_sync_fence_private_key)
|
||||
|
||||
static void
|
||||
radeon_sync_fence_set_triggered (SyncFence *fence)
|
||||
{
|
||||
ScreenPtr screen = fence->pScreen;
|
||||
radeon_sync_fence_private *private = SYNC_FENCE_PRIV(fence);
|
||||
|
||||
/* Flush pending rendering operations */
|
||||
radeon_cs_flush_indirect(xf86ScreenToScrn(screen));
|
||||
|
||||
fence->funcs.SetTriggered = private->set_triggered;
|
||||
fence->funcs.SetTriggered(fence);
|
||||
private->set_triggered = fence->funcs.SetTriggered;
|
||||
fence->funcs.SetTriggered = radeon_sync_fence_set_triggered;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_sync_create_fence(ScreenPtr screen,
|
||||
SyncFence *fence,
|
||||
Bool initially_triggered)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen);
|
||||
radeon_sync_fence_private *private = SYNC_FENCE_PRIV(fence);
|
||||
|
||||
screen_funcs->CreateFence = info->CreateFence;
|
||||
screen_funcs->CreateFence(screen, fence, initially_triggered);
|
||||
info->CreateFence = screen_funcs->CreateFence;
|
||||
screen_funcs->CreateFence = radeon_sync_create_fence;
|
||||
|
||||
private->set_triggered = fence->funcs.SetTriggered;
|
||||
fence->funcs.SetTriggered = radeon_sync_fence_set_triggered;
|
||||
}
|
||||
|
||||
Bool
|
||||
radeon_sync_init(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
SyncScreenFuncsPtr screen_funcs;
|
||||
|
||||
if (!xf86LoaderCheckSymbol("miSyncShmScreenInit")) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"SYNC extension fences disabled because "
|
||||
"miSyncShmScreenInit symbol unresolved\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (!miSyncShmScreenInit(screen)) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"SYNC extension fences disabled because "
|
||||
"miSyncShmScreenInit failed\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (!dixPrivateKeyRegistered(&radeon_sync_fence_private_key)) {
|
||||
if (!dixRegisterPrivateKey(&radeon_sync_fence_private_key,
|
||||
PRIVATE_SYNC_FENCE,
|
||||
sizeof (radeon_sync_fence_private))) {
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"SYNC extension fences disabled because "
|
||||
"dixRegisterPrivateKey failed\n");
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO,
|
||||
"SYNC extension fences enabled\n");
|
||||
|
||||
screen_funcs = miSyncGetScreenFuncs(screen);
|
||||
info->CreateFence = screen_funcs->CreateFence;
|
||||
screen_funcs->CreateFence = radeon_sync_create_fence;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void
|
||||
radeon_sync_close(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
RADEONInfoPtr info = RADEONPTR(scrn);
|
||||
SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen);
|
||||
|
||||
if (screen_funcs && info->CreateFence)
|
||||
screen_funcs->CreateFence = info->CreateFence;
|
||||
|
||||
info->CreateFence = NULL;
|
||||
}
|
||||
925
src/radeon_textured_video.c
Normal file
925
src/radeon_textured_video.c
Normal file
|
|
@ -0,0 +1,925 @@
|
|||
/*
|
||||
* Copyright 2008 Alex Deucher
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
*
|
||||
* Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al.
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include <X11/extensions/Xv.h>
|
||||
#include "fourcc.h"
|
||||
|
||||
extern void
|
||||
R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
|
||||
|
||||
extern void
|
||||
EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
|
||||
|
||||
|
||||
#define IMAGE_MAX_WIDTH 2048
|
||||
#define IMAGE_MAX_HEIGHT 2048
|
||||
|
||||
#define IMAGE_MAX_WIDTH_R500 4096
|
||||
#define IMAGE_MAX_HEIGHT_R500 4096
|
||||
|
||||
#define IMAGE_MAX_WIDTH_R600 8192
|
||||
#define IMAGE_MAX_HEIGHT_R600 8192
|
||||
|
||||
#define IMAGE_MAX_WIDTH_EG 16384
|
||||
#define IMAGE_MAX_HEIGHT_EG 16384
|
||||
|
||||
static Bool
|
||||
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
static __inline__ uint32_t F_TO_DW(float val)
|
||||
{
|
||||
union {
|
||||
float f;
|
||||
uint32_t l;
|
||||
} tmp;
|
||||
tmp.f = val;
|
||||
return tmp.l;
|
||||
}
|
||||
|
||||
/* Borrowed from Mesa */
|
||||
static __inline__ uint32_t F_TO_24(float val)
|
||||
{
|
||||
float mantissa;
|
||||
int exponent;
|
||||
uint32_t float24 = 0;
|
||||
|
||||
if (val == 0.0)
|
||||
return 0;
|
||||
|
||||
mantissa = frexpf(val, &exponent);
|
||||
|
||||
/* Handle -ve */
|
||||
if (mantissa < 0) {
|
||||
float24 |= (1 << 23);
|
||||
mantissa = mantissa * -1.0;
|
||||
}
|
||||
/* Handle exponent, bias of 63 */
|
||||
exponent += 62;
|
||||
float24 |= (exponent << 16);
|
||||
/* Kill 7 LSB of mantissa */
|
||||
float24 |= (F_TO_DW(mantissa) & 0x7FFFFF) >> 7;
|
||||
|
||||
return float24;
|
||||
}
|
||||
|
||||
static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa)
|
||||
{
|
||||
unsigned ur = fr * 255.0 + 0.5;
|
||||
unsigned ug = fg * 255.0 + 0.5;
|
||||
unsigned ub = fb * 255.0 + 0.5;
|
||||
unsigned ua = fa * 255.0 + 0.5;
|
||||
return (ua << 24) | (ur << 16) | (ug << 8) | ub;
|
||||
}
|
||||
|
||||
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
|
||||
note the difference to the parameters used in overlay are due
|
||||
to 10bit vs. float calcs */
|
||||
static REF_TRANSFORM trans[2] =
|
||||
{
|
||||
{1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */
|
||||
{1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */
|
||||
};
|
||||
|
||||
|
||||
/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
|
||||
* or by freeing mem_struct (if non-NULL) and allocating a new space. The size
|
||||
* is measured in bytes, and the offset from the beginning of card space is
|
||||
* returned.
|
||||
*/
|
||||
static Bool
|
||||
radeon_allocate_video_bo(ScrnInfoPtr pScrn,
|
||||
struct radeon_bo **video_bo_p,
|
||||
int size,
|
||||
int align,
|
||||
int domain)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_bo *video_bo;
|
||||
|
||||
if (*video_bo_p)
|
||||
radeon_bo_unref(*video_bo_p);
|
||||
|
||||
video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0);
|
||||
|
||||
*video_bo_p = video_bo;
|
||||
|
||||
if (!video_bo)
|
||||
return FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
{
|
||||
if (pPriv->video_memory) {
|
||||
radeon_bo_unref(pPriv->video_memory);
|
||||
pPriv->video_memory = NULL;
|
||||
|
||||
if (pPriv->textured) {
|
||||
pPriv->src_bo[0] = NULL;
|
||||
radeon_bo_unref(pPriv->src_bo[1]);
|
||||
pPriv->src_bo[1] = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
RADEONStopVideo(ScrnInfoPtr pScrn, void *data, Bool cleanup)
|
||||
{
|
||||
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
|
||||
|
||||
if (pPriv->textured) {
|
||||
if (cleanup) {
|
||||
RADEONFreeVideoMemory(pScrn, pPriv);
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#define OUT_ACCEL_REG_F(reg, val) OUT_RING_REG(reg, F_TO_DW(val))
|
||||
|
||||
#include "radeon_textured_videofuncs.c"
|
||||
|
||||
#undef OUT_ACCEL_REG_F
|
||||
|
||||
static void
|
||||
R600CopyData(
|
||||
ScrnInfoPtr pScrn,
|
||||
unsigned char *src,
|
||||
unsigned char *dst,
|
||||
unsigned int srcPitch,
|
||||
unsigned int dstPitch,
|
||||
unsigned int h,
|
||||
unsigned int w,
|
||||
unsigned int cpp
|
||||
){
|
||||
if (cpp == 2) {
|
||||
w *= 2;
|
||||
cpp = 1;
|
||||
}
|
||||
|
||||
if (srcPitch == dstPitch)
|
||||
memcpy(dst, src, srcPitch * h);
|
||||
else {
|
||||
while (h--) {
|
||||
memcpy(dst, src, srcPitch);
|
||||
src += srcPitch;
|
||||
dst += dstPitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
RADEONPutImageTextured(ScrnInfoPtr pScrn,
|
||||
short src_x, short src_y,
|
||||
short drw_x, short drw_y,
|
||||
short src_w, short src_h,
|
||||
short drw_w, short drw_h,
|
||||
int id,
|
||||
unsigned char *buf,
|
||||
short width,
|
||||
short height,
|
||||
Bool sync,
|
||||
RegionPtr clipBoxes,
|
||||
void *data,
|
||||
DrawablePtr pDraw)
|
||||
{
|
||||
ScreenPtr pScreen = pScrn->pScreen;
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
|
||||
INT32 x1, x2, y1, y2;
|
||||
int srcPitch, srcPitch2, dstPitch, dstPitch2 = 0;
|
||||
int s2offset, s3offset, tmp;
|
||||
int d2line, d3line;
|
||||
int top, nlines, size;
|
||||
BoxRec dstBox;
|
||||
int dst_width = width, dst_height = height;
|
||||
int aligned_height;
|
||||
int h_align = drmmode_get_height_align(pScrn, 0);
|
||||
struct radeon_bo *src_bo;
|
||||
int ret;
|
||||
|
||||
/* make the compiler happy */
|
||||
s2offset = s3offset = srcPitch2 = 0;
|
||||
|
||||
/* Clip */
|
||||
x1 = src_x;
|
||||
x2 = src_x + src_w;
|
||||
y1 = src_y;
|
||||
y2 = src_y + src_h;
|
||||
|
||||
dstBox.x1 = drw_x;
|
||||
dstBox.x2 = drw_x + drw_w;
|
||||
dstBox.y1 = drw_y;
|
||||
dstBox.y2 = drw_y + drw_h;
|
||||
|
||||
if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height))
|
||||
return Success;
|
||||
|
||||
if ((x1 >= x2) || (y1 >= y2))
|
||||
return Success;
|
||||
|
||||
/* Bicubic filter setup */
|
||||
pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF);
|
||||
if (!(IS_R300_3D || IS_R500_3D)) {
|
||||
pPriv->bicubic_enabled = FALSE;
|
||||
pPriv->bicubic_state = BICUBIC_OFF;
|
||||
}
|
||||
if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) {
|
||||
/*
|
||||
* Applying the bicubic filter with a scale of less than 200%
|
||||
* results in a blurred picture, so disable the filter.
|
||||
*/
|
||||
if ((src_w > drw_w / 2) || (src_h > drw_h / 2))
|
||||
pPriv->bicubic_enabled = FALSE;
|
||||
}
|
||||
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600)
|
||||
pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0);
|
||||
else
|
||||
pPriv->hw_align = 64;
|
||||
|
||||
aligned_height = RADEON_ALIGN(dst_height, h_align);
|
||||
|
||||
switch(id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
srcPitch = RADEON_ALIGN(width, 4);
|
||||
srcPitch2 = RADEON_ALIGN(width >> 1, 4);
|
||||
if (pPriv->bicubic_state != BICUBIC_OFF) {
|
||||
dstPitch = RADEON_ALIGN(dst_width << 1, pPriv->hw_align);
|
||||
dstPitch2 = 0;
|
||||
} else {
|
||||
dstPitch = RADEON_ALIGN(dst_width, pPriv->hw_align);
|
||||
dstPitch2 = RADEON_ALIGN(dstPitch >> 1, pPriv->hw_align);
|
||||
}
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
dstPitch = RADEON_ALIGN(dst_width << 1, pPriv->hw_align);
|
||||
srcPitch = (width << 1);
|
||||
srcPitch2 = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
size = dstPitch * aligned_height + 2 * dstPitch2 * RADEON_ALIGN(((aligned_height + 1) >> 1), h_align);
|
||||
size = RADEON_ALIGN(size, pPriv->hw_align);
|
||||
|
||||
if (size != pPriv->size) {
|
||||
RADEONFreeVideoMemory(pScrn, pPriv);
|
||||
}
|
||||
|
||||
if (!pPriv->video_memory) {
|
||||
Bool ret;
|
||||
ret = radeon_allocate_video_bo(pScrn,
|
||||
&pPriv->video_memory,
|
||||
size, pPriv->hw_align,
|
||||
RADEON_GEM_DOMAIN_GTT);
|
||||
if (ret == FALSE)
|
||||
return BadAlloc;
|
||||
|
||||
pPriv->src_bo[0] = pPriv->video_memory;
|
||||
radeon_allocate_video_bo(pScrn, (void*)&pPriv->src_bo[1], size,
|
||||
pPriv->hw_align,
|
||||
RADEON_GEM_DOMAIN_GTT);
|
||||
}
|
||||
|
||||
/* Bicubic filter loading */
|
||||
if (pPriv->bicubic_enabled) {
|
||||
if (!info->bicubic_bo)
|
||||
pPriv->bicubic_enabled = FALSE;
|
||||
}
|
||||
|
||||
if (pDraw->type == DRAWABLE_WINDOW)
|
||||
pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw);
|
||||
else
|
||||
pPriv->pPixmap = (PixmapPtr)pDraw;
|
||||
|
||||
/* Force the pixmap into framebuffer so we can draw to it. */
|
||||
info->exa_force_create = TRUE;
|
||||
exaMoveInPixmap(pPriv->pPixmap);
|
||||
info->exa_force_create = FALSE;
|
||||
|
||||
/* copy data */
|
||||
top = (y1 >> 16) & ~1;
|
||||
nlines = ((y2 + 0xffff) >> 16) - top;
|
||||
|
||||
pPriv->currentBuffer ^= 1;
|
||||
|
||||
src_bo = pPriv->src_bo[pPriv->currentBuffer];
|
||||
|
||||
ret = radeon_bo_map(src_bo, 1);
|
||||
if (ret)
|
||||
return BadAlloc;
|
||||
|
||||
pPriv->src_addr = src_bo->ptr;
|
||||
pPriv->src_pitch = dstPitch;
|
||||
|
||||
pPriv->planeu_offset = dstPitch * aligned_height;
|
||||
pPriv->planeu_offset = RADEON_ALIGN(pPriv->planeu_offset, pPriv->hw_align);
|
||||
pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * RADEON_ALIGN(((aligned_height + 1) >> 1), h_align);
|
||||
pPriv->planev_offset = RADEON_ALIGN(pPriv->planev_offset, pPriv->hw_align);
|
||||
|
||||
pPriv->size = size;
|
||||
pPriv->pDraw = pDraw;
|
||||
|
||||
switch(id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
s2offset = srcPitch * (RADEON_ALIGN(height, 2));
|
||||
s3offset = s2offset + (srcPitch2 * ((height + 1) >> 1));
|
||||
s2offset += ((top >> 1) * srcPitch2);
|
||||
s3offset += ((top >> 1) * srcPitch2);
|
||||
if (pPriv->bicubic_state != BICUBIC_OFF) {
|
||||
if (id == FOURCC_I420) {
|
||||
tmp = s2offset;
|
||||
s2offset = s3offset;
|
||||
s3offset = tmp;
|
||||
}
|
||||
RADEONCopyMungedData(pScrn, buf + (top * srcPitch),
|
||||
buf + s2offset, buf + s3offset, pPriv->src_addr + (top * dstPitch),
|
||||
srcPitch, srcPitch2, dstPitch, nlines, width);
|
||||
} else {
|
||||
if (id == FOURCC_YV12) {
|
||||
tmp = s2offset;
|
||||
s2offset = s3offset;
|
||||
s3offset = tmp;
|
||||
}
|
||||
d2line = pPriv->planeu_offset + ((top >> 1) * dstPitch2);
|
||||
d3line = pPriv->planev_offset + ((top >> 1) * dstPitch2);
|
||||
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600) {
|
||||
R600CopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch),
|
||||
srcPitch, dstPitch, nlines, width, 1);
|
||||
R600CopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line,
|
||||
srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1);
|
||||
R600CopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line,
|
||||
srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1);
|
||||
} else {
|
||||
RADEONCopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch),
|
||||
srcPitch, dstPitch, nlines, width, 1);
|
||||
RADEONCopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line,
|
||||
srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1);
|
||||
RADEONCopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line,
|
||||
srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600)
|
||||
R600CopyData(pScrn, buf + (top * srcPitch),
|
||||
pPriv->src_addr + (top * dstPitch),
|
||||
srcPitch, dstPitch, nlines, width, 2);
|
||||
else
|
||||
RADEONCopyData(pScrn, buf + (top * srcPitch),
|
||||
pPriv->src_addr + (top * dstPitch),
|
||||
srcPitch, dstPitch, nlines, width, 2);
|
||||
break;
|
||||
}
|
||||
|
||||
/* update cliplist */
|
||||
if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
|
||||
REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
|
||||
}
|
||||
|
||||
pPriv->id = id;
|
||||
pPriv->src_w = src_w;
|
||||
pPriv->src_h = src_h;
|
||||
pPriv->src_x = src_x;
|
||||
pPriv->src_y = src_y;
|
||||
pPriv->drw_x = drw_x;
|
||||
pPriv->drw_y = drw_y;
|
||||
pPriv->dst_w = drw_w;
|
||||
pPriv->dst_h = drw_h;
|
||||
pPriv->w = width;
|
||||
pPriv->h = height;
|
||||
|
||||
radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]);
|
||||
if (info->directRenderingEnabled) {
|
||||
if (IS_EVERGREEN_3D)
|
||||
EVERGREENDisplayTexturedVideo(pScrn, pPriv);
|
||||
else if (IS_R600_3D)
|
||||
R600DisplayTexturedVideo(pScrn, pPriv);
|
||||
else if (IS_R500_3D)
|
||||
R500DisplayTexturedVideo(pScrn, pPriv);
|
||||
else if (IS_R300_3D)
|
||||
R300DisplayTexturedVideo(pScrn, pPriv);
|
||||
else if (IS_R200_3D)
|
||||
R200DisplayTexturedVideo(pScrn, pPriv);
|
||||
else
|
||||
RADEONDisplayTexturedVideo(pScrn, pPriv);
|
||||
}
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
/* client libraries expect an encoding */
|
||||
static XF86VideoEncodingRec DummyEncoding[1] =
|
||||
{
|
||||
{
|
||||
0,
|
||||
"XV_IMAGE",
|
||||
IMAGE_MAX_WIDTH, IMAGE_MAX_HEIGHT,
|
||||
{1, 1}
|
||||
}
|
||||
};
|
||||
|
||||
static XF86VideoEncodingRec DummyEncodingR500[1] =
|
||||
{
|
||||
{
|
||||
0,
|
||||
"XV_IMAGE",
|
||||
IMAGE_MAX_WIDTH_R500, IMAGE_MAX_HEIGHT_R500,
|
||||
{1, 1}
|
||||
}
|
||||
};
|
||||
|
||||
static XF86VideoEncodingRec DummyEncodingR600[1] =
|
||||
{
|
||||
{
|
||||
0,
|
||||
"XV_IMAGE",
|
||||
IMAGE_MAX_WIDTH_R600, IMAGE_MAX_HEIGHT_R600,
|
||||
{1, 1}
|
||||
}
|
||||
};
|
||||
|
||||
static XF86VideoEncodingRec DummyEncodingEG[1] =
|
||||
{
|
||||
{
|
||||
0,
|
||||
"XV_IMAGE",
|
||||
IMAGE_MAX_WIDTH_EG, IMAGE_MAX_HEIGHT_EG,
|
||||
{1, 1}
|
||||
}
|
||||
};
|
||||
|
||||
#define NUM_FORMATS 4
|
||||
|
||||
static XF86VideoFormatRec Formats[NUM_FORMATS] =
|
||||
{
|
||||
{15, TrueColor}, {16, TrueColor}, {24, TrueColor}, {30, TrueColor}
|
||||
};
|
||||
|
||||
#define NUM_ATTRIBUTES 2
|
||||
|
||||
static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1, 1, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#define NUM_ATTRIBUTES_R200 7
|
||||
|
||||
static XF86AttributeRec Attributes_r200[NUM_ATTRIBUTES_R200+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
|
||||
{XvSettable | XvGettable, -1, 1, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#define NUM_ATTRIBUTES_R300 9
|
||||
|
||||
static XF86AttributeRec Attributes_r300[NUM_ATTRIBUTES_R300+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 2, "XV_BICUBIC"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
|
||||
{XvSettable | XvGettable, 100, 10000, "XV_GAMMA"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
|
||||
{XvSettable | XvGettable, -1, 1, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#define NUM_ATTRIBUTES_R500 8
|
||||
|
||||
static XF86AttributeRec Attributes_r500[NUM_ATTRIBUTES_R500+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 2, "XV_BICUBIC"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
|
||||
{XvSettable | XvGettable, -1, 1, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#define NUM_ATTRIBUTES_R600 7
|
||||
|
||||
static XF86AttributeRec Attributes_r600[NUM_ATTRIBUTES_R600+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
|
||||
{XvSettable | XvGettable, -1, 1, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
static XF86AttributeRec Attributes_eg[NUM_ATTRIBUTES_R600+1] =
|
||||
{
|
||||
{XvSettable | XvGettable, 0, 1, "XV_VSYNC"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
|
||||
{XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
|
||||
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
|
||||
{XvSettable | XvGettable, -1, 5, "XV_CRTC"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
static Atom xvBicubic;
|
||||
static Atom xvVSync;
|
||||
static Atom xvBrightness, xvContrast, xvSaturation, xvHue;
|
||||
static Atom xvGamma, xvColorspace;
|
||||
static Atom xvCRTC;
|
||||
|
||||
#define NUM_IMAGES 4
|
||||
|
||||
static XF86ImageRec Images[NUM_IMAGES] =
|
||||
{
|
||||
XVIMAGE_YUY2,
|
||||
XVIMAGE_YV12,
|
||||
XVIMAGE_I420,
|
||||
XVIMAGE_UYVY
|
||||
};
|
||||
|
||||
int
|
||||
RADEONGetTexPortAttribute(ScrnInfoPtr pScrn,
|
||||
Atom attribute,
|
||||
INT32 *value,
|
||||
void *data)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
|
||||
|
||||
if (info->accelOn) RADEON_SYNC(info, pScrn);
|
||||
|
||||
if (attribute == xvBicubic)
|
||||
*value = pPriv->bicubic_state;
|
||||
else if (attribute == xvVSync)
|
||||
*value = pPriv->vsync;
|
||||
else if (attribute == xvBrightness)
|
||||
*value = pPriv->brightness;
|
||||
else if (attribute == xvContrast)
|
||||
*value = pPriv->contrast;
|
||||
else if (attribute == xvSaturation)
|
||||
*value = pPriv->saturation;
|
||||
else if (attribute == xvHue)
|
||||
*value = pPriv->hue;
|
||||
else if (attribute == xvGamma)
|
||||
*value = pPriv->gamma;
|
||||
else if(attribute == xvColorspace)
|
||||
*value = pPriv->transform_index;
|
||||
else if(attribute == xvCRTC) {
|
||||
int c;
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
|
||||
for (c = 0; c < xf86_config->num_crtc; c++)
|
||||
if (xf86_config->crtc[c] == pPriv->desired_crtc)
|
||||
break;
|
||||
if (c == xf86_config->num_crtc)
|
||||
c = -1;
|
||||
*value = c;
|
||||
} else
|
||||
return BadMatch;
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
int
|
||||
RADEONSetTexPortAttribute(ScrnInfoPtr pScrn,
|
||||
Atom attribute,
|
||||
INT32 value,
|
||||
void *data)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
|
||||
|
||||
RADEON_SYNC(info, pScrn);
|
||||
|
||||
if (attribute == xvBicubic)
|
||||
pPriv->bicubic_state = ClipValue (value, 0, 2);
|
||||
else if (attribute == xvVSync)
|
||||
pPriv->vsync = ClipValue (value, 0, 1);
|
||||
else if (attribute == xvBrightness)
|
||||
pPriv->brightness = ClipValue (value, -1000, 1000);
|
||||
else if (attribute == xvContrast)
|
||||
pPriv->contrast = ClipValue (value, -1000, 1000);
|
||||
else if (attribute == xvSaturation)
|
||||
pPriv->saturation = ClipValue (value, -1000, 1000);
|
||||
else if (attribute == xvHue)
|
||||
pPriv->hue = ClipValue (value, -1000, 1000);
|
||||
else if (attribute == xvGamma)
|
||||
pPriv->gamma = ClipValue (value, 100, 10000);
|
||||
else if(attribute == xvColorspace)
|
||||
pPriv->transform_index = ClipValue (value, 0, 1);
|
||||
else if(attribute == xvCRTC) {
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
|
||||
if ((value < -1) || (value > xf86_config->num_crtc))
|
||||
return BadValue;
|
||||
if (value < 0)
|
||||
pPriv->desired_crtc = NULL;
|
||||
else
|
||||
pPriv->desired_crtc = xf86_config->crtc[value];
|
||||
} else
|
||||
return BadMatch;
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int ret;
|
||||
/* Bicubic filter loading */
|
||||
ret = radeon_allocate_video_bo(pScrn,
|
||||
&info->bicubic_bo,
|
||||
sizeof(bicubic_tex_512), 64,
|
||||
RADEON_GEM_DOMAIN_VRAM);
|
||||
if (ret == FALSE)
|
||||
return FALSE;
|
||||
|
||||
/* Upload bicubic filter tex */
|
||||
if (info->ChipFamily < CHIP_FAMILY_R600) {
|
||||
uint8_t *bicubic_addr;
|
||||
int ret;
|
||||
ret = radeon_bo_map(info->bicubic_bo, 1);
|
||||
if (ret)
|
||||
return FALSE;
|
||||
|
||||
bicubic_addr = info->bicubic_bo->ptr;
|
||||
|
||||
RADEONCopySwap(bicubic_addr, (uint8_t *)bicubic_tex_512, 1024,
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
RADEON_HOST_DATA_SWAP_16BIT
|
||||
#else
|
||||
RADEON_HOST_DATA_SWAP_NONE
|
||||
#endif
|
||||
);
|
||||
radeon_bo_unmap(info->bicubic_bo);
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* XXX */
|
||||
static void radeon_unload_bicubic_texture(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
|
||||
if (info->bicubic_memory) {
|
||||
radeon_bo_unref(info->bicubic_memory);
|
||||
info->bicubic_memory = NULL;
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
RADEONQueryBestSize(
|
||||
ScrnInfoPtr pScrn,
|
||||
Bool motion,
|
||||
short vid_w, short vid_h,
|
||||
short drw_w, short drw_h,
|
||||
unsigned int *p_w, unsigned int *p_h,
|
||||
void *data
|
||||
){
|
||||
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
|
||||
|
||||
if (!pPriv->textured) {
|
||||
if (vid_w > (drw_w << 4))
|
||||
drw_w = vid_w >> 4;
|
||||
if (vid_h > (drw_h << 4))
|
||||
drw_h = vid_h >> 4;
|
||||
}
|
||||
|
||||
*p_w = drw_w;
|
||||
*p_h = drw_h;
|
||||
}
|
||||
|
||||
#define FOURCC_RGB24 0x00000000
|
||||
#define FOURCC_RGBT16 0x54424752
|
||||
#define FOURCC_RGB16 0x32424752
|
||||
#define FOURCC_RGBA32 0x41424752
|
||||
|
||||
static int
|
||||
RADEONQueryImageAttributes(
|
||||
ScrnInfoPtr pScrn,
|
||||
int id,
|
||||
unsigned short *w, unsigned short *h,
|
||||
int *pitches, int *offsets
|
||||
){
|
||||
const RADEONInfoRec * const info = RADEONPTR(pScrn);
|
||||
int size, tmp;
|
||||
|
||||
if(*w > info->xv_max_width) *w = info->xv_max_width;
|
||||
if(*h > info->xv_max_height) *h = info->xv_max_height;
|
||||
|
||||
*w = RADEON_ALIGN(*w, 2);
|
||||
if(offsets) offsets[0] = 0;
|
||||
|
||||
switch(id) {
|
||||
case FOURCC_YV12:
|
||||
case FOURCC_I420:
|
||||
*h = RADEON_ALIGN(*h, 2);
|
||||
size = RADEON_ALIGN(*w, 4);
|
||||
if(pitches) pitches[0] = size;
|
||||
size *= *h;
|
||||
if(offsets) offsets[1] = size;
|
||||
tmp = RADEON_ALIGN(*w >> 1, 4);
|
||||
if(pitches) pitches[1] = pitches[2] = tmp;
|
||||
tmp *= (*h >> 1);
|
||||
size += tmp;
|
||||
if(offsets) offsets[2] = size;
|
||||
size += tmp;
|
||||
break;
|
||||
case FOURCC_RGBA32:
|
||||
size = *w << 2;
|
||||
if(pitches) pitches[0] = size;
|
||||
size *= *h;
|
||||
break;
|
||||
case FOURCC_RGB24:
|
||||
size = *w * 3;
|
||||
if(pitches) pitches[0] = size;
|
||||
size *= *h;
|
||||
break;
|
||||
case FOURCC_RGBT16:
|
||||
case FOURCC_RGB16:
|
||||
case FOURCC_UYVY:
|
||||
case FOURCC_YUY2:
|
||||
default:
|
||||
size = *w << 1;
|
||||
if(pitches) pitches[0] = size;
|
||||
size *= *h;
|
||||
break;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
XF86VideoAdaptorPtr
|
||||
RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
RADEONPortPrivPtr pPortPriv;
|
||||
XF86VideoAdaptorPtr adapt;
|
||||
int i;
|
||||
int num_texture_ports = 16;
|
||||
|
||||
adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
|
||||
(sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
|
||||
if (!adapt)
|
||||
return NULL;
|
||||
|
||||
xvBicubic = MAKE_ATOM("XV_BICUBIC");
|
||||
xvVSync = MAKE_ATOM("XV_VSYNC");
|
||||
xvBrightness = MAKE_ATOM("XV_BRIGHTNESS");
|
||||
xvContrast = MAKE_ATOM("XV_CONTRAST");
|
||||
xvSaturation = MAKE_ATOM("XV_SATURATION");
|
||||
xvHue = MAKE_ATOM("XV_HUE");
|
||||
xvGamma = MAKE_ATOM("XV_GAMMA");
|
||||
xvColorspace = MAKE_ATOM("XV_COLORSPACE");
|
||||
xvCRTC = MAKE_ATOM("XV_CRTC");
|
||||
|
||||
adapt->type = XvWindowMask | XvInputMask | XvImageMask;
|
||||
adapt->flags = 0;
|
||||
adapt->name = "Radeon Textured Video";
|
||||
adapt->nEncodings = 1;
|
||||
if (IS_EVERGREEN_3D)
|
||||
adapt->pEncodings = DummyEncodingEG;
|
||||
else if (IS_R600_3D)
|
||||
adapt->pEncodings = DummyEncodingR600;
|
||||
else if (IS_R500_3D)
|
||||
adapt->pEncodings = DummyEncodingR500;
|
||||
else
|
||||
adapt->pEncodings = DummyEncoding;
|
||||
adapt->nFormats = NUM_FORMATS;
|
||||
adapt->pFormats = Formats;
|
||||
adapt->nPorts = num_texture_ports;
|
||||
adapt->pPortPrivates = (DevUnion*)(&adapt[1]);
|
||||
|
||||
pPortPriv =
|
||||
(RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]);
|
||||
|
||||
if (IS_EVERGREEN_3D) {
|
||||
adapt->pAttributes = Attributes_eg;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES_R600;
|
||||
}
|
||||
else if (IS_R600_3D) {
|
||||
adapt->pAttributes = Attributes_r600;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES_R600;
|
||||
}
|
||||
else if (IS_R500_3D) {
|
||||
adapt->pAttributes = Attributes_r500;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES_R500;
|
||||
}
|
||||
else if (IS_R300_3D) {
|
||||
adapt->pAttributes = Attributes_r300;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES_R300;
|
||||
}
|
||||
else if (IS_R200_3D) {
|
||||
adapt->pAttributes = Attributes_r200;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES_R200;
|
||||
}
|
||||
else {
|
||||
adapt->pAttributes = Attributes;
|
||||
adapt->nAttributes = NUM_ATTRIBUTES;
|
||||
}
|
||||
adapt->pImages = Images;
|
||||
adapt->nImages = NUM_IMAGES;
|
||||
adapt->PutVideo = NULL;
|
||||
adapt->PutStill = NULL;
|
||||
adapt->GetVideo = NULL;
|
||||
adapt->GetStill = NULL;
|
||||
adapt->StopVideo = RADEONStopVideo;
|
||||
adapt->SetPortAttribute = RADEONSetTexPortAttribute;
|
||||
adapt->GetPortAttribute = RADEONGetTexPortAttribute;
|
||||
adapt->QueryBestSize = RADEONQueryBestSize;
|
||||
adapt->PutImage = RADEONPutImageTextured;
|
||||
adapt->ReputImage = NULL;
|
||||
adapt->QueryImageAttributes = RADEONQueryImageAttributes;
|
||||
|
||||
for (i = 0; i < num_texture_ports; i++) {
|
||||
RADEONPortPrivPtr pPriv = &pPortPriv[i];
|
||||
|
||||
pPriv->textured = TRUE;
|
||||
pPriv->bicubic_state = BICUBIC_OFF;
|
||||
pPriv->vsync = TRUE;
|
||||
pPriv->brightness = 0;
|
||||
pPriv->contrast = 0;
|
||||
pPriv->saturation = 0;
|
||||
pPriv->hue = 0;
|
||||
pPriv->gamma = 1000;
|
||||
pPriv->transform_index = 0;
|
||||
pPriv->desired_crtc = NULL;
|
||||
|
||||
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
|
||||
REGION_NULL(pScreen, &pPriv->clip);
|
||||
adapt->pPortPrivates[i].ptr = (void*) (pPriv);
|
||||
}
|
||||
|
||||
if (IS_R500_3D || IS_R300_3D)
|
||||
radeon_load_bicubic_texture(pScrn);
|
||||
|
||||
info->xv_max_width = adapt->pEncodings->width;
|
||||
info->xv_max_height = adapt->pEncodings->height;
|
||||
|
||||
return adapt;
|
||||
}
|
||||
|
||||
3869
src/radeon_textured_videofuncs.c
Normal file
3869
src/radeon_textured_videofuncs.c
Normal file
File diff suppressed because it is too large
Load diff
209
src/radeon_vbo.c
Normal file
209
src/radeon_vbo.c
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* Copyright © 2009 Red Hat, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Dave Airlie <airlied@redhat.com>
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <errno.h>
|
||||
#include "radeon.h"
|
||||
#include "radeon_bo.h"
|
||||
#include "radeon_cs.h"
|
||||
|
||||
#define VBO_SIZE (16*1024)
|
||||
|
||||
/* KMS vertex buffer support - for R600 only but could be used on previous gpus */
|
||||
|
||||
static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn);
|
||||
|
||||
void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
|
||||
{
|
||||
|
||||
if (vbo->vb_bo) {
|
||||
radeon_bo_unmap(vbo->vb_bo);
|
||||
radeon_bo_unref(vbo->vb_bo);
|
||||
vbo->vb_bo = NULL;
|
||||
vbo->vb_total = 0;
|
||||
}
|
||||
|
||||
vbo->vb_offset = 0;
|
||||
}
|
||||
|
||||
void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
|
||||
{
|
||||
int ret;
|
||||
|
||||
vbo->vb_bo = radeon_vbo_get_bo(pScrn);
|
||||
if (vbo->vb_bo) {
|
||||
radeon_bo_ref(vbo->vb_bo);
|
||||
ret = radeon_bo_map(vbo->vb_bo, 1);
|
||||
if (ret)
|
||||
FatalError("Failed to map vb %d\n", ret);
|
||||
}
|
||||
|
||||
vbo->vb_total = VBO_SIZE;
|
||||
vbo->vb_offset = 0;
|
||||
vbo->vb_start_op = vbo->vb_offset;
|
||||
}
|
||||
|
||||
/* these functions could migrate to libdrm and
|
||||
be shared with the radeon 3D driver */
|
||||
static int radeon_bo_is_idle(struct radeon_bo *bo)
|
||||
{
|
||||
uint32_t domain;
|
||||
int ret = radeon_bo_is_busy(bo, &domain);
|
||||
return ret != -EBUSY;
|
||||
}
|
||||
|
||||
void radeon_vbo_init_lists(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
|
||||
accel_state->use_vbos = TRUE;
|
||||
make_empty_list(&accel_state->bo_free);
|
||||
make_empty_list(&accel_state->bo_wait);
|
||||
make_empty_list(&accel_state->bo_reserved);
|
||||
}
|
||||
|
||||
void radeon_vbo_free_lists(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
struct radeon_dma_bo *dma_bo, *temp;
|
||||
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_free) {
|
||||
remove_from_list(dma_bo);
|
||||
radeon_bo_unref(dma_bo->bo);
|
||||
free(dma_bo);
|
||||
}
|
||||
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_wait) {
|
||||
remove_from_list(dma_bo);
|
||||
radeon_bo_unref(dma_bo->bo);
|
||||
free(dma_bo);
|
||||
}
|
||||
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_reserved) {
|
||||
remove_from_list(dma_bo);
|
||||
radeon_bo_unref(dma_bo->bo);
|
||||
free(dma_bo);
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_vbo_flush_bos(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
struct radeon_dma_bo *dma_bo, *temp;
|
||||
const int expire_at = ++accel_state->bo_free.expire_counter + DMA_BO_FREE_TIME;
|
||||
const int time = accel_state->bo_free.expire_counter;
|
||||
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_wait) {
|
||||
if (dma_bo->expire_counter == time) {
|
||||
ErrorF("leaking dma buffer\n");
|
||||
while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {}
|
||||
remove_from_list(dma_bo);
|
||||
free(dma_bo);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!radeon_bo_is_idle(dma_bo->bo))
|
||||
continue;
|
||||
|
||||
if (dma_bo->bo->ptr) {
|
||||
ErrorF("bo with pointer on wait list!\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
remove_from_list(dma_bo);
|
||||
dma_bo->expire_counter = expire_at;
|
||||
insert_at_tail(&accel_state->bo_free, dma_bo);
|
||||
}
|
||||
|
||||
/* move reserved to wait list */
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_reserved) {
|
||||
remove_from_list(dma_bo);
|
||||
dma_bo->expire_counter = expire_at;
|
||||
insert_at_tail(&accel_state->bo_wait, dma_bo);
|
||||
}
|
||||
|
||||
/* free bos that have been unused */
|
||||
foreach_s(dma_bo, temp, &accel_state->bo_free) {
|
||||
if (dma_bo->expire_counter != time)
|
||||
break;
|
||||
/* always keep one hanging around at end */
|
||||
if (at_end(&accel_state->bo_free, dma_bo)) {
|
||||
dma_bo->expire_counter = time + DMA_BO_FREE_TIME;
|
||||
break;
|
||||
}
|
||||
|
||||
remove_from_list(dma_bo);
|
||||
radeon_bo_unref(dma_bo->bo);
|
||||
free(dma_bo);
|
||||
}
|
||||
}
|
||||
|
||||
static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn)
|
||||
{
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
struct radeon_accel_state *accel_state = info->accel_state;
|
||||
struct radeon_dma_bo *dma_bo = NULL;
|
||||
struct radeon_bo *bo;
|
||||
|
||||
if (is_empty_list(&accel_state->bo_free)) {
|
||||
dma_bo = calloc(1, sizeof(struct radeon_dma_bo));
|
||||
if (!dma_bo)
|
||||
return NULL;
|
||||
|
||||
again_alloc:
|
||||
dma_bo->bo = radeon_bo_open(info->bufmgr, 0, VBO_SIZE,
|
||||
0, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
|
||||
if (!dma_bo->bo) {
|
||||
ErrorF("failure to allocate DMA BO\n");
|
||||
free(dma_bo);
|
||||
return NULL;
|
||||
}
|
||||
insert_at_head(&accel_state->bo_reserved, dma_bo);
|
||||
} else {
|
||||
dma_bo = last_elem(&accel_state->bo_free);
|
||||
remove_from_list(dma_bo);
|
||||
insert_at_head(&accel_state->bo_reserved, dma_bo);
|
||||
}
|
||||
|
||||
if (is_empty_list(&accel_state->bo_reserved))
|
||||
goto again_alloc;
|
||||
|
||||
bo = first_elem(&accel_state->bo_reserved)->bo;
|
||||
|
||||
/* need a space check */
|
||||
if (radeon_cs_space_check_with_bo(info->cs,
|
||||
bo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0))
|
||||
ErrorF("failed to revalidate\n");
|
||||
|
||||
return bo;
|
||||
}
|
||||
|
||||
45
src/radeon_vbo.h
Normal file
45
src/radeon_vbo.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
#ifndef RADEON_VBO_H
|
||||
#define RADEON_VBO_H
|
||||
|
||||
extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);
|
||||
extern void radeon_vbo_init_lists(ScrnInfoPtr pScrn);
|
||||
extern void radeon_vbo_free_lists(ScrnInfoPtr pScrn);
|
||||
extern void radeon_vbo_flush_bos(ScrnInfoPtr pScrn);
|
||||
extern void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo);
|
||||
extern void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo);
|
||||
|
||||
static inline void radeon_vbo_check(ScrnInfoPtr pScrn,
|
||||
struct radeon_vbo_object *vbo,
|
||||
int vert_size)
|
||||
{
|
||||
|
||||
if ((vbo->vb_offset + (vbo->verts_per_op * vert_size)) > vbo->vb_total) {
|
||||
radeon_vb_no_space(pScrn, vbo, vert_size);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void *
|
||||
radeon_vbo_space(ScrnInfoPtr pScrn,
|
||||
struct radeon_vbo_object *vbo,
|
||||
int vert_size)
|
||||
{
|
||||
void *vb;
|
||||
|
||||
/* we've ran out of space in the vertex buffer - need to get a
|
||||
new one */
|
||||
radeon_vbo_check(pScrn, vbo, vert_size);
|
||||
|
||||
vbo->vb_op_vert_size = vert_size;
|
||||
vb = (void*)((char *)vbo->vb_bo->ptr + vbo->vb_offset);
|
||||
return vb;
|
||||
}
|
||||
|
||||
static inline void radeon_vbo_commit(ScrnInfoPtr pScrn,
|
||||
struct radeon_vbo_object *vbo)
|
||||
{
|
||||
|
||||
vbo->vb_offset += vbo->verts_per_op * vbo->vb_op_vert_size;
|
||||
}
|
||||
|
||||
#endif
|
||||
64
src/radeon_version.h
Normal file
64
src/radeon_version.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and its
|
||||
* documentation for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice appear in all copies and that both that copyright
|
||||
* notice and this permission notice appear in supporting documentation, and
|
||||
* that the name of Marc Aurele La France not be used in advertising or
|
||||
* publicity pertaining to distribution of the software without specific,
|
||||
* written prior permission. Marc Aurele La France makes no representations
|
||||
* about the suitability of this software for any purpose. It is provided
|
||||
* "as-is" without express or implied warranty.
|
||||
*
|
||||
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
|
||||
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
|
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RADEON_VERSION_H_
|
||||
#define _RADEON_VERSION_H_ 1
|
||||
|
||||
#undef RADEON_NAME
|
||||
#undef RADEON_DRIVER_NAME
|
||||
#undef R200_DRIVER_NAME
|
||||
#undef RADEON_VERSION_MAJOR
|
||||
#undef RADEON_VERSION_MINOR
|
||||
#undef RADEON_VERSION_PATCH
|
||||
#undef RADEON_VERSION_CURRENT
|
||||
#undef RADEON_VERSION_EVALUATE
|
||||
#undef RADEON_VERSION_STRINGIFY
|
||||
#undef RADEON_VERSION_NAME
|
||||
|
||||
#define RADEON_NAME "RADEON"
|
||||
#define RADEON_DRIVER_NAME "radeon"
|
||||
#define R200_DRIVER_NAME "r200"
|
||||
#define R300_DRIVER_NAME "r300"
|
||||
#define R600_DRIVER_NAME "r600"
|
||||
#define SI_DRIVER_NAME "radeonsi"
|
||||
|
||||
#define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR
|
||||
#define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR
|
||||
#define RADEON_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
|
||||
|
||||
#ifndef RADEON_VERSION_EXTRA
|
||||
#define RADEON_VERSION_EXTRA ""
|
||||
#endif
|
||||
|
||||
#define RADEON_VERSION_CURRENT \
|
||||
((RADEON_VERSION_MAJOR << 20) | \
|
||||
(RADEON_VERSION_MINOR << 10) | \
|
||||
(RADEON_VERSION_PATCH))
|
||||
|
||||
#define RADEON_VERSION_EVALUATE(__x) #__x
|
||||
#define RADEON_VERSION_STRINGIFY(_x) RADEON_VERSION_EVALUATE(_x)
|
||||
#define RADEON_VERSION_NAME \
|
||||
RADEON_VERSION_STRINGIFY(RADEON_VERSION_MAJOR) "." \
|
||||
RADEON_VERSION_STRINGIFY(RADEON_VERSION_MINOR) "." \
|
||||
RADEON_VERSION_STRINGIFY(RADEON_VERSION_PATCH) RADEON_VERSION_EXTRA
|
||||
|
||||
#endif /* _RADEON_VERSION_H_ */
|
||||
272
src/radeon_video.c
Normal file
272
src/radeon_video.c
Normal file
|
|
@ -0,0 +1,272 @@
|
|||
#include "config.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_glamor.h"
|
||||
#include "radeon_reg.h"
|
||||
#include "radeon_probe.h"
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include "xf86.h"
|
||||
#include "dixstruct.h"
|
||||
|
||||
/* DPMS */
|
||||
#include <X11/extensions/dpmsconst.h>
|
||||
|
||||
#include <X11/extensions/Xv.h>
|
||||
#include "fourcc.h"
|
||||
|
||||
#define OFF_DELAY 250 /* milliseconds */
|
||||
#define FREE_DELAY 15000
|
||||
|
||||
#define OFF_TIMER 0x01
|
||||
#define FREE_TIMER 0x02
|
||||
#define CLIENT_VIDEO_ON 0x04
|
||||
|
||||
#define GET_PORT_PRIVATE(pScrn) \
|
||||
(RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
|
||||
|
||||
static void
|
||||
radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b)
|
||||
{
|
||||
dest->x1 = a->x1 > b->x1 ? a->x1 : b->x1;
|
||||
dest->x2 = a->x2 < b->x2 ? a->x2 : b->x2;
|
||||
dest->y1 = a->y1 > b->y1 ? a->y1 : b->y1;
|
||||
dest->y2 = a->y2 < b->y2 ? a->y2 : b->y2;
|
||||
|
||||
if (dest->x1 >= dest->x2 || dest->y1 >= dest->y2)
|
||||
dest->x1 = dest->x2 = dest->y1 = dest->y2 = 0;
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box)
|
||||
{
|
||||
if (crtc->enabled) {
|
||||
crtc_box->x1 = crtc->x;
|
||||
crtc_box->x2 = crtc->x + xf86ModeWidth(&crtc->mode, crtc->rotation);
|
||||
crtc_box->y1 = crtc->y;
|
||||
crtc_box->y2 = crtc->y + xf86ModeHeight(&crtc->mode, crtc->rotation);
|
||||
} else
|
||||
crtc_box->x1 = crtc_box->x2 = crtc_box->y1 = crtc_box->y2 = 0;
|
||||
}
|
||||
|
||||
static int
|
||||
radeon_box_area(BoxPtr box)
|
||||
{
|
||||
return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1);
|
||||
}
|
||||
|
||||
Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc)
|
||||
{
|
||||
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
|
||||
return drmmode_crtc->dpms_mode == DPMSModeOn;
|
||||
}
|
||||
|
||||
xf86CrtcPtr
|
||||
radeon_pick_best_crtc(ScrnInfoPtr pScrn, Bool consider_disabled,
|
||||
int x1, int x2, int y1, int y2)
|
||||
{
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
|
||||
int coverage, best_coverage, c, cd;
|
||||
BoxRec box, crtc_box, cover_box;
|
||||
RROutputPtr primary_output = NULL;
|
||||
xf86CrtcPtr best_crtc = NULL, primary_crtc = NULL;
|
||||
|
||||
if (!pScrn->vtSema)
|
||||
return NULL;
|
||||
|
||||
box.x1 = x1;
|
||||
box.x2 = x2;
|
||||
box.y1 = y1;
|
||||
box.y2 = y2;
|
||||
best_coverage = 0;
|
||||
|
||||
/* Prefer the CRTC of the primary output */
|
||||
if (dixPrivateKeyRegistered(rrPrivKey))
|
||||
{
|
||||
primary_output = RRFirstOutput(pScrn->pScreen);
|
||||
}
|
||||
if (primary_output && primary_output->crtc)
|
||||
primary_crtc = primary_output->crtc->devPrivate;
|
||||
|
||||
/* first consider only enabled CRTCs
|
||||
* then on second pass consider disabled ones
|
||||
*/
|
||||
for (cd = 0; cd < (consider_disabled ? 2 : 1); cd++) {
|
||||
for (c = 0; c < xf86_config->num_crtc; c++) {
|
||||
xf86CrtcPtr crtc = xf86_config->crtc[c];
|
||||
|
||||
if (!cd && !radeon_crtc_is_enabled(crtc))
|
||||
continue;
|
||||
|
||||
radeon_crtc_box(crtc, &crtc_box);
|
||||
radeon_box_intersect(&cover_box, &crtc_box, &box);
|
||||
coverage = radeon_box_area(&cover_box);
|
||||
if (coverage > best_coverage ||
|
||||
(coverage == best_coverage &&
|
||||
crtc == primary_crtc)) {
|
||||
best_crtc = crtc;
|
||||
best_coverage = coverage;
|
||||
}
|
||||
}
|
||||
if (best_crtc)
|
||||
break;
|
||||
}
|
||||
|
||||
return best_crtc;
|
||||
}
|
||||
|
||||
|
||||
void RADEONInitVideo(ScreenPtr pScreen)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
|
||||
XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL;
|
||||
XF86VideoAdaptorPtr texturedAdaptor = NULL;
|
||||
int num_adaptors;
|
||||
|
||||
/* no overlay or 3D on RN50 */
|
||||
if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2)
|
||||
return;
|
||||
|
||||
num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors);
|
||||
newAdaptors = malloc((num_adaptors + 2) * sizeof(*newAdaptors));
|
||||
if (!newAdaptors)
|
||||
return;
|
||||
|
||||
memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
|
||||
adaptors = newAdaptors;
|
||||
|
||||
if (info->use_glamor) {
|
||||
texturedAdaptor = radeon_glamor_xv_init(pScreen, 16);
|
||||
if (texturedAdaptor) {
|
||||
adaptors[num_adaptors++] = texturedAdaptor;
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video (glamor)\n");
|
||||
} else
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video (glamor)\n");
|
||||
} else if ((info->ChipFamily < CHIP_FAMILY_RS400)
|
||||
|| (info->directRenderingEnabled)
|
||||
) {
|
||||
texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
|
||||
if (texturedAdaptor) {
|
||||
adaptors[num_adaptors++] = texturedAdaptor;
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
|
||||
} else
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
|
||||
} else
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n");
|
||||
|
||||
if(num_adaptors)
|
||||
xf86XVScreenInit(pScreen, adaptors, num_adaptors);
|
||||
|
||||
if(texturedAdaptor) {
|
||||
XF86MCAdaptorPtr xvmcAdaptor = RADEONCreateAdaptorXvMC(pScreen, (char *)texturedAdaptor->name);
|
||||
if(xvmcAdaptor) {
|
||||
if(!xf86XvMCScreenInit(pScreen, 1, &xvmcAdaptor))
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[XvMC] Failed to initialize extension.\n");
|
||||
else
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[XvMC] Extension initialized.\n");
|
||||
}
|
||||
}
|
||||
|
||||
if(newAdaptors)
|
||||
free(newAdaptors);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
RADEONCopyData(
|
||||
ScrnInfoPtr pScrn,
|
||||
unsigned char *src,
|
||||
unsigned char *dst,
|
||||
unsigned int srcPitch,
|
||||
unsigned int dstPitch,
|
||||
unsigned int h,
|
||||
unsigned int w,
|
||||
unsigned int bpp
|
||||
){
|
||||
/* Get the byte-swapping right for big endian systems */
|
||||
if ( bpp == 2 ) {
|
||||
w *= 2;
|
||||
bpp = 1;
|
||||
}
|
||||
|
||||
{
|
||||
int swap = RADEON_HOST_DATA_SWAP_NONE;
|
||||
|
||||
#if X_BYTE_ORDER == X_BIG_ENDIAN
|
||||
switch(bpp) {
|
||||
case 2:
|
||||
swap = RADEON_HOST_DATA_SWAP_16BIT;
|
||||
break;
|
||||
case 4:
|
||||
swap = RADEON_HOST_DATA_SWAP_32BIT;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
w *= bpp;
|
||||
|
||||
if (dstPitch == w && dstPitch == srcPitch)
|
||||
RADEONCopySwap(dst, src, h * dstPitch, swap);
|
||||
else {
|
||||
while (h--) {
|
||||
RADEONCopySwap(dst, src, w, swap);
|
||||
src += srcPitch;
|
||||
dst += dstPitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
RADEONCopyMungedData(
|
||||
ScrnInfoPtr pScrn,
|
||||
unsigned char *src1,
|
||||
unsigned char *src2,
|
||||
unsigned char *src3,
|
||||
unsigned char *dst1,
|
||||
unsigned int srcPitch,
|
||||
unsigned int srcPitch2,
|
||||
unsigned int dstPitch,
|
||||
unsigned int h,
|
||||
unsigned int w
|
||||
){
|
||||
uint32_t *dst;
|
||||
uint8_t *s1, *s2, *s3;
|
||||
int i, j;
|
||||
|
||||
w /= 2;
|
||||
|
||||
for( j = 0; j < h; j++ ) {
|
||||
dst = (void*)dst1;
|
||||
s1 = src1; s2 = src2; s3 = src3;
|
||||
i = w;
|
||||
while( i > 4 ) {
|
||||
dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24));
|
||||
dst[1] = cpu_to_le32(s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24));
|
||||
dst[2] = cpu_to_le32(s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24));
|
||||
dst[3] = cpu_to_le32(s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24));
|
||||
dst += 4; s2 += 4; s3 += 4; s1 += 8;
|
||||
i -= 4;
|
||||
}
|
||||
while( i-- ) {
|
||||
dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24));
|
||||
dst++; s2++; s3++;
|
||||
s1 += 2;
|
||||
}
|
||||
|
||||
dst1 += dstPitch;
|
||||
src1 += srcPitch;
|
||||
if( j & 1 ) {
|
||||
src2 += srcPitch2;
|
||||
src3 += srcPitch2;
|
||||
}
|
||||
}
|
||||
}
|
||||
103
src/radeon_video.h
Normal file
103
src/radeon_video.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
#ifndef __RADEON_VIDEO_H__
|
||||
#define __RADEON_VIDEO_H__
|
||||
|
||||
#include "xf86i2c.h"
|
||||
#include "xf86Crtc.h"
|
||||
|
||||
#include "bicubic_table.h"
|
||||
|
||||
#include <xf86xvmc.h>
|
||||
|
||||
#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v))
|
||||
|
||||
/* Xvideo port struct */
|
||||
typedef struct {
|
||||
uint32_t transform_index;
|
||||
uint32_t gamma; /* gamma value x 1000 */
|
||||
int brightness;
|
||||
int saturation;
|
||||
int hue;
|
||||
int contrast;
|
||||
|
||||
unsigned char currentBuffer;
|
||||
RegionRec clip;
|
||||
|
||||
Time offTime;
|
||||
Time freeTime;
|
||||
xf86CrtcPtr desired_crtc;
|
||||
|
||||
int size;
|
||||
|
||||
struct radeon_bo *video_memory;
|
||||
|
||||
int planeu_offset;
|
||||
int planev_offset;
|
||||
|
||||
/* bicubic filtering */
|
||||
Bool bicubic_enabled;
|
||||
int bicubic_state;
|
||||
#define BICUBIC_OFF 0
|
||||
#define BICUBIC_ON 1
|
||||
#define BICUBIC_AUTO 2
|
||||
|
||||
/* textured video */
|
||||
Bool textured;
|
||||
DrawablePtr pDraw;
|
||||
PixmapPtr pPixmap;
|
||||
|
||||
uint32_t src_pitch;
|
||||
uint8_t *src_addr;
|
||||
|
||||
int id;
|
||||
int src_w, src_h, dst_w, dst_h;
|
||||
int w, h;
|
||||
int drw_x, drw_y;
|
||||
int src_x, src_y;
|
||||
int vsync;
|
||||
Bool is_planar;
|
||||
int vtx_count;
|
||||
int hw_align;
|
||||
|
||||
struct radeon_bo *src_bo[2];
|
||||
} RADEONPortPrivRec, *RADEONPortPrivPtr;
|
||||
|
||||
/* Reference color space transform data */
|
||||
typedef struct tagREF_TRANSFORM
|
||||
{
|
||||
float RefLuma;
|
||||
float RefRCb;
|
||||
float RefRCr;
|
||||
float RefGCb;
|
||||
float RefGCr;
|
||||
float RefBCb;
|
||||
float RefBCr;
|
||||
} REF_TRANSFORM;
|
||||
|
||||
#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0)
|
||||
#define RTFBrightness(a) (((a)*1.0)/2000.0)
|
||||
#define RTFIntensity(a) (((a)*1.0)/2000.0)
|
||||
#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0)
|
||||
#define RTFHue(a) (((a)*3.1416)/1000.0)
|
||||
|
||||
XF86VideoAdaptorPtr
|
||||
RADEONSetupImageTexturedVideo(ScreenPtr pScreen);
|
||||
|
||||
XF86MCAdaptorPtr
|
||||
RADEONCreateAdaptorXvMC(ScreenPtr pScreen, char *xv_adaptor_name);
|
||||
|
||||
void
|
||||
RADEONCopyData(ScrnInfoPtr pScrn,
|
||||
unsigned char *src, unsigned char *dst,
|
||||
unsigned int srcPitch, unsigned int dstPitch,
|
||||
unsigned int h, unsigned int w, unsigned int bpp);
|
||||
|
||||
void
|
||||
RADEONCopyMungedData(ScrnInfoPtr pScrn,
|
||||
unsigned char *src1, unsigned char *src2,
|
||||
unsigned char *src3, unsigned char *dst1,
|
||||
unsigned int srcPitch, unsigned int srcPitch2,
|
||||
unsigned int dstPitch, unsigned int h, unsigned int w);
|
||||
|
||||
Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc);
|
||||
|
||||
#endif
|
||||
141
src/radeon_xvmc.c
Normal file
141
src/radeon_xvmc.c
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright 2010 Christian König
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
*
|
||||
* Based on vl_hwmc.c from xf86-video-nouveau
|
||||
*
|
||||
*/
|
||||
#include "config.h"
|
||||
|
||||
#include <xf86.h>
|
||||
#include "radeon_video.h"
|
||||
|
||||
#include <X11/extensions/Xv.h>
|
||||
#include <X11/extensions/XvMC.h>
|
||||
#include "fourcc.h"
|
||||
|
||||
#define FOURCC_RGB 0x0000003
|
||||
|
||||
static int subpicture_index_list[] =
|
||||
{
|
||||
FOURCC_RGB,
|
||||
FOURCC_IA44,
|
||||
FOURCC_AI44
|
||||
};
|
||||
|
||||
static XF86MCImageIDList subpicture_list =
|
||||
{
|
||||
3,
|
||||
subpicture_index_list
|
||||
};
|
||||
|
||||
static XF86MCSurfaceInfoRec yv12_mpeg2_surface =
|
||||
{
|
||||
FOURCC_YV12,
|
||||
XVMC_CHROMA_FORMAT_420,
|
||||
0,
|
||||
2048,
|
||||
2048,
|
||||
2048,
|
||||
2048,
|
||||
XVMC_IDCT | XVMC_MOCOMP | XVMC_MPEG_2,
|
||||
XVMC_SUBPICTURE_INDEPENDENT_SCALING | XVMC_BACKEND_SUBPICTURE,
|
||||
&subpicture_list
|
||||
};
|
||||
|
||||
static XF86MCSurfaceInfoPtr surfaces[] =
|
||||
{
|
||||
(XF86MCSurfaceInfoPtr)&yv12_mpeg2_surface,
|
||||
};
|
||||
|
||||
static XF86ImageRec rgb_subpicture =
|
||||
{
|
||||
FOURCC_RGB,
|
||||
XvRGB,
|
||||
LSBFirst,
|
||||
{
|
||||
'R', 'G', 'B', 0x00,
|
||||
0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
|
||||
},
|
||||
32,
|
||||
XvPacked,
|
||||
1,
|
||||
24, 0x00FF0000, 0x0000FF00, 0x000000FF,
|
||||
0, 0, 0,
|
||||
0, 0, 0,
|
||||
0, 0, 0,
|
||||
{
|
||||
'B','G','R','X',
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
},
|
||||
XvTopToBottom
|
||||
};
|
||||
|
||||
static XF86ImageRec ia44_subpicture = XVIMAGE_IA44;
|
||||
static XF86ImageRec ai44_subpicture = XVIMAGE_AI44;
|
||||
|
||||
static XF86ImagePtr subpictures[] =
|
||||
{
|
||||
(XF86ImagePtr)&rgb_subpicture,
|
||||
(XF86ImagePtr)&ia44_subpicture,
|
||||
(XF86ImagePtr)&ai44_subpicture
|
||||
};
|
||||
|
||||
static XF86MCAdaptorRec adaptor_template =
|
||||
{
|
||||
"",
|
||||
1,
|
||||
surfaces,
|
||||
3,
|
||||
subpictures,
|
||||
(xf86XvMCCreateContextProcPtr)NULL,
|
||||
(xf86XvMCDestroyContextProcPtr)NULL,
|
||||
(xf86XvMCCreateSurfaceProcPtr)NULL,
|
||||
(xf86XvMCDestroySurfaceProcPtr)NULL,
|
||||
(xf86XvMCCreateSubpictureProcPtr)NULL,
|
||||
(xf86XvMCDestroySubpictureProcPtr)NULL
|
||||
};
|
||||
|
||||
XF86MCAdaptorPtr
|
||||
RADEONCreateAdaptorXvMC(ScreenPtr pScreen, char *xv_adaptor_name)
|
||||
{
|
||||
XF86MCAdaptorPtr adaptor;
|
||||
ScrnInfoPtr pScrn;
|
||||
|
||||
assert(pScreen);
|
||||
|
||||
pScrn = xf86ScreenToScrn(pScreen);
|
||||
adaptor = xf86XvMCCreateAdaptorRec();
|
||||
|
||||
if (!adaptor)
|
||||
{
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[XvMC] Memory allocation failed.\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
*adaptor = adaptor_template;
|
||||
adaptor->name = xv_adaptor_name;
|
||||
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[XvMC] Associated with %s.\n", adaptor->name);
|
||||
|
||||
return adaptor;
|
||||
}
|
||||
202
src/simple_list.h
Normal file
202
src/simple_list.h
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/**
|
||||
* \file simple_list.h
|
||||
* Simple macros for type-safe, intrusive lists.
|
||||
*
|
||||
* Intended to work with a list sentinel which is created as an empty
|
||||
* list. Insert & delete are O(1).
|
||||
*
|
||||
* \author
|
||||
* (C) 1997, Keith Whitwell
|
||||
*/
|
||||
|
||||
/*
|
||||
* Mesa 3-D graphics library
|
||||
* Version: 3.5
|
||||
*
|
||||
* Copyright (C) 1999-2001 Brian Paul All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SIMPLE_LIST_H
|
||||
#define _SIMPLE_LIST_H
|
||||
|
||||
struct simple_node {
|
||||
struct simple_node *next;
|
||||
struct simple_node *prev;
|
||||
};
|
||||
|
||||
/**
|
||||
* Remove an element from list.
|
||||
*
|
||||
* \param elem element to remove.
|
||||
*/
|
||||
#define remove_from_list(elem) \
|
||||
do { \
|
||||
(elem)->next->prev = (elem)->prev; \
|
||||
(elem)->prev->next = (elem)->next; \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* Insert an element to the list head.
|
||||
*
|
||||
* \param list list.
|
||||
* \param elem element to insert.
|
||||
*/
|
||||
#define insert_at_head(list, elem) \
|
||||
do { \
|
||||
(elem)->prev = list; \
|
||||
(elem)->next = (list)->next; \
|
||||
(list)->next->prev = elem; \
|
||||
(list)->next = elem; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* Insert an element to the list tail.
|
||||
*
|
||||
* \param list list.
|
||||
* \param elem element to insert.
|
||||
*/
|
||||
#define insert_at_tail(list, elem) \
|
||||
do { \
|
||||
(elem)->next = list; \
|
||||
(elem)->prev = (list)->prev; \
|
||||
(list)->prev->next = elem; \
|
||||
(list)->prev = elem; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* Move an element to the list head.
|
||||
*
|
||||
* \param list list.
|
||||
* \param elem element to move.
|
||||
*/
|
||||
#define move_to_head(list, elem) \
|
||||
do { \
|
||||
remove_from_list(elem); \
|
||||
insert_at_head(list, elem); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* Move an element to the list tail.
|
||||
*
|
||||
* \param list list.
|
||||
* \param elem element to move.
|
||||
*/
|
||||
#define move_to_tail(list, elem) \
|
||||
do { \
|
||||
remove_from_list(elem); \
|
||||
insert_at_tail(list, elem); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* Make a empty list empty.
|
||||
*
|
||||
* \param sentinel list (sentinel element).
|
||||
*/
|
||||
#define make_empty_list(sentinel) \
|
||||
do { \
|
||||
(sentinel)->next = sentinel; \
|
||||
(sentinel)->prev = sentinel; \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* Get list first element.
|
||||
*
|
||||
* \param list list.
|
||||
*
|
||||
* \return pointer to first element.
|
||||
*/
|
||||
#define first_elem(list) ((list)->next)
|
||||
|
||||
/**
|
||||
* Get list last element.
|
||||
*
|
||||
* \param list list.
|
||||
*
|
||||
* \return pointer to last element.
|
||||
*/
|
||||
#define last_elem(list) ((list)->prev)
|
||||
|
||||
/**
|
||||
* Get next element.
|
||||
*
|
||||
* \param elem element.
|
||||
*
|
||||
* \return pointer to next element.
|
||||
*/
|
||||
#define next_elem(elem) ((elem)->next)
|
||||
|
||||
/**
|
||||
* Get previous element.
|
||||
*
|
||||
* \param elem element.
|
||||
*
|
||||
* \return pointer to previous element.
|
||||
*/
|
||||
#define prev_elem(elem) ((elem)->prev)
|
||||
|
||||
/**
|
||||
* Test whether element is at end of the list.
|
||||
*
|
||||
* \param list list.
|
||||
* \param elem element.
|
||||
*
|
||||
* \return non-zero if element is at end of list, or zero otherwise.
|
||||
*/
|
||||
#define at_end(list, elem) ((elem) == (list))
|
||||
|
||||
/**
|
||||
* Test if a list is empty.
|
||||
*
|
||||
* \param list list.
|
||||
*
|
||||
* \return non-zero if list empty, or zero otherwise.
|
||||
*/
|
||||
#define is_empty_list(list) ((list)->next == (list))
|
||||
|
||||
/**
|
||||
* Walk through the elements of a list.
|
||||
*
|
||||
* \param ptr pointer to the current element.
|
||||
* \param list list.
|
||||
*
|
||||
* \note It should be followed by a { } block or a single statement, as in a \c
|
||||
* for loop.
|
||||
*/
|
||||
#define foreach(ptr, list) \
|
||||
for( ptr=(list)->next ; ptr!=list ; ptr=(ptr)->next )
|
||||
|
||||
/**
|
||||
* Walk through the elements of a list.
|
||||
*
|
||||
* Same as #foreach but lets you unlink the current value during a list
|
||||
* traversal. Useful for freeing a list, element by element.
|
||||
*
|
||||
* \param ptr pointer to the current element.
|
||||
* \param t temporary pointer.
|
||||
* \param list list.
|
||||
*
|
||||
* \note It should be followed by a { } block or a single statement, as in a \c
|
||||
* for loop.
|
||||
*/
|
||||
#define foreach_s(ptr, t, list) \
|
||||
for(ptr=(list)->next,t=(ptr)->next; list != ptr; ptr=t, t=(t)->next)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue