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Add initial EXA and Xv support for evergreen

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Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases.  We haven't
tracked down why yet.  Might be related to constant
buffer persistence.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
This commit is contained in:
Alex Deucher 2010-08-20 16:55:21 -04:00
commit 6930d2c981
18 changed files with 11521 additions and 160 deletions
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8
src/Makefile.am
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@ -53,7 +53,8 @@ RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c
endif
if USE_EXA
RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c
RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c \
evergreen_exa.c evergreen_accel.c evergreen_shader.c evergreen_textured_videofuncs.c
endif
AM_CFLAGS = \
@ -129,6 +130,11 @@ EXTRA_DIST = \
r600_reg_r7xx.h \
r600_shader.h \
r600_state.h \
evergreen_reg.h \
evergreen_reg_auto.h \
evergreen_reg_r7xx.h \
evergreen_shader.h \
evergreen_state.h \
ati.h \
ativersion.h \
bicubic_table.h \

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/*
* Evergeen Register documentation
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _EVERGREEN_REG_H_
#define _EVERGREEN_REG_H_
/*
* Register definitions
*/
#include "evergreen_reg_auto.h"
enum {
SHADER_TYPE_PS,
SHADER_TYPE_VS,
SHADER_TYPE_GS,
SHADER_TYPE_HS,
SHADER_TYPE_LS,
SHADER_TYPE_CS,
SHADER_TYPE_FS,
};
/* SET_*_REG offsets + ends */
enum {
SET_CONFIG_REG_offset = 0x00008000,
SET_CONFIG_REG_end = 0x0000ac00,
SET_CONTEXT_REG_offset = 0x00028000,
SET_CONTEXT_REG_end = 0x00029000,
SET_RESOURCE_offset = 0x00030000,
SET_RESOURCE_end = 0x00038000,
SET_SAMPLER_offset = 0x0003c000,
SET_SAMPLER_end = 0x0003c600,
SET_CTL_CONST_offset = 0x0003cff0,
SET_CTL_CONST_end = 0x0003ff0c,
SET_LOOP_CONST_offset = 0x0003a200,
SET_LOOP_CONST_end = 0x0003a500,
SET_BOOL_CONST_offset = 0x0003a500,
SET_BOOL_CONST_end = 0x0003a518,
};
/* Packet3 commands */
enum {
IT_NOP = 0x10,
IT_INDIRECT_BUFFER_END = 0x17,
IT_SET_PREDICATION = 0x20,
IT_COND_EXEC = 0x22,
IT_PRED_EXEC = 0x23,
IT_DRAW_INDEX_2 = 0x27,
IT_CONTEXT_CONTROL = 0x28,
IT_DRAW_INDEX_OFFSET = 0x29,
IT_INDEX_TYPE = 0x2A,
IT_DRAW_INDEX = 0x2B,
IT_DRAW_INDEX_AUTO = 0x2D,
IT_DRAW_INDEX_IMMD = 0x2E,
IT_NUM_INSTANCES = 0x2F,
IT_INDIRECT_BUFFER = 0x32,
IT_STRMOUT_BUFFER_UPDATE = 0x34,
IT_MEM_SEMAPHORE = 0x39,
IT_MPEG_INDEX = 0x3A,
IT_WAIT_REG_MEM = 0x3C,
IT_MEM_WRITE = 0x3D,
IT_SURFACE_SYNC = 0x43,
IT_ME_INITIALIZE = 0x44,
IT_COND_WRITE = 0x45,
IT_EVENT_WRITE = 0x46,
IT_EVENT_WRITE_EOP = 0x47,
IT_EVENT_WRITE_EOS = 0x48,
IT_SET_CONFIG_REG = 0x68,
IT_SET_CONTEXT_REG = 0x69,
IT_SET_ALU_CONST = 0x6A,
IT_SET_BOOL_CONST = 0x6B,
IT_SET_LOOP_CONST = 0x6C,
IT_SET_RESOURCE = 0x6D,
IT_SET_SAMPLER = 0x6E,
IT_SET_CTL_CONST = 0x6F,
};
/* IT_WAIT_REG_MEM operation encoding */
#define IT_WAIT_ALWAYS (0 << 0)
#define IT_WAIT_LT (1 << 0)
#define IT_WAIT_LE (2 << 0)
#define IT_WAIT_EQ (3 << 0)
#define IT_WAIT_NE (4 << 0)
#define IT_WAIT_GE (5 << 0)
#define IT_WAIT_GT (6 << 0)
#define IT_WAIT_REG (0 << 4)
#define IT_WAIT_MEM (1 << 4)
#define IT_WAIT_ADDR(x) ((x) >> 2)
enum {
SQ_LDS_ALLOC_PS = 0x288ec,
SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838,
SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c,
WAIT_UNTIL = 0x8040,
WAIT_CP_DMA_IDLE_bit = 1 << 8,
WAIT_CMDFIFO_bit = 1 << 10,
WAIT_3D_IDLE_bit = 1 << 15,
WAIT_3D_IDLECLEAN_bit = 1 << 17,
WAIT_EXTERN_SIG_bit = 1 << 19,
CMDFIFO_ENTRIES_mask = 0xf << 20,
CMDFIFO_ENTRIES_shift = 20,
CP_COHER_CNTL = 0x85f0,
DEST_BASE_0_ENA_bit = 1 << 0,
DEST_BASE_1_ENA_bit = 1 << 1,
SO0_DEST_BASE_ENA_bit = 1 << 2,
SO1_DEST_BASE_ENA_bit = 1 << 3,
SO2_DEST_BASE_ENA_bit = 1 << 4,
SO3_DEST_BASE_ENA_bit = 1 << 5,
CB0_DEST_BASE_ENA_bit = 1 << 6,
CB1_DEST_BASE_ENA_bit = 1 << 7,
CB2_DEST_BASE_ENA_bit = 1 << 8,
CB3_DEST_BASE_ENA_bit = 1 << 9,
CB4_DEST_BASE_ENA_bit = 1 << 10,
CB5_DEST_BASE_ENA_bit = 1 << 11,
CB6_DEST_BASE_ENA_bit = 1 << 12,
CB7_DEST_BASE_ENA_bit = 1 << 13,
DB_DEST_BASE_ENA_bit = 1 << 14,
CB8_DEST_BASE_ENA_bit = 1 << 15,
CB9_DEST_BASE_ENA_bit = 1 << 16,
CB10_DEST_BASE_ENA_bit = 1 << 17,
CB11_DEST_BASE_ENA_bit = 1 << 18,
FULL_CACHE_ENA_bit = 1 << 20,
TC_ACTION_ENA_bit = 1 << 23,
VC_ACTION_ENA_bit = 1 << 24,
CB_ACTION_ENA_bit = 1 << 25,
DB_ACTION_ENA_bit = 1 << 26,
SH_ACTION_ENA_bit = 1 << 27,
SX_ACTION_ENA_bit = 1 << 28,
CP_COHER_SIZE = 0x85f4,
CP_COHER_BASE = 0x85f8,
CP_COHER_STATUS = 0x85fc,
MATCHING_GFX_CNTX_mask = 0xff << 0,
MATCHING_GFX_CNTX_shift = 0,
STATUS_bit = 1 << 31,
// SQ_VTX_CONSTANT_WORD2_0 = 0x00030008,
// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
FMT_1 = 37, FMT_GB_GR=39,
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
FMT_32_32_32_FLOAT=48,
// High level register file lengths
SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0,
SQ_FETCH_RESOURCE_ps_num = 176,
SQ_FETCH_RESOURCE_vs_num = 160,
SQ_FETCH_RESOURCE_gs_num = 160,
SQ_FETCH_RESOURCE_hs_num = 160,
SQ_FETCH_RESOURCE_ls_num = 160,
SQ_FETCH_RESOURCE_cs_num = 176,
SQ_FETCH_RESOURCE_fs_num = 32,
SQ_FETCH_RESOURCE_all_num = 1024,
SQ_FETCH_RESOURCE_offset = 32,
SQ_FETCH_RESOURCE_ps = 0, // 0...175
SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335
SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_fs_num, // 336...495
SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655
SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815
SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991
SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0,
SQ_TEX_SAMPLER_WORD_ps_num = 18,
SQ_TEX_SAMPLER_WORD_vs_num = 18,
SQ_TEX_SAMPLER_WORD_gs_num = 18,
SQ_TEX_SAMPLER_WORD_hs_num = 18,
SQ_TEX_SAMPLER_WORD_ls_num = 18,
SQ_TEX_SAMPLER_WORD_cs_num = 18,
SQ_TEX_SAMPLER_WORD_all_num = 108,
SQ_TEX_SAMPLER_WORD_offset = 12,
SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53
SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71
SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89
SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107
SQ_LOOP_CONST = SQ_LOOP_CONST_0,
SQ_LOOP_CONST_ps_num = 32,
SQ_LOOP_CONST_vs_num = 32,
SQ_LOOP_CONST_gs_num = 32,
SQ_LOOP_CONST_hs_num = 32,
SQ_LOOP_CONST_ls_num = 32,
SQ_LOOP_CONST_cs_num = 32,
SQ_LOOP_CONST_all_num = 192,
SQ_LOOP_CONST_offset = 4,
SQ_LOOP_CONST_ps = 0, // 0...31
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95
SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127
SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159
SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */
SQ_BOOL_CONST_ps_num = 1,
SQ_BOOL_CONST_vs_num = 1,
SQ_BOOL_CONST_gs_num = 1,
SQ_BOOL_CONST_hs_num = 1,
SQ_BOOL_CONST_ls_num = 1,
SQ_BOOL_CONST_cs_num = 1,
SQ_BOOL_CONST_all_num = 6,
SQ_BOOL_CONST_offset = 4,
SQ_BOOL_CONST_ps = 0,
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num,
SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num,
SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num,
SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num,
};
#endif

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/*
* Evergreen shaders
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Shader macros
*/
#ifndef __SHADER_H__
#define __SHADER_H__
#include "radeon.h"
/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
// CF insts
// addr
#define ADDR(x) (x)
// jumptable
#define JUMPTABLE_SEL(x) (x)
// pc
#define POP_COUNT(x) (x)
// const
#define CF_CONST(x) (x)
// cond
#define COND(x) (x) // SQ_COND_*
// count
#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
// vpm
#define VALID_PIXEL_MODE(x) (x)
// eop
#define END_OF_PROGRAM(x) (x)
// cf inst
#define CF_INST(x) (x) // SQ_CF_INST_*
// wqm
#define WHOLE_QUAD_MODE(x) (x)
// barrier
#define BARRIER(x) (x)
//kb0
#define KCACHE_BANK0(x) (x)
//kb1
#define KCACHE_BANK1(x) (x)
// km0/1
#define KCACHE_MODE0(x) (x)
#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_*
//
#define KCACHE_ADDR0(x) (x)
#define KCACHE_ADDR1(x) (x)
#define ALT_CONST(x) (x)
#define ARRAY_BASE(x) (x)
// export pixel
#define CF_PIXEL_MRT0 0
#define CF_PIXEL_MRT1 1
#define CF_PIXEL_MRT2 2
#define CF_PIXEL_MRT3 3
#define CF_PIXEL_MRT4 4
#define CF_PIXEL_MRT5 5
#define CF_PIXEL_MRT6 6
#define CF_PIXEL_MRT7 7
// computed Z
#define CF_COMPUTED_Z 61
// export pos
#define CF_POS0 60
#define CF_POS1 61
#define CF_POS2 62
#define CF_POS3 63
// export param
// 0...31
#define TYPE(x) (x) // SQ_EXPORT_*
#define RW_GPR(x) (x)
#define RW_REL(x) (x)
#define ABSOLUTE 0
#define RELATIVE 1
#define INDEX_GPR(x) (x)
#define ELEM_SIZE(x) (x ? (x - 1) : 0)
#define BURST_COUNT(x) (x ? (x - 1) : 0)
#define MARK(x) (x)
// swiz
#define SRC_SEL_X(x) (x) // SQ_SEL_* each
#define SRC_SEL_Y(x) (x)
#define SRC_SEL_Z(x) (x)
#define SRC_SEL_W(x) (x)
#define CF_DWORD0(addr, jmptbl) ((addr) | ((jmptbl) << 24))
#define CF_DWORD1(pc, cf_const, cond, count, vpm, eop, cf_inst, wqm, b) \
(((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \
((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | ((wqm) << 30) | ((b) << 31))
#define CF_ALU_DWORD0(addr, kb0, kb1, km0) (((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))
#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \
(((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))
#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
(((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \
((index_gpr) << 23) | ((es) << 30))
#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, eop, cf_inst, m, b) \
(((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \
((bc) << 16) | ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | \
((m) << 30) | ((b) << 31))
// ALU clause insts
#define SRC0_SEL(x) (x)
#define SRC1_SEL(x) (x)
#define SRC2_SEL(x) (x)
// src[0-2]_sel
// 0-127 GPR
// 128-159 kcache constants bank 0
// 160-191 kcache constants bank 1
// 192-255 inline const values
// 256-287 kcache constants bank 2
// 288-319 kcache constants bank 3
// 219-255 special SQ_ALU_SRC_* (0, 1, etc.)
// 488-520 src param space
#define ALU_SRC_GPR_BASE 0
#define ALU_SRC_KCACHE0_BASE 128
#define ALU_SRC_KCACHE1_BASE 160
#define ALU_SRC_INLINE_K_BASE 192
#define ALU_SRC_KCACHE2_BASE 256
#define ALU_SRC_KCACHE3_BASE 288
#define ALU_SRC_PARAM_BASE 448
#define SRC0_REL(x) (x)
#define SRC1_REL(x) (x)
#define SRC2_REL(x) (x)
// elem
#define SRC0_ELEM(x) (x)
#define SRC1_ELEM(x) (x)
#define SRC2_ELEM(x) (x)
#define ELEM_X 0
#define ELEM_Y 1
#define ELEM_Z 2
#define ELEM_W 3
// neg
#define SRC0_NEG(x) (x)
#define SRC1_NEG(x) (x)
#define SRC2_NEG(x) (x)
// im
#define INDEX_MODE(x) (x) // SQ_INDEX_*
// ps
#define PRED_SEL(x) (x) // SQ_PRED_SEL_*
// last
#define LAST(x) (x)
// abs
#define SRC0_ABS(x) (x)
#define SRC1_ABS(x) (x)
// uem
#define UPDATE_EXECUTE_MASK(x) (x)
// up
#define UPDATE_PRED(x) (x)
// wm
#define WRITE_MASK(x) (x)
// omod
#define OMOD(x) (x) // SQ_ALU_OMOD_*
// alu inst
#define ALU_INST(x) (x) // SQ_ALU_INST_*
//bs
#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_*
#define DST_GPR(x) (x)
#define DST_REL(x) (x)
#define DST_ELEM(x) (x)
#define CLAMP(x) (x)
#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
(((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
((im) << 26) | ((ps) << 29) | ((last) << 31))
#define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
(((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
((dr) << 28) | ((de) << 29) | ((clamp) << 31))
#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
(((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
((de) << 29) | ((clamp) << 31))
// VTX clause insts
// vxt insts
#define VTX_INST(x) (x) // SQ_VTX_INST_*
// fetch type
#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_*
#define FETCH_WHOLE_QUAD(x) (x)
#define BUFFER_ID(x) (x)
#define SRC_GPR(x) (x)
#define SRC_REL(x) (x)
#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
#define DST_SEL_X(x) (x)
#define DST_SEL_Y(x) (x)
#define DST_SEL_Z(x) (x)
#define DST_SEL_W(x) (x)
#define USE_CONST_FIELDS(x) (x)
#define DATA_FORMAT(x) (x)
// num format
#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_*
// format comp
#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_*
// sma
#define SRF_MODE_ALL(x) (x)
#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
#define SRF_MODE_NO_ZERO 1
#define OFFSET(x) (x)
// endian swap
#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_*
#define CONST_BUF_NO_STRIDE(x) (x)
// mf
#define MEGA_FETCH(x) (x)
#define BUFFER_INDEX_MODE(x) (x)
#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
(((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26))
#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
(((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))
#define VTX_DWORD2(offset, es, cbns, mf, alt_const, bim) \
(((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19) | ((alt_const) << 20) | ((bim) << 21))
#define VTX_DWORD_PAD 0x00000000
// TEX clause insts
// tex insts
#define TEX_INST(x) (x) // SQ_TEX_INST_*
#define INST_MOD(x) (x)
#define FETCH_WHOLE_QUAD(x) (x)
#define RESOURCE_ID(x) (x)
#define RESOURCE_INDEX_MODE(x) (x)
#define SAMPLER_INDEX_MODE(x) (x)
#define LOD_BIAS(x) (x)
//ct
#define COORD_TYPE_X(x) (x)
#define COORD_TYPE_Y(x) (x)
#define COORD_TYPE_Z(x) (x)
#define COORD_TYPE_W(x) (x)
#define TEX_UNNORMALIZED 0
#define TEX_NORMALIZED 1
#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
#define SAMPLER_ID(x) (x)
#define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \
(((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27))
#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
(((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31))
#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
(((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29))
#define TEX_DWORD_PAD 0x00000000
extern int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs);
extern int evergreen_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps);
extern int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs);
extern int evergreen_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps);
extern int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader);
extern int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader);
extern int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs);
extern int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps);
#endif

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/*
* Copyright 2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors: Alex Deucher <alexander.deucher@amd.com>
*
*/
#ifndef __EVERGREEN_STATE_H__
#define __EVERGREEN_STATE_H__
typedef int bool_t;
#define CLEAR(x) memset (&x, 0, sizeof(x))
/* Sequencer / thread handling */
typedef struct {
int ps_prio;
int vs_prio;
int gs_prio;
int es_prio;
int hs_prio;
int ls_prio;
int cs_prio;
int num_ps_gprs;
int num_vs_gprs;
int num_gs_gprs;
int num_es_gprs;
int num_hs_gprs;
int num_ls_gprs;
int num_cs_gprs;
int num_temp_gprs;
int num_ps_threads;
int num_vs_threads;
int num_gs_threads;
int num_es_threads;
int num_hs_threads;
int num_ls_threads;
int num_ps_stack_entries;
int num_vs_stack_entries;
int num_gs_stack_entries;
int num_es_stack_entries;
int num_hs_stack_entries;
int num_ls_stack_entries;
} sq_config_t;
/* Color buffer / render target */
typedef struct {
int id;
int w;
int h;
uint64_t base;
int format;
int endian;
int array_mode; // tiling
int number_type;
int read_size;
int comp_swap;
int tile_mode;
int blend_clamp;
int clear_color;
int blend_bypass;
int simple_float;
int round_mode;
int tile_compact;
int source_format;
int resource_type;
int fast_clear;
int compression;
int rat;
struct radeon_bo *bo;
} cb_config_t;
/* Shader */
typedef struct {
uint64_t shader_addr;
uint32_t shader_size;
int num_gprs;
int stack_size;
int dx10_clamp;
int clamp_consts;
int export_mode;
int uncached_first_inst;
int single_round;
int double_round;
int allow_sdi;
int allow_sd0;
int allow_ddi;
int allow_ddo;
struct radeon_bo *bo;
} shader_config_t;
/* Shader consts */
typedef struct {
int type;
int size_bytes;
uint64_t const_addr;
struct radeon_bo *bo;
} const_config_t;
/* Vertex buffer / vtx resource */
typedef struct {
int id;
uint64_t vb_addr;
uint32_t vtx_num_entries;
uint32_t vtx_size_dw;
int clamp_x;
int format;
int num_format_all;
int format_comp_all;
int srf_mode_all;
int endian;
int mem_req_size;
int dst_sel_x;
int dst_sel_y;
int dst_sel_z;
int dst_sel_w;
int uncached;
struct radeon_bo *bo;
} vtx_resource_t;
/* Texture resource */
typedef struct {
int id;
int w;
int h;
int pitch;
int depth;
int dim;
int array_mode;
int tile_type;
int format;
uint64_t base;
uint64_t mip_base;
uint32_t size;
int format_comp_x;
int format_comp_y;
int format_comp_z;
int format_comp_w;
int num_format_all;
int srf_mode_all;
int force_degamma;
int endian;
int dst_sel_x;
int dst_sel_y;
int dst_sel_z;
int dst_sel_w;
int base_level;
int last_level;
int base_array;
int last_array;
int perf_modulation;
int interlaced;
int min_lod;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
} tex_resource_t;
/* Texture sampler */
typedef struct {
int id;
/* Clamping */
int clamp_x, clamp_y, clamp_z;
int border_color;
/* Filtering */
int xy_mag_filter, xy_min_filter;
int z_filter;
int mip_filter;
bool_t high_precision_filter; /* ? */
int perf_mip; /* ? 0-7 */
int perf_z; /* ? 3 */
/* LoD selection */
int min_lod, max_lod; /* 0-0x3ff */
int lod_bias; /* 0-0xfff (signed?) */
int lod_bias2; /* ? 0-0xfff (signed?) */
bool_t lod_uses_minor_axis; /* ? */
/* Other stuff */
bool_t point_sampling_clamp; /* ? */
bool_t tex_array_override; /* ? */
bool_t mc_coord_truncate; /* ? */
bool_t force_degamma; /* ? */
bool_t fetch_4; /* ? */
bool_t sample_is_pcf; /* ? */
bool_t type; /* ? */
int depth_compare; /* only depth textures? */
int chroma_key;
int truncate_coord;
bool_t disable_cube_wrap;
} tex_sampler_t;
/* Draw command */
typedef struct {
uint32_t prim_type;
uint32_t vgt_draw_initiator;
uint32_t index_type;
uint32_t num_instances;
uint32_t num_indices;
} draw_config_t;
#define BEGIN_BATCH(n) \
do { \
radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
} while(0)
#define END_BATCH() \
do { \
radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
} while(0)
#define RELOC_BATCH(bo, rd, wd) \
do { \
int _ret; \
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
} while(0)
#define E32(dword) \
do { \
radeon_cs_write_dword(info->cs, (dword)); \
} while (0)
#define EFLOAT(val) \
do { \
union { float f; uint32_t d; } a; \
a.f = (val); \
E32(a.d); \
} while (0)
#define PACK3(cmd, num) \
do { \
E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
} while (0)
/* write num registers, start at reg */
/* If register falls in a special area, special commands are issued */
#define PACK0(reg, num) \
do { \
if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
PACK3(IT_SET_CONFIG_REG, (num) + 1); \
E32(((reg) - SET_CONFIG_REG_offset) >> 2); \
} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
PACK3(IT_SET_CONTEXT_REG, (num) + 1); \
E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \
} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
PACK3(IT_SET_RESOURCE, num + 1); \
E32(((reg) - SET_RESOURCE_offset) >> 2); \
} else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
PACK3(IT_SET_SAMPLER, (num) + 1); \
E32((reg - SET_SAMPLER_offset) >> 2); \
} else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
PACK3(IT_SET_CTL_CONST, (num) + 1); \
E32(((reg) - SET_CTL_CONST_offset) >> 2); \
} else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
PACK3(IT_SET_LOOP_CONST, (num) + 1); \
E32(((reg) - SET_LOOP_CONST_offset) >> 2); \
} else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
PACK3(IT_SET_BOOL_CONST, (num) + 1); \
E32(((reg) - SET_BOOL_CONST_offset) >> 2); \
} else { \
E32(CP_PACKET0 ((reg), (num) - 1)); \
} \
} while (0)
/* write a single register */
#define EREG(reg, val) \
do { \
PACK0((reg), 1); \
E32((val)); \
} while (0)
void
evergreen_start_3d(ScrnInfoPtr pScrn);
void
evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
void
evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
void
evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
void
evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
void
evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
void
evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
void
evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
void
evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
void
evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
void
evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
void
evergreen_set_default_state(ScrnInfoPtr pScrn);
void
evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
Bool
EVERGREENSetAccelState(ScrnInfoPtr pScrn,
struct r600_accel_object *src0,
struct r600_accel_object *src1,
struct r600_accel_object *dst,
uint32_t vs_offset, uint32_t ps_offset,
int rop, Pixel planemask);
extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
#endif

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/*
* Copyright 2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Author: Alex Deucher <alexander.deucher@amd.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "exa.h"
#include "radeon.h"
#include "radeon_reg.h"
#include "evergreen_shader.h"
#include "evergreen_reg.h"
#include "evergreen_state.h"
#include "radeon_video.h"
#include <X11/extensions/Xv.h>
#include "fourcc.h"
#include "damage.h"
#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
note the difference to the parameters used in overlay are due
to 10bit vs. float calcs */
static REF_TRANSFORM trans[2] =
{
{1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */
{1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */
};
void
EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
PixmapPtr pPixmap = pPriv->pPixmap;
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
int nBox = REGION_NUM_RECTS(&pPriv->clip);
int dstxoff, dstyoff;
struct r600_accel_object src_obj, dst_obj;
cb_config_t cb_conf;
tex_resource_t tex_res;
tex_sampler_t tex_samp;
shader_config_t vs_conf, ps_conf;
/*
* y' = y - .0625
* u' = u - .5
* v' = v - .5;
*
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
*
* DP3 might look like the straightforward solution
* but we'd need to move the texture yuv values in
* the same reg for this to work. Therefore use MADs.
* Brightness just adds to the off constant.
* Contrast is multiplication of luminance.
* Saturation and hue change the u and v coeffs.
* Default values (before adjustments - depend on colorspace):
* yco = 1.1643
* uco = 0, -0.39173, 2.017
* vco = 1.5958, -0.8129, 0
* off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r],
* -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g],
* -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b],
*
* temp = MAD(yco, yuv.yyyy, off)
* temp = MAD(uco, yuv.uuuu, temp)
* result = MAD(vco, yuv.vvvv, temp)
*/
/* TODO: calc consts in the shader */
const float Loff = -0.0627;
const float Coff = -0.502;
float uvcosf, uvsinf;
float yco;
float uco[3], vco[3], off[3];
float bright, cont, gamma;
int ref = pPriv->transform_index;
Bool needgamma = FALSE;
float *ps_alu_consts;
const_config_t ps_const_conf;
float *vs_alu_consts;
const_config_t vs_const_conf;
int ret;
cont = RTFContrast(pPriv->contrast);
bright = RTFBrightness(pPriv->brightness);
gamma = (float)pPriv->gamma / 1000.0;
uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue));
uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue));
/* overlay video also does pre-gamma contrast/sat adjust, should we? */
yco = trans[ref].RefLuma * cont;
uco[0] = -trans[ref].RefRCr * uvsinf;
uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf;
uco[2] = trans[ref].RefBCb * uvcosf;
vco[0] = trans[ref].RefRCr * uvcosf;
vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf;
vco[2] = trans[ref].RefBCb * uvsinf;
off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright;
off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright;
off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright;
// XXX
gamma = 1.0;
if (gamma != 1.0) {
needgamma = TRUE;
/* note: gamma correction is out = in ^ gamma;
gpu can only do LG2/EX2 therefore we transform into
in ^ gamma = 2 ^ (log2(in) * gamma).
Lots of scalar ops, unfortunately (better solution?) -
without gamma that's 3 inst, with gamma it's 10...
could use different gamma factors per channel,
if that's of any use. */
}
CLEAR (cb_conf);
CLEAR (tex_res);
CLEAR (tex_samp);
CLEAR (vs_conf);
CLEAR (ps_conf);
CLEAR (vs_const_conf);
CLEAR (ps_const_conf);
/* setup the ps consts */
ps_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
RADEON_GEM_DOMAIN_GTT, 0);
if (ps_const_conf.bo == NULL) {
ErrorF("ps const buffer alloc failed\n");
return;
}
ret = radeon_bo_map(ps_const_conf.bo, 0);
if (ret) {
ErrorF("ps const buffer map failed\n");
return;
}
/* PS alu constants */
ps_const_conf.size_bytes = 256;
ps_const_conf.const_addr = 0;
ps_const_conf.type = SHADER_TYPE_PS;
ps_alu_consts = (float *)ps_const_conf.bo->ptr;
ps_alu_consts[0] = off[0];
ps_alu_consts[1] = off[1];
ps_alu_consts[2] = off[2];
ps_alu_consts[3] = yco;
ps_alu_consts[4] = uco[0];
ps_alu_consts[5] = uco[1];
ps_alu_consts[6] = uco[2];
ps_alu_consts[7] = gamma;
ps_alu_consts[8] = vco[0];
ps_alu_consts[9] = vco[1];
ps_alu_consts[10] = vco[2];
ps_alu_consts[11] = 0.0;
radeon_bo_unmap(ps_const_conf.bo);
vs_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
RADEON_GEM_DOMAIN_GTT, 0);
if (vs_const_conf.bo == NULL) {
ErrorF("vs const buffer alloc failed\n");
return;
}
ret = radeon_bo_map(vs_const_conf.bo, 0);
if (ret) {
ErrorF("vs const buffer map failed\n");
return;
}
/* PS alu constants */
vs_const_conf.size_bytes = 256;
vs_const_conf.const_addr = 0;
vs_const_conf.type = SHADER_TYPE_VS;
vs_alu_consts = (float *)vs_const_conf.bo->ptr;
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
vs_alu_consts[2] = 0.0;
vs_alu_consts[3] = 0.0;
radeon_bo_unmap(vs_const_conf.bo);
radeon_cs_space_add_persistent_bo(info->cs, ps_const_conf.bo,
RADEON_GEM_DOMAIN_GTT, 0);
radeon_cs_space_add_persistent_bo(info->cs, vs_const_conf.bo,
RADEON_GEM_DOMAIN_GTT, 0);
if (radeon_cs_space_check(info->cs)) {
radeon_bo_unref(ps_const_conf.bo);
radeon_bo_unref(vs_const_conf.bo);
ErrorF("const buffer size check failed\n");
return;
}
#if defined(XF86DRM_MODE)
if (info->cs) {
dst_obj.offset = 0;
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
} else
#endif
{
dst_obj.offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset;
src_obj.offset = pPriv->src_offset + info->fbLocation + pScrn->fbOffset;
dst_obj.bo = src_obj.bo = NULL;
}
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
src_obj.pitch = pPriv->src_pitch;
src_obj.width = pPriv->w;
src_obj.height = pPriv->h;
src_obj.bpp = 16;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
if (!EVERGREENSetAccelState(pScrn,
&src_obj,
NULL,
&dst_obj,
accel_state->xv_vs_offset, accel_state->xv_ps_offset,
3, 0xffffffff))
return;
#ifdef COMPOSITE
dstxoff = -pPixmap->screen_x + pPixmap->drawable.x;
dstyoff = -pPixmap->screen_y + pPixmap->drawable.y;
#else
dstxoff = 0;
dstyoff = 0;
#endif
radeon_vbo_check(pScrn, 16);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* PS bool constant */
switch(pPriv->id) {
case FOURCC_YV12:
case FOURCC_I420:
evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0));
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0));
break;
}
/* Shader */
vs_conf.shader_addr = accel_state->vs_mc_addr;
vs_conf.shader_size = accel_state->vs_size;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
ps_conf.num_gprs = 3;
ps_conf.stack_size = 1;
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
/* Texture */
switch(pPriv->id) {
case FOURCC_YV12:
case FOURCC_I420:
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
/* Y texture */
tex_res.id = 0;
tex_res.w = accel_state->src_obj[0].width;
tex_res.h = accel_state->src_obj[0].height;
tex_res.pitch = accel_state->src_obj[0].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
tex_res.dst_sel_y = SQ_SEL_1;
tex_res.dst_sel_z = SQ_SEL_1;
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_z = SQ_TEX_WRAP;
/* xxx: switch to bicubic */
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
evergreen_set_tex_sampler(pScrn, &tex_samp);
/* U or V texture */
tex_res.id = 1;
tex_res.format = FMT_8;
tex_res.w = accel_state->src_obj[0].width >> 1;
tex_res.h = accel_state->src_obj[0].height >> 1;
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, 256);
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
tex_res.dst_sel_y = SQ_SEL_1;
tex_res.dst_sel_z = SQ_SEL_1;
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.size = accel_state->src_size[0] / 4;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
tex_samp.id = 1;
evergreen_set_tex_sampler(pScrn, &tex_samp);
/* U or V texture */
tex_res.id = 2;
tex_res.format = FMT_8;
tex_res.w = accel_state->src_obj[0].width >> 1;
tex_res.h = accel_state->src_obj[0].height >> 1;
tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, 256);
tex_res.dst_sel_x = SQ_SEL_X; /* V or U */
tex_res.dst_sel_y = SQ_SEL_1;
tex_res.dst_sel_z = SQ_SEL_1;
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.size = accel_state->src_size[0] / 4;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
tex_samp.id = 2;
evergreen_set_tex_sampler(pScrn, &tex_samp);
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
/* Y texture */
tex_res.id = 0;
tex_res.w = accel_state->src_obj[0].width;
tex_res.h = accel_state->src_obj[0].height;
tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
tex_res.format = FMT_8_8;
if (pPriv->id == FOURCC_UYVY)
tex_res.dst_sel_x = SQ_SEL_Y; /* Y */
else
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
tex_res.dst_sel_y = SQ_SEL_1;
tex_res.dst_sel_z = SQ_SEL_1;
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_z = SQ_TEX_WRAP;
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
evergreen_set_tex_sampler(pScrn, &tex_samp);
/* UV texture */
tex_res.id = 1;
tex_res.format = FMT_8_8_8_8;
tex_res.w = accel_state->src_obj[0].width >> 1;
tex_res.h = accel_state->src_obj[0].height;
tex_res.pitch = accel_state->src_obj[0].pitch >> 2;
if (pPriv->id == FOURCC_UYVY) {
tex_res.dst_sel_x = SQ_SEL_X; /* V */
tex_res.dst_sel_y = SQ_SEL_Z; /* U */
} else {
tex_res.dst_sel_x = SQ_SEL_Y; /* V */
tex_res.dst_sel_y = SQ_SEL_W; /* U */
}
tex_res.dst_sel_z = SQ_SEL_1;
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
tex_samp.id = 1;
evergreen_set_tex_sampler(pScrn, &tex_samp);
break;
}
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
switch (accel_state->dst_obj.bpp) {
case 16:
if (pPixmap->drawable.depth == 15) {
cb_conf.format = COLOR_1_5_5_5;
cb_conf.comp_swap = 1; /* ARGB */
} else {
cb_conf.format = COLOR_5_6_5;
cb_conf.comp_swap = 2; /* RGB */
}
break;
case 32:
cb_conf.format = COLOR_8_8_8_8;
cb_conf.comp_swap = 1; /* ARGB */
break;
default:
return;
}
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
BEGIN_BATCH(23);
EREG(CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift));
EREG(CB_COLOR_CONTROL, ((0xcc << ROP3_shift) |
(CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
EREG(CB_BLEND0_CONTROL, 0);
/* Interpolator setup */
/* export tex coords from VS */
EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
EREG(SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
EREG(SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
(0x03 << DEFAULT_VAL_shift)));
/* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
* *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
PACK0(SPI_PS_IN_CONTROL_0, 3);
E32(((1 << NUM_INTERP_shift) |
LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
E32(0); // SPI_PS_IN_CONTROL_1
E32(0); // SPI_INTERP_CONTROL_0
END_BATCH();
/* VS alu constants */
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
if (pPriv->vsync) {
xf86CrtcPtr crtc;
if (pPriv->desired_crtc)
crtc = pPriv->desired_crtc;
else
crtc = radeon_pick_best_crtc(pScrn,
pPriv->drw_x,
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
evergreen_cp_wait_vline_sync(pScrn, pPixmap,
crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
while (nBox--) {
int srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
float *vb;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
dstw = pBox->x2 - pBox->x1;
dsth = pBox->y2 - pBox->y1;
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
pPriv->src_w) / pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
pPriv->src_h) / pPriv->dst_h;
srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
srch = (pPriv->src_h * dsth) / pPriv->dst_h;
vb = radeon_vbo_space(pScrn, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
vb[2] = (float)srcX;
vb[3] = (float)srcY;
vb[4] = (float)dstX;
vb[5] = (float)(dstY + dsth);
vb[6] = (float)srcX;
vb[7] = (float)(srcY + srch);
vb[8] = (float)(dstX + dstw);
vb[9] = (float)(dstY + dsth);
vb[10] = (float)(srcX + srcw);
vb[11] = (float)(srcY + srch);
radeon_vbo_commit(pScrn);
pBox++;
}
evergreen_finish_op(pScrn, 16);
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}

106
src/r600_exa.c
View file

@ -43,7 +43,7 @@
/* #define SHOW_VERTEXES */
uint32_t RADEON_ROP[16] = {
uint32_t R600_ROP[16] = {
RADEON_ROP3_ZERO, /* GXclear */
RADEON_ROP3_DSa, /* Gxand */
RADEON_ROP3_SDna, /* GXandReverse */
@ -211,11 +211,11 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
radeon_vbo_check(pScrn, 16);
radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
r600_set_default_state(pScrn, accel_state->ib);
set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* Shader */
vs_conf.shader_addr = accel_state->vs_mc_addr;
@ -223,7 +223,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
@ -233,7 +233,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
@ -253,7 +253,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
if (accel_state->planemask & 0x000000ff)
@ -266,7 +266,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
pmask |= 8; /* A */
BEGIN_BATCH(20);
EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
@ -312,8 +312,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_alu_consts[2] = (float)b / 255; /* B */
ps_alu_consts[3] = (float)a / 255; /* A */
}
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
if (accel_state->vsync)
RADEONVlineHelperClear(pScrn);
@ -355,10 +355,10 @@ R600DoneSolid(PixmapPtr pPix)
struct radeon_accel_state *accel_state = info->accel_state;
if (accel_state->vsync)
cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
r600_finish_op(pScrn, 8);
}
@ -383,11 +383,11 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
radeon_vbo_check(pScrn, 16);
radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
r600_set_default_state(pScrn, accel_state->ib);
set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* Shader */
vs_conf.shader_addr = accel_state->vs_mc_addr;
@ -395,7 +395,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
@ -405,7 +405,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* Texture */
tex_res.id = 0;
@ -443,7 +443,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
@ -453,7 +453,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
@ -472,7 +472,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
if (accel_state->planemask & 0x000000ff)
@ -485,7 +485,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
pmask |= 8; /* A */
BEGIN_BATCH(20);
EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]);
/* Interpolator setup */
/* export tex coord from VS */
@ -521,10 +521,10 @@ R600DoCopyVline(PixmapPtr pPix)
struct radeon_accel_state *accel_state = info->accel_state;
if (accel_state->vsync)
cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
r600_finish_op(pScrn, 16);
}
@ -603,7 +603,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
src_obj.height = pSrc->drawable.height;
src_obj.bpp = pSrc->drawable.bitsPerPixel;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
dst_obj.width = pDst->drawable.width;
dst_obj.height = pDst->drawable.height;
dst_obj.bpp = pDst->drawable.bitsPerPixel;
@ -1060,7 +1060,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain);
tex_samp.id = unit;
tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
@ -1102,7 +1102,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_samp.clamp_z = SQ_TEX_WRAP;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
if (pPict->transform != 0) {
accel_state->is_transform[unit] = TRUE;
@ -1132,8 +1132,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
}
/* VS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2),
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2),
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
return TRUE;
}
@ -1264,7 +1264,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (info->cs) {
mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
} else
} else
#endif
{
mask_obj.offset = exaGetPixmapOffset(pMask) + info->fbLocation + pScrn->fbOffset;
@ -1324,11 +1324,11 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
r600_set_default_state(pScrn, accel_state->ib);
set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
R600IBDiscard(pScrn, accel_state->ib);
@ -1346,11 +1346,11 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
accel_state->is_transform[1] = FALSE;
if (pMask) {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0));
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
} else {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0));
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
}
/* Shader */
@ -1359,7 +1359,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
@ -1369,7 +1369,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
@ -1405,7 +1405,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
BEGIN_BATCH(24);
EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
@ -1414,10 +1414,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (info->ChipFamily == CHIP_FAMILY_R600) {
/* no per-MRT blend on R600 */
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift));
EREG(accel_state->ib, CB_BLEND_CONTROL, blendcntl);
} else {
EREG(accel_state->ib, CB_COLOR_CONTROL, (RADEON_ROP[3] |
EREG(accel_state->ib, CB_COLOR_CONTROL, (R600_ROP[3] |
(1 << TARGET_BLEND_ENABLE_shift) |
PER_MRT_BLEND_bit));
EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl);
@ -1542,10 +1542,10 @@ static void R600DoneComposite(PixmapPtr pDst)
int vtx_size;
if (accel_state->vsync)
cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
accel_state->vline_crtc,
accel_state->vline_y1,
accel_state->vline_y2);
vtx_size = accel_state->msk_pic ? 24 : 16;
@ -1913,7 +1913,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = w;
dst_obj.height = h;

42
src/r600_state.h
View file

@ -274,48 +274,46 @@ do { \
void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
uint64_t
upload (ScrnInfoPtr pScrn, void *shader, int size, int offset);
void
wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
void
wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
void
start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
void
set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
void
cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
void
vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
void
ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
void
set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
void
set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
void
set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
void
set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
void
set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
void
set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
void
set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
void
set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
void
draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
void
draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);

54
src/r600_textured_videofuncs.c
View file

@ -209,22 +209,22 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
radeon_vbo_check(pScrn, 16);
radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
r600_set_default_state(pScrn, accel_state->ib);
set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* PS bool constant */
switch(pPriv->id) {
case FOURCC_YV12:
case FOURCC_I420:
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
break;
}
@ -234,7 +234,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
@ -244,11 +244,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
/* Texture */
switch(pPriv->id) {
@ -280,7 +280,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
tex_samp.id = 0;
@ -294,7 +294,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
/* U or V texture */
tex_res.id = 1;
@ -311,11 +311,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.size = accel_state->src_size[0] / 4;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
tex_samp.id = 1;
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
/* U or V texture */
tex_res.id = 2;
@ -332,11 +332,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.size = accel_state->src_size[0] / 4;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
tex_samp.id = 2;
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
@ -370,7 +370,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
tex_samp.id = 0;
@ -384,7 +384,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
/* UV texture */
tex_res.id = 1;
@ -406,11 +406,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
tex_samp.id = 1;
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
break;
}
@ -440,7 +440,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
BEGIN_BATCH(20);
@ -469,8 +469,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_alu_consts[3] = 0.0;
/* VS alu constants */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs,
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs,
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
if (pPriv->vsync) {
xf86CrtcPtr crtc;
@ -483,10 +483,10 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
while (nBox--) {

106
src/r6xx_accel.c
View file

@ -98,7 +98,7 @@ void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
}
void
wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -113,7 +113,7 @@ wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
}
void
wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -123,7 +123,7 @@ wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib)
}
void
start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -147,7 +147,7 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
// asic stack/thread/gpr limits - need to query the drm
static void
sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
{
uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
@ -198,7 +198,7 @@ sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
}
void
set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info;
int pitch, slice, h;
@ -276,8 +276,9 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
}
static void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain)
r600_cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type,
uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t cp_coher_size;
@ -297,7 +298,8 @@ cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_
}
/* inserts a wait for vline in the command stream */
void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
void
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
xf86CrtcPtr crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -380,7 +382,7 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
}
void
fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@ -403,7 +405,7 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t dom
}
void
vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@ -419,9 +421,9 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t dom
sq_pgm_resources |= UNCACHED_FIRST_INST_bit;
/* flush SQ cache */
cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
vs_conf->shader_size, vs_conf->shader_addr,
vs_conf->bo, domain, 0);
r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
vs_conf->shader_size, vs_conf->shader_addr,
vs_conf->bo, domain, 0);
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
@ -435,7 +437,7 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t dom
}
void
ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_pgm_resources;
@ -453,9 +455,9 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t dom
sq_pgm_resources |= CLAMP_CONSTS_bit;
/* flush SQ cache */
cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
ps_conf->shader_size, ps_conf->shader_addr,
ps_conf->bo, domain, 0);
r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
ps_conf->shader_size, ps_conf->shader_addr,
ps_conf->bo, domain, 0);
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
@ -470,7 +472,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t dom
}
void
set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf)
r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
int i;
@ -484,7 +486,7 @@ set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *co
}
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
/* bool register order is: ps, vs, gs; one register each
@ -496,7 +498,7 @@ set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
}
static void
set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
@ -522,15 +524,15 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t
(info->ChipFamily == CHIP_FAMILY_RS780) ||
(info->ChipFamily == CHIP_FAMILY_RS880) ||
(info->ChipFamily == CHIP_FAMILY_RV710))
cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
accel_state->vb_offset, accel_state->vb_mc_addr,
res->bo,
domain, 0);
r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
accel_state->vb_offset, accel_state->vb_mc_addr,
res->bo,
domain, 0);
else
cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
accel_state->vb_offset, accel_state->vb_mc_addr,
res->bo,
domain, 0);
r600_cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
accel_state->vb_offset, accel_state->vb_mc_addr,
res->bo,
domain, 0);
BEGIN_BATCH(9 + 2);
PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7);
@ -546,7 +548,7 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t
}
void
set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
@ -599,9 +601,9 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint3
sq_tex_resource_word6 |= INTERLACED_bit;
/* flush texture cache */
cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
tex_res->size, tex_res->base,
tex_res->bo, domain, 0);
r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
tex_res->size, tex_res->base,
tex_res->bo, domain, 0);
BEGIN_BATCH(9 + 4);
PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7);
@ -618,7 +620,7 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint3
}
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s)
r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2;
@ -670,7 +672,7 @@ set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s)
//XXX deal with clip offsets in clip setup
void
set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -684,7 +686,7 @@ set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
}
void
set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -699,7 +701,7 @@ set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x
}
void
set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -714,7 +716,7 @@ set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
}
void
set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -729,7 +731,7 @@ set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
}
void
set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -747,7 +749,7 @@ set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, i
*/
void
set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
{
tex_resource_t tex_res;
shader_config_t fs_conf;
@ -764,7 +766,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
accel_state->XInited3D = TRUE;
start_3d(pScrn, accel_state->ib);
r600_start_3d(pScrn, accel_state->ib);
// SQ
sq_conf.ps_prio = 0;
@ -888,7 +890,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
break;
}
sq_setup(pScrn, ib, &sq_conf);
r600_sq_setup(pScrn, ib, &sq_conf);
/* set fake reloc for unused depth */
BEGIN_BATCH(3 + 2);
@ -992,10 +994,10 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
/* clip boolean is set to always visible -> doesn't matter */
for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192);
r600_set_clip_rect(pScrn, ib, i, 0, 0, 8192, 8192);
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192);
r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192);
BEGIN_BATCH(42);
PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
@ -1051,7 +1053,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// clear FS
fs_conf.bo = accel_state->shaders_bo;
fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(43);
@ -1102,7 +1104,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
*/
void
draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices)
r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t i, count;
@ -1140,7 +1142,7 @@ draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *i
}
void
draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -1183,7 +1185,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
set_vtx_resource (pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
/* Draw */
draw_conf.prim_type = DI_PT_RECTLIST;
@ -1192,15 +1194,15 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw;
draw_conf.index_type = DI_INDEX_SIZE_16_BIT;
draw_auto(pScrn, accel_state->ib, &draw_conf);
r600_draw_auto(pScrn, accel_state->ib, &draw_conf);
/* XXX drm should handle this in fence submit */
wait_3d_idle_clean(pScrn, accel_state->ib);
r600_wait_3d_idle_clean(pScrn, accel_state->ib);
/* sync dst surface */
cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
accel_state->dst_size, accel_state->dst_obj.offset,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
r600_cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
accel_state->dst_size, accel_state->dst_obj.offset,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
accel_state->vb_start_op = -1;
accel_state->ib_reset_op = 0;

14
src/radeon.h
View file

@ -387,6 +387,8 @@ typedef enum {
#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR))
#define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR)
#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600)
#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
@ -753,6 +755,16 @@ struct radeon_accel_state {
uint32_t comp_ps_offset;
uint32_t xv_vs_offset;
uint32_t xv_ps_offset;
// shader consts
uint32_t solid_vs_const_offset;
uint32_t solid_ps_const_offset;
uint32_t copy_vs_const_offset;
uint32_t copy_ps_const_offset;
uint32_t comp_vs_const_offset;
uint32_t comp_ps_const_offset;
uint32_t comp_mask_ps_const_offset;
uint32_t xv_vs_const_offset;
uint32_t xv_ps_const_offset;
//size/addr stuff
struct r600_accel_object src_obj[2];
@ -1274,6 +1286,8 @@ extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn,
Pixel planemask);
extern Bool R600DrawInit(ScreenPtr pScreen);
extern Bool R600LoadShaders(ScrnInfoPtr pScrn);
extern Bool EVERGREENDrawInit(ScreenPtr pScreen);
extern Bool EVERGREENLoadShaders(ScrnInfoPtr pScrn);
#endif
#if defined(XF86DRI) && defined(USE_EXA)

5
src/radeon_accel.c
View file

@ -1072,7 +1072,10 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
if (info->useEXA) {
# ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
if (!EVERGREENDrawInit(pScreen))
return FALSE;
} else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (!R600DrawInit(pScreen))
return FALSE;
} else {

13
src/radeon_kms.c
View file

@ -202,8 +202,18 @@ static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
int r;
uint32_t tmp;
#ifndef RADEON_INFO_ACCEL_WORKING
#define RADEON_INFO_ACCEL_WORKING 0x03
#endif
#ifndef RADEON_INFO_ACCEL_WORKING2
#define RADEON_INFO_ACCEL_WORKING2 0x05
#endif
memset(&ginfo, 0, sizeof(ginfo));
ginfo.request = 0x3;
if (info->dri->pKernelDRMVersion->version_minor >= 5)
ginfo.request = RADEON_INFO_ACCEL_WORKING2;
else
ginfo.request = RADEON_INFO_ACCEL_WORKING;
ginfo.value = (uintptr_t)&tmp;
r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
if (r) {
@ -230,7 +240,6 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
}
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
(info->ChipFamily >= CHIP_FAMILY_CEDAR) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");

6
src/radeon_reg.h
View file

@ -4242,6 +4242,12 @@
#define EVERGREEN_DATA_FORMAT 0x6b00
# define EVERGREEN_INTERLEAVE_EN (1 << 0)
#define EVERGREEN_DESKTOP_HEIGHT 0x6b04
#define EVERGREEN_VLINE_START_END 0x6b08
# define EVERGREEN_VLINE_START_SHIFT 0
# define EVERGREEN_VLINE_END_SHIFT 16
# define EVERGREEN_VLINE_INV (1 << 31)
#define EVERGREEN_VLINE_STATUS 0x6bb8
# define EVERGREEN_VLINE_STAT (1 << 12)
#define EVERGREEN_VIEWPORT_START 0x6d70
#define EVERGREEN_VIEWPORT_SIZE 0x6d74

8
src/radeon_textured_video.c
View file

@ -36,7 +36,6 @@
#include "radeon.h"
#include "radeon_reg.h"
#include "r600_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_video.h"
@ -47,6 +46,9 @@
extern void
R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
extern void
EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
extern Bool
R600CopyToVRAM(ScrnInfoPtr pScrn,
char *src, int src_pitch,
@ -473,7 +475,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
#endif
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (IS_R600_3D)
if (IS_EVERGREEN_3D)
EVERGREENDisplayTexturedVideo(pScrn, pPriv);
else if (IS_R600_3D)
R600DisplayTexturedVideo(pScrn, pPriv);
else if (IS_R500_3D)
R500DisplayTexturedVideoCP(pScrn, pPriv);