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radeon: drop all UMS/DRI1/XAA/overlay support.

Browse source 
This overhauls the radeon driver and removes all the old UMS-only code,
it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners

There are probably a lot more cleanups that will fall out of this afterwards.

So far this is compile/build tested.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2012-06-15 10:05:03 +01:00
commit 18d5ae3bd9
84 changed files with 1072 additions and 58947 deletions
Download patch file Download diff file Expand all files Collapse all files

153
configure.ac
View file

@ -30,12 +30,6 @@ AC_INIT([xf86-video-ati],
AC_CONFIG_SRCDIR([Makefile.am])
AC_CONFIG_HEADERS([config.h])
# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
m4_ifndef([XORG_MACROS_VERSION],
[m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])])
XORG_MACROS_VERSION(1.8)
XORG_DEFAULT_OPTIONS
AC_CONFIG_AUX_DIR(.)
# Initialize Automake
@ -44,6 +38,12 @@ AC_SYS_LARGEFILE
AM_MAINTAINER_MODE
# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
m4_ifndef([XORG_MACROS_VERSION],
[m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])])
XORG_MACROS_VERSION(1.8)
XORG_DEFAULT_OPTIONS
# Initialize libtool
AC_DISABLE_STATIC
AC_PROG_LIBTOOL
@ -64,144 +64,32 @@ AC_ARG_WITH(xorg-module-dir,
[moduledir="$withval"],
[moduledir="$libdir/xorg/modules"])
AC_ARG_ENABLE(dri, AS_HELP_STRING([--disable-dri],
[Disable DRI support [[default=auto]]]),
[DRI="$enableval"],
[DRI=auto])
AC_ARG_ENABLE(exa,
AS_HELP_STRING([--disable-exa],
[Disable EXA support [[default=enabled]]]),
[EXA="$enableval"],
[EXA=yes])
AC_ARG_ENABLE(kms,
AS_HELP_STRING([--disable-kms],
[Disable KMS support [[default=enabled]]]),
[DRM_MODE="$enableval"],
[DRM_MODE=yes])
# Store the list of server defined optional extensions in REQUIRED_MODULES
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XV, videoproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for libraries.
PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.35])
PKG_CHECK_MODULES(LIBDRM_RADEON, [libdrm_radeon])
# Obtain compiler/linker options for the driver dependencies
PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
PKG_CHECK_MODULES(XORG, [xorg-server >= 1.6.2 xproto fontsproto xf86driproto $REQUIRED_MODULES])
PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1],
HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, [xextproto 7.1 available]),
HAVE_XEXTPROTO_71="no")
AM_CONDITIONAL(HAVE_XEXTPROTO_71, [ test "$HAVE_XEXTPROTO_71" = "yes" ])
# Checks for libraries.
if test "$DRI" != no; then
PKG_CHECK_MODULES(DRI, [libdrm >= 2.2 xf86driproto])
save_CPPFLAGS="$CPPFLAGS"
CPPFLAGS="$XORG_CFLAGS $DRI_CFLAGS"
AC_CHECK_HEADER([dri.h],
[have_dri_h="yes"], [have_dri_h="no"],[-])
AC_CHECK_HEADER([sarea.h],
[have_sarea_h="yes"], [have_sarea_h="no"],[-])
AC_PREPROC_IFELSE([AC_LANG_PROGRAM([[
#include <xorg-server.h>
#include <dristruct.h>
]])],
[have_dristruct_h="yes"], [have_dristruct_h="no"],[-])
AC_CHECK_HEADER([damage.h],
[have_damage_h="yes"], [have_damage_h="no"],[-])
CPPFLAGS="$save_CPPFLAGS"
PKG_CHECK_MODULES(LIBUDEV, [libudev], [LIBUDEV=yes], [LIBUDEV=no])
if test "x$LIBUDEV" = xyes; then
AC_DEFINE(HAVE_LIBUDEV, 1,[libudev support])
fi
AC_MSG_CHECKING([whether to include DRI support])
if test x$DRI = xauto; then
if test "$have_dri_h" = yes -a \
"$have_sarea_h" = yes -a \
"$have_dristruct_h" = yes; then
DRI="yes"
else
DRI="no"
fi
fi
AC_MSG_RESULT([$DRI])
AM_CONDITIONAL(DRI, test x$DRI = xyes)
if test "$DRI" = yes; then
AC_DEFINE(XF86DRI,1,[Enable DRI driver support])
AC_DEFINE(XF86DRI_DEVEL,1,[Enable developmental DRI driver support])
if test "$have_damage_h" = yes; then
AC_DEFINE(DAMAGE,1,[Use Damage extension])
fi
save_CFLAGS="$CFLAGS"
CFLAGS="$XORG_CFLAGS $DRI_CFLAGS $CFLAGS"
if test "$DRM_MODE" = yes; then
AC_CHECK_HEADER(xf86drmMode.h,[DRM_MODE=yes],[DRM_MODE=no],[#include <stdint.h>
#include <stdlib.h>])
if test "x$DRM_MODE" = xyes; then
PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.35 libdrm_radeon],
[LIBDRM_RADEON=yes], [LIBDRM_RADEON=no])
if test "x$LIBDRM_RADEON" = xyes; then
AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
AC_DEFINE(RADEON_DRI2, 1,[Enable DRI2 code])
else
DRM_MODE=no
fi
PKG_CHECK_MODULES(LIBUDEV, [libudev], [LIBUDEV=yes], [LIBUDEV=no])
if test "x$LIBUDEV" = xyes; then
AC_DEFINE(HAVE_LIBUDEV, 1,[libudev support])
fi
fi
fi
CFLAGS="$save_CFLAGS"
else
DRM_MODE=no
fi
AM_CONDITIONAL(DRM_MODE, test x$DRM_MODE = xyes)
AM_CONDITIONAL(LIBUDEV, test x$LIBUDEV = xyes)
AC_DEFINE(USE_XAA, 1, [Build support for XAA])
# Properly handle EXA.
AC_MSG_CHECKING([whether to enable EXA support])
if test "x$EXA" = xyes; then
AC_MSG_RESULT(yes)
SAVE_CPPFLAGS="$CPPFLAGS"
CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
AC_CHECK_HEADER(exa.h,
[have_exa_h="yes"], [have_exa_h="no"])
CPPFLAGS="$SAVE_CPPFLAGS"
else
AC_MSG_RESULT(no)
fi
SAVE_CPPFLAGS="$CPPFLAGS"
CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
if test "x$have_exa_h" = xyes; then
AC_MSG_CHECKING([whether EXA version is at least 2.0.0])
AC_PREPROC_IFELSE([AC_LANG_PROGRAM([[
#include "exa.h"
#if EXA_VERSION_MAJOR < 2
#error OLD EXA!
#endif
]])],
[USE_EXA=yes],
[USE_EXA=no])
AC_MSG_RESULT($USE_EXA)
if test "x$USE_EXA" = xyes; then
AC_DEFINE(USE_EXA, 1, [Build support for Exa])
fi
fi
AC_CHECK_DECL(xf86XVFillKeyHelperDrawable,
[AC_DEFINE(HAVE_XV_DRAWABLE_HELPER, 1, [Have xf86XVFillKeyHelperDrawable prototype])],
[],
[#include <xf86xv.h>])
AC_CHECK_DECL(xf86ModeBandwidth,
[AC_DEFINE(HAVE_XF86MODEBANDWIDTH, 1, [Have xf86ModeBandwidth prototype])],
@ -248,10 +136,6 @@ fi
CPPFLAGS="$SAVE_CPPFLAGS"
AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes)
AM_CONDITIONAL(XF86DRM_MODE, test "x$LIBDRM_RADEON" = xyes)
if test "x$XSERVER_LIBPCIACCESS" = xyes; then
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
@ -318,11 +202,6 @@ b = bswap16(a);
fi
fi
case $host_os in
*linux*)
AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;;
esac
AC_SUBST([moduledir])
DRIVER_NAME=ati
@ -356,10 +235,6 @@ echo " exec_prefix: $exec_prefix"
echo " libdir: $libdir"
echo " includedir: $includedir"
echo ""
echo " Kernel modesetting: $DRM_MODE"
echo ""
echo " CFLAGS: $CFLAGS"
echo " CXXFLAGS: $CXXFLAGS"

983
src/AtomBios/CD_Operations.c
View file

@ -1,983 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/**
Module Name:
CD_Operations.c
Abstract:
Functions Implementing Command Operations and other common functions
Revision History:
NEG:27.09.2002 Initiated.
--*/
#define __SW_4
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <X11/Xos.h>
#include "xorg-server.h"
#include "compiler.h"
#include "Decoder.h"
VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData);
UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable);
WRITE_IO_FUNCTION WritePCIFunctions[8] = {
WritePCIReg32,
WritePCIReg16, WritePCIReg16, WritePCIReg16,
WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8
};
WRITE_IO_FUNCTION WriteIOFunctions[8] = {
WriteSysIOReg32,
WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16,
WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8
};
READ_IO_FUNCTION ReadPCIFunctions[8] = {
(READ_IO_FUNCTION)ReadPCIReg32,
(READ_IO_FUNCTION)ReadPCIReg16,
(READ_IO_FUNCTION)ReadPCIReg16,
(READ_IO_FUNCTION)ReadPCIReg16,
(READ_IO_FUNCTION)ReadPCIReg8,
(READ_IO_FUNCTION)ReadPCIReg8,
(READ_IO_FUNCTION)ReadPCIReg8,
(READ_IO_FUNCTION)ReadPCIReg8
};
READ_IO_FUNCTION ReadIOFunctions[8] = {
(READ_IO_FUNCTION)ReadSysIOReg32,
(READ_IO_FUNCTION)ReadSysIOReg16,
(READ_IO_FUNCTION)ReadSysIOReg16,
(READ_IO_FUNCTION)ReadSysIOReg16,
(READ_IO_FUNCTION)ReadSysIOReg8,
(READ_IO_FUNCTION)ReadSysIOReg8,
(READ_IO_FUNCTION)ReadSysIOReg8,
(READ_IO_FUNCTION)ReadSysIOReg8
};
READ_IO_FUNCTION GetParametersDirectArray[8]={
GetParametersDirect32,
GetParametersDirect16,GetParametersDirect16,GetParametersDirect16,
GetParametersDirect8,GetParametersDirect8,GetParametersDirect8,
GetParametersDirect8
};
COMMANDS_DECODER PutDataFunctions[6] = {
PutDataRegister,
PutDataPS,
PutDataWS,
PutDataFB,
PutDataPLL,
PutDataMC
};
CD_GET_PARAMETERS GetDestination[6] = {
GetParametersRegister,
GetParametersPS,
GetParametersWS,
GetParametersFB,
GetParametersPLL,
GetParametersMC
};
COMMANDS_DECODER SkipDestination[6] = {
SkipParameters16,
SkipParameters8,
SkipParameters8,
SkipParameters8,
SkipParameters8,
SkipParameters8
};
CD_GET_PARAMETERS GetSource[8] = {
GetParametersRegister,
GetParametersPS,
GetParametersWS,
GetParametersFB,
GetParametersIndirect,
GetParametersDirect,
GetParametersPLL,
GetParametersMC
};
UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF};
UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24};
UINT8 DestinationAlignmentShift[4] = {0,8,16,24};
#define INDIRECTIO_ID 1
#define INDIRECTIO_END_OF_ID 9
VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp);
VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={
{IndirectIOCommand,1},
{IndirectIOCommand,2},
{ReadIndReg32,3},
{WriteIndReg32,3},
{IndirectIOCommand_CLEAR,3},
{IndirectIOCommand_SET,3},
{IndirectIOCommand_MOVE_INDEX,4},
{IndirectIOCommand_MOVE_ATTR,4},
{IndirectIOCommand_MOVE_DATA,4},
{IndirectIOCommand,3}
};
VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
}
VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) &
(0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
}
VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2])
& (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
}
VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2])
& (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
}
VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
}
VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
}
UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
// if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID;
// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable;
while (*pParserTempData->IndirectIOTablePointer)
{
if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) &&
(pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData))
{
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID)
{
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1)));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
return 0;
}
VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=(UINT32)UINT16LE_TO_CPU(pParserTempData->pCmd->Parameters.WordXX.PA_Destination);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort){
case ATI_RegsPort:
if (pParserTempData->CurrentPortID == INDIRECT_IO_MM)
{
if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2;
WriteReg32( pParserTempData);
} else
{
pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE;
IndirectInputOutput(pParserTempData);
}
break;
case PCI_Port:
WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
break;
case SystemIO_Port:
WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
break;
}
}
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32),
pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C)
*(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32;
else
switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)
{
case WS_REMINDER_C:
pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32;
break;
case WS_QUOTIENT_C:
pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32;
break;
case WS_DATAPTR_C:
#ifndef UEFI_BUILD
pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32;
#else
pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32;
#endif
break;
case WS_SHIFT_C:
pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32;
break;
case WS_FB_WINDOW_C:
pParserTempData->CurrentFB_Window=pParserTempData->DestData32;
break;
case WS_ATTRIBUTES_C:
pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32;
break;
case WS_REGPTR_C:
pParserTempData->CurrentRegBlock=(UINT16)pParserTempData->DestData32;
break;
}
}
VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
//Make an Index from address first, then add to the Index
pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
WriteFrameBuffer32(pParserTempData);
}
VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
WritePLL32( pParserTempData );
}
VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
WriteMC32( pParserTempData );
}
VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
}
VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
}
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
{
case PCI_Port:
return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
case SystemIO_Port:
return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
case ATI_RegsPort:
default:
if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData );
else
{
pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ;
return IndirectInputOutput(pParserTempData);
}
}
}
UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT32 data;
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
data = UINT32LE_TO_CPU(ldl_u(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index));
return data;
}
UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
if (pParserTempData->Index < WS_QUOTIENT_C)
return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index);
else
switch (pParserTempData->Index)
{
case WS_REMINDER_C:
return pParserTempData->MultiplicationOrDivision.Division.Reminder32;
case WS_QUOTIENT_C:
return pParserTempData->MultiplicationOrDivision.Division.Quotient32;
case WS_DATAPTR_C:
return (UINT32)pParserTempData->CurrentDataBlock;
case WS_OR_MASK_C:
return ((UINT32)1) << pParserTempData->Shift2MaskConverter;
case WS_AND_MASK_C:
return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter);
case WS_FB_WINDOW_C:
return pParserTempData->CurrentFB_Window;
case WS_ATTRIBUTES_C:
return pParserTempData->AttributesData;
case WS_REGPTR_C:
return (UINT32)pParserTempData->CurrentRegBlock;
}
return 0;
}
UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
return ReadFrameBuffer32(pParserTempData);
}
UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
return ReadPLL32( pParserTempData );
}
UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
return ReadMC32( pParserTempData );
}
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT32 ret;
pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
ret = UINT32LE_TO_CPU(ldl_u((UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock)));
return ret;
}
UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentByte0;
pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
return pParserTempData->Index;
}
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentDword;
pParserTempData->Index=UINT32LE_TO_CPU(ldl_u((UINT32*)pParserTempData->pWorkingTableData->IP));
pParserTempData->pWorkingTableData->IP+=sizeof(UINT32);
return pParserTempData->Index;
}
UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
}
VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
}
VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
}
VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
} else
{
SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData);
}
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
{
pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 |= pParserTempData->SourceData32;
} else
{
pParserTempData->DestData32=pParserTempData->SourceData32;
}
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT8 src;
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
src = pParserTempData->CD_Mask.SrcAlignment;
pParserTempData->SourceData32=GetParametersDirect(pParserTempData);
pParserTempData->Index=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
pParserTempData->DestData32 &= pParserTempData->SourceData32;
pParserTempData->Index >>= SourceAlignmentShift[src];
pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
pParserTempData->DestData32 |= pParserTempData->Index;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
pParserTempData->DestData32 &= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 |= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 ^= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 <<= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 >>= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 += pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonSourceDataTransformation(pParserTempData);
pParserTempData->DestData32 -= pParserTempData->SourceData32;
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonOperationDataTransformation(pParserTempData);
pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32;
}
VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonOperationDataTransformation(pParserTempData);
pParserTempData->MultiplicationOrDivision.Division.Quotient32=
pParserTempData->DestData32 / pParserTempData->SourceData32;
pParserTempData->MultiplicationOrDivision.Division.Reminder32=
pParserTempData->DestData32 % pParserTempData->SourceData32;
}
VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonOperationDataTransformation(pParserTempData);
// Here we just set flags based on evaluation
if (pParserTempData->DestData32==pParserTempData->SourceData32)
pParserTempData->CompareFlags = Equal;
else
pParserTempData->CompareFlags =
(UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above);
}
VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
if (pParserTempData->ParametersType.Destination == 0 &&
pParserTempData->Multipurpose.CurrentPort == ATI_RegsPort &&
pParserTempData->Index == 0) {
pParserTempData->DestData32 = 0;
} else
pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]);
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetParametersDirect8(pParserTempData);
// save original value of the destination
pParserTempData->Index = pParserTempData->DestData32 & ~mask;
pParserTempData->DestData32 &= mask;
if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE)
pParserTempData->DestData32 <<= pParserTempData->SourceData32; else
pParserTempData->DestData32 >>= pParserTempData->SourceData32;
// Clear any bits shifted out of masked area...
pParserTempData->DestData32 &= mask;
// ... and restore the area outside of masked with original values
pParserTempData->DestData32 |= pParserTempData->Index;
// write data back
PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
}
VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
CommonOperationDataTransformation(pParserTempData);
pParserTempData->CompareFlags =
(UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal);
}
VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->CurrentFB_Window=pParserTempData->SourceData32;
}
VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
pParserTempData->pWorkingTableData->IP++;
pParserTempData->DestData32=GetParametersDirect(pParserTempData);
pParserTempData->Index=GetParametersDirect16(pParserTempData);
if (pParserTempData->SourceData32 == pParserTempData->DestData32)
{
pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index);
return;
}
}
}
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
}
VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT8 value;
UINT16* pMasterDataTable;
value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
if (value == 0) pParserTempData->CurrentDataBlock=0; else
{
if (value == DB_CURRENT_COMMAND_TABLE)
{
pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image);
} else
{
pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData);
pParserTempData->CurrentDataBlock= UINT16LE_TO_CPU((TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]);
}
}
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
}
VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort;
pParserTempData->CurrentPortID = (UINT8)UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CurrentRegBlock = UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
//Atavism!!! Review!!!
VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination;
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY);
}
VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 =
((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
DelayMilliseconds(pParserTempData);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
}
VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32 =
((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
DelayMicroseconds(pParserTempData);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
}
VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->SourceData32 =
((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
PostCharOutput(pParserTempData);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
}
VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->SourceData32 =
((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
CallerDebugFunc(pParserTempData);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
}
VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->pWorkingTableData->IP+=UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination)+sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT16* MasterTableOffset;
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData);
if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO
{
ATOM_TABLE_ATTRIBUTE lTableAttr;
pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value);
lTableAttr = GetCommandTableAttribute(pParserTempData->pWorkingTableData->pTableHead);
pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = (lTableAttr.PS_SizeInBytes >>2);
pParserTempData->pDeviceData->pParameterSpace+=
pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable;
pParserTempData->Status=CD_CALL_TABLE;
pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset;
}
}
VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
}
static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Status = CD_NOT_IMPLEMENTED;
}
VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if ((pParserTempData->ParametersType.Destination == NoCondition) ||
(pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags ))
{
pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
}
VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if ((pParserTempData->CompareFlags == Equal) ||
(pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination))
{
pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
}
VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if (pParserTempData->CompareFlags != Equal)
{
pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
}
COMMANDS_PROPERTIES CallTable[] =
{
{ NULL, 0,0},
{ ProcessMove, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessMove, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessMove, destMC, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessAnd, destMC, sizeof(COMMAND_HEADER)},
{ ProcessOr, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessOr, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessOr, destMC, sizeof(COMMAND_HEADER)},
{ ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessShift, destMC, sizeof(COMMAND_HEADER)},
{ ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessShift, destMC, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessMUL, destMC, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessDIV, destMC, sizeof(COMMAND_HEADER)},
{ ProcessADD, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessADD, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessADD, destMC, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessSUB, destMC, sizeof(COMMAND_HEADER)},
{ cmdSet_ATI_Port, ATI_RegsPort, 0},
{ cmdSet_X_Port, PCI_Port, 0},
{ cmdSet_X_Port, SystemIO_Port, 0},
{ cmdSet_Reg_Block, 0, 0},
{ ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessCompare, destMC, sizeof(COMMAND_HEADER)},
{ ProcessSwitch, 0, sizeof(COMMAND_HEADER)},
{ ProcessJump, NoCondition, 0},
{ ProcessJump, Equal, 0},
{ ProcessJump, Below, 0},
{ ProcessJump, Above, 0},
{ ProcessJumpE, Below, 0},
{ ProcessJumpE, Above, 0},
{ ProcessJumpNE, 0, 0},
{ ProcessTest, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessTest, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessTest, destMC, sizeof(COMMAND_HEADER)},
{ cmdDelay_Millisec,0, 0},
{ cmdDelay_Microsec,0, 0},
{ cmdCall_Table, 0, 0},
/*cmdRepeat*/ { NotImplemented, 0, 0},
{ ProcessClear, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessClear, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessClear, destMC, sizeof(COMMAND_HEADER)},
{ cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
/*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
{ ProcessMask, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessMask, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessMask, destMC, sizeof(COMMAND_HEADER)},
/*cmdPost_Card*/ { ProcessPostChar, 0, 0},
/*cmdBeep*/ { NotImplemented, 0, 0},
/*cmdSave_Reg*/ { NotImplemented, 0, 0},
/*cmdRestore_Reg*/{ NotImplemented, 0, 0},
{ cmdSetDataBlock, 0, 0},
{ ProcessXor, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessXor, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessXor, destMC, sizeof(COMMAND_HEADER)},
{ ProcessShl, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessShl, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessShl, destMC, sizeof(COMMAND_HEADER)},
{ ProcessShr, destRegister, sizeof(COMMAND_HEADER)},
{ ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)},
{ ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)},
{ ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)},
{ ProcessShr, destPLL, sizeof(COMMAND_HEADER)},
{ ProcessShr, destMC, sizeof(COMMAND_HEADER)},
/*cmdDebug*/ { ProcessDebug, 0, 0},
{ ProcessDS, 0, 0},
};
// EOF

258
src/AtomBios/Decoder.c
View file

@ -1,258 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/**
Module Name:
Decoder.c
Abstract:
Commands Decoder
Revision History:
NEG:24.09.2002 Initiated.
--*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <X11/Xos.h>
#include "xorg-server.h"
#include "Decoder.h"
#ifndef DISABLE_EASF
#include "easf.h"
#endif
#define INDIRECT_IO_TABLE (((UINT16)(ULONG_PTR)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) )
extern COMMANDS_PROPERTIES CallTable[];
UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode;
pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize;
pParserTempData->ParametersType.Destination=CallTable[opcode].destination;
pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source;
pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment;
pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment;
return opcode;
}
UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
{
UINT16 *MasterTableOffset;
#ifndef DISABLE_EASF
if (pDeviceData->format == TABLE_FORMAT_EASF)
{
/*
make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize.
*/
MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+(UINT16LE_TO_CPU(((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset));
} else
#endif
{
#ifndef UEFI_BUILD
MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image);
MasterTableOffset = (UINT16 *)((ULONG)UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset) + pDeviceData->pBIOS_Image );
MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables);
#else
MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables));
#endif
}
return MasterTableOffset;
}
UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
{
UINT16 *MasterTableOffset;
#ifndef UEFI_BUILD
MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image);
MasterTableOffset = (UINT16 *)((ULONG)(UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset)) + pDeviceData->pBIOS_Image );
MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables);
#else
MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables));
#endif
return MasterTableOffset;
}
UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable)
{
#ifndef DISABLE_EASF
UINT16 i;
if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF)
{
/*
Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[]
((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize;
((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID;
usFunctionID has to be shifted left by 2 before compare it to the value provided by caller.
*/
for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4)
if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK));
return 1;
} else
#endif
{
return IndexInMasterTable;
}
}
ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader)
{
ATOM_TABLE_ATTRIBUTE_ACCESS lTableAccess;
/* It's unclear whether this union trick breaks C aliasing rules,
* however, it's explicitely permitted by gcc, and we have other
* case where the code relies on a union being accessed by either
* of the "ways" and stay consistent so if a compiler breaks this
* assumption, it will probably need us to compile without strict
* aliasing enforcement
*/
lTableAccess.sbfAccess = ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pTableHeader)->TableAttribute;
lTableAccess.susAccess = UINT16LE_TO_CPU(lTableAccess.susAccess);
return lTableAccess.sbfAccess;
}
CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable)
{
PARSER_TEMP_DATA ParserTempData;
WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData;
memset(&ParserTempData, 0, sizeof(PARSER_TEMP_DATA));
ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData;
#ifndef DISABLE_EASF
if (pDeviceData->format == TABLE_FORMAT_EASF)
{
ParserTempData.IndirectIOTablePointer = 0;
} else
#endif
{
ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData);
ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE])) + pDeviceData->pBIOS_Image);
ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER);
}
ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData);
IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable);
if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO
{
ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable;
ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort;
ParserTempData.CurrentPortID=INDIRECT_IO_MM;
ParserTempData.CurrentRegBlock=0;
ParserTempData.CurrentFB_Window=0;
prevWorkingTableData=NULL;
ParserTempData.Status=CD_CALL_TABLE;
do{
if (ParserTempData.Status==CD_CALL_TABLE)
{
IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable;
if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO
{
ATOM_TABLE_ATTRIBUTE lTableAttr;
lTableAttr = GetCommandTableAttribute(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image);
#ifndef UEFI_BUILD
ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
#else
ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
#endif
if (ParserTempData.pWorkingTableData!=NULL)
{
ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA));
#ifndef UEFI_BUILD
ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image);
#else
ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]));
#endif
ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER);
ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData;
prevWorkingTableData=ParserTempData.pWorkingTableData;
ParserTempData.Status = CD_SUCCESS;
} else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR;
} else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND;
}
if (!CD_ERROR(ParserTempData.Status))
{
ParserTempData.Status = CD_SUCCESS;
while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status))
{
if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
{
ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP;
if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
{
ParserTempData.Status=CD_COMPLETED;
prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData;
FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData);
ParserTempData.pWorkingTableData=prevWorkingTableData;
if (prevWorkingTableData!=NULL)
{
ATOM_TABLE_ATTRIBUTE lTableAttr;
lTableAttr = GetCommandTableAttribute(ParserTempData.pWorkingTableData->pTableHead);
ParserTempData.pDeviceData->pParameterSpace-=(lTableAttr.PS_SizeInBytes>>2);
}
// if there is a parent table where to return, then restore PS_pointer to the original state
}
else
{
IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
(*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
#if (PARSER_TYPE!=DRIVER_TYPE_PARSER)
BIOS_STACK_MODIFIER();
#endif
}
}
else
{
ParserTempData.Status=CD_INVALID_OPCODE;
break;
}
} // while
} // if
else
break;
} while (prevWorkingTableData!=NULL);
if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS;
return ParserTempData.Status;
} else return CD_SUCCESS;
}
// EOF

354
src/AtomBios/hwserv_drv.c
View file

@ -1,354 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/**
Module Name:
hwserv_drv.c
Abstract:
Functions defined in the Command Decoder Specification document
Revision History:
NEG:27.09.2002 Initiated.
--*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <X11/Xos.h>
#include "xorg-server.h"
#include "Decoder.h"
//trace settings
#if DEBUG_OUTPUT_DEVICE & 1
#define TRACE_USING_STDERR //define it to use stderr as trace output,
#endif
#if DEBUG_OUTPUT_DEVICE & 2
#define TRACE_USING_RS232
#endif
#if DEBUG_OUTPUT_DEVICE & 4
#define TRACE_USING_LPT
#endif
#if DEBUG_PARSER == 4
#define IO_TRACE //IO access trace switch, undefine it to turn off
#define PCI_TRACE //PCI access trace switch, undefine it to turn off
#define MEM_TRACE //MEM access trace switch, undefine it to turn off
#endif
UINT32 CailReadATIRegister(VOID*,UINT32);
VOID CailWriteATIRegister(VOID*,UINT32,UINT32);
VOID* CailAllocateMemory(VOID*,UINT16);
VOID CailReleaseMemory(VOID *,VOID *);
VOID CailDelayMicroSeconds(VOID *,UINT32 );
VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16);
VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16);
UINT32 CailReadFBData(VOID*,UINT32);
VOID CailWriteFBData(VOID*,UINT32,UINT32);
ULONG CailReadPLL(VOID *Context ,ULONG Address);
VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data);
ULONG CailReadMC(VOID *Context ,ULONG Address);
VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data);
#if DEBUG_PARSER>0
VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16);
#endif
// Delay function
#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000);
}
VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32);
}
#endif
VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
}
VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
}
// PCI READ Access
#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT8 rvl;
CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8));
return rvl;
}
#endif
#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT16 rvl;
CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16));
return rvl;
}
#endif
#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT32 rvl;
CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32));
return rvl;
}
#endif
// PCI WRITE Access
#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8));
}
#endif
#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16));
}
#endif
#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32));
}
#endif
// System IO Access
#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT8 rvl;
rvl=0;
//rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8));
return rvl;
}
#endif
#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT16 rvl;
rvl=0;
//rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16));
return rvl;
}
#endif
#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT32 rvl;
rvl=0;
//rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32));
return rvl;
}
#endif
// PCI WRITE Access
#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
//WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value);
}
#endif
#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
//WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value);
}
#endif
#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
//WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value);
}
#endif
// ATI Registers Memory Mapped Access
#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS)
UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
}
VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 );
}
VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)));
}
VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)),pWorkingTableData->IndirectData);
}
#endif
// ATI Registers IO Mapped Access
#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS )
UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
//return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
return 0;
}
VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
// return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 );
}
#endif
// access to Frame buffer, dummy function, need more information to implement it
UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 ));
}
VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32);
}
VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize)
{
if(MemSize)
return(CailAllocateMemory(pDeviceData->CAIL,MemSize));
else
return NULL;
}
VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData)
{
if( pWorkingTableData)
CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData);
}
UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT32 ReadData;
ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
return ReadData;
}
VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
}
UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
UINT32 ReadData;
ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
return ReadData;
}
VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
}
#if DEBUG_PARSER>0
VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str)
{
CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS);
}
VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type )
{
CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type);
}
#endif
// EOF

172
src/AtomBios/includes/CD_Common_Types.h
View file

@ -1,172 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*++
Module Name:
CD_Common_Types.h
Abstract:
Defines common data types to use across platforms/SW components
Revision History:
NEG:17.09.2002 Initiated.
--*/
#ifndef _COMMON_TYPES_H_
#define _COMMON_TYPES_H_
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#ifndef LINUX
#if _MSC_EXTENSIONS
//
// use Microsoft* C complier dependent interger width types
//
// typedef unsigned __int64 uint64_t;
// typedef __int64 int64_t;
typedef unsigned __int32 uint32_t;
typedef __int32 int32_t;
#elif defined (__linux__) || defined (__NetBSD__) \
|| defined(__sun) || defined(__OpenBSD__) \
|| defined (__FreeBSD__) || defined(__DragonFly__) || defined(__GLIBC__)
typedef unsigned int uint32_t;
typedef int int32_t;
#else
typedef unsigned long uint32_t;
typedef signed long int32_t;
#endif
typedef unsigned char uint8_t;
#if (defined(__sun) && defined(_CHAR_IS_SIGNED))
typedef char int8_t;
#else
typedef signed char int8_t;
#endif
typedef unsigned short uint16_t;
typedef signed short int16_t;
#endif
#ifndef UEFI_BUILD
typedef signed int intn_t;
typedef unsigned int uintn_t;
#else
#ifndef EFIX64
typedef signed int intn_t;
typedef unsigned int uintn_t;
#endif
#endif
#ifndef FGL_LINUX
#pragma warning ( disable : 4142 )
#endif
#ifndef VOID
typedef void VOID;
#endif
#ifndef UEFI_BUILD
typedef intn_t INTN;
typedef uintn_t UINTN;
#else
#ifndef EFIX64
typedef intn_t INTN;
typedef uintn_t UINTN;
#endif
#endif
#ifndef BOOLEAN
typedef uint8_t BOOLEAN;
#endif
#ifndef INT8
typedef int8_t INT8;
#endif
#ifndef UINT8
typedef uint8_t UINT8;
#endif
#ifndef INT16
typedef int16_t INT16;
#endif
#ifndef UINT16
typedef uint16_t UINT16;
#endif
#ifndef INT32
typedef int32_t INT32;
#endif
#ifndef UINT32
typedef uint32_t UINT32;
#endif
//typedef int64_t INT64;
//typedef uint64_t UINT64;
typedef uint8_t CHAR8;
typedef uint16_t CHAR16;
#ifndef USHORT
typedef UINT16 USHORT;
#endif
#ifndef UCHAR
typedef UINT8 UCHAR;
#endif
#ifndef ULONG
typedef UINT32 ULONG;
#endif
#ifndef _WIN64
#ifndef ULONG_PTR
typedef unsigned long ULONG_PTR;
#endif // ULONG_PTR
#endif // _WIN64
//#define FAR __far
#ifndef TRUE
#define TRUE ((BOOLEAN) 1 == 1)
#endif
#ifndef FALSE
#define FALSE ((BOOLEAN) 0 == 1)
#endif
#ifndef NULL
#define NULL ((VOID *) 0)
#endif
//typedef UINTN CD_STATUS;
#ifndef FGL_LINUX
#pragma warning ( default : 4142 )
#endif
#ifndef ATOM_BIG_ENDIAN
#ifdef X_BYTE_ORDER
#if X_BYTE_ORDER == X_BIG_ENDIAN
#define ATOM_BIG_ENDIAN 1
#endif
#endif
#endif
#ifndef ATOM_BIG_ENDIAN
#define ATOM_BIG_ENDIAN 0
#endif
#endif // _COMMON_TYPES_H_
// EOF

50
src/AtomBios/includes/CD_Definitions.h
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@ -1,50 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*++
Module Name:
CD_Definitions.h
Abstract:
Defines Script Language commands
Revision History:
NEG:27.08.2002 Initiated.
--*/
#include "CD_Structs.h"
#ifndef _CD_DEFINITIONS_H
#define _CD_DEFINITIONS_H_
#ifdef DRIVER_PARSER
VOID *AllocateMemory(DEVICE_DATA *, UINT16);
VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* );
#endif
CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable);
//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData);
CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable);
UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData);
ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader);
#endif //CD_DEFINITIONS

181
src/AtomBios/includes/CD_Opcodes.h
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/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*++
Module Name:
CD_OPCODEs.h
Abstract:
Defines Command Decoder OPCODEs
Revision History:
NEG:24.09.2002 Initiated.
--*/
#ifndef _CD_OPCODES_H_
#define _CD_OPCODES_H_
typedef enum _OPCODE {
Reserved_00= 0, // 0 = 0x00
// MOVE_ group
MOVE_REG_OPCODE, // 1 = 0x01
FirstValidCommand=MOVE_REG_OPCODE,
MOVE_PS_OPCODE, // 2 = 0x02
MOVE_WS_OPCODE, // 3 = 0x03
MOVE_FB_OPCODE, // 4 = 0x04
MOVE_PLL_OPCODE, // 5 = 0x05
MOVE_MC_OPCODE, // 6 = 0x06
// Logic group
AND_REG_OPCODE, // 7 = 0x07
AND_PS_OPCODE, // 8 = 0x08
AND_WS_OPCODE, // 9 = 0x09
AND_FB_OPCODE, // 10 = 0x0A
AND_PLL_OPCODE, // 11 = 0x0B
AND_MC_OPCODE, // 12 = 0x0C
OR_REG_OPCODE, // 13 = 0x0D
OR_PS_OPCODE, // 14 = 0x0E
OR_WS_OPCODE, // 15 = 0x0F
OR_FB_OPCODE, // 16 = 0x10
OR_PLL_OPCODE, // 17 = 0x11
OR_MC_OPCODE, // 18 = 0x12
SHIFT_LEFT_REG_OPCODE, // 19 = 0x13
SHIFT_LEFT_PS_OPCODE, // 20 = 0x14
SHIFT_LEFT_WS_OPCODE, // 21 = 0x15
SHIFT_LEFT_FB_OPCODE, // 22 = 0x16
SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17
SHIFT_LEFT_MC_OPCODE, // 24 = 0x18
SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19
SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A
SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B
SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C
SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D
SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E
// Arithmetic group
MUL_REG_OPCODE, // 31 = 0x1F
MUL_PS_OPCODE, // 32 = 0x20
MUL_WS_OPCODE, // 33 = 0x21
MUL_FB_OPCODE, // 34 = 0x22
MUL_PLL_OPCODE, // 35 = 0x23
MUL_MC_OPCODE, // 36 = 0x24
DIV_REG_OPCODE, // 37 = 0x25
DIV_PS_OPCODE, // 38 = 0x26
DIV_WS_OPCODE, // 39 = 0x27
DIV_FB_OPCODE, // 40 = 0x28
DIV_PLL_OPCODE, // 41 = 0x29
DIV_MC_OPCODE, // 42 = 0x2A
ADD_REG_OPCODE, // 43 = 0x2B
ADD_PS_OPCODE, // 44 = 0x2C
ADD_WS_OPCODE, // 45 = 0x2D
ADD_FB_OPCODE, // 46 = 0x2E
ADD_PLL_OPCODE, // 47 = 0x2F
ADD_MC_OPCODE, // 48 = 0x30
SUB_REG_OPCODE, // 49 = 0x31
SUB_PS_OPCODE, // 50 = 0x32
SUB_WS_OPCODE, // 51 = 0x33
SUB_FB_OPCODE, // 52 = 0x34
SUB_PLL_OPCODE, // 53 = 0x35
SUB_MC_OPCODE, // 54 = 0x36
// Control grouop
SET_ATI_PORT_OPCODE, // 55 = 0x37
SET_PCI_PORT_OPCODE, // 56 = 0x38
SET_SYS_IO_PORT_OPCODE, // 57 = 0x39
SET_REG_BLOCK_OPCODE, // 58 = 0x3A
SET_FB_BASE_OPCODE, // 59 = 0x3B
COMPARE_REG_OPCODE, // 60 = 0x3C
COMPARE_PS_OPCODE, // 61 = 0x3D
COMPARE_WS_OPCODE, // 62 = 0x3E
COMPARE_FB_OPCODE, // 63 = 0x3F
COMPARE_PLL_OPCODE, // 64 = 0x40
COMPARE_MC_OPCODE, // 65 = 0x41
SWITCH_OPCODE, // 66 = 0x42
JUMP__OPCODE, // 67 = 0x43
JUMP_EQUAL_OPCODE, // 68 = 0x44
JUMP_BELOW_OPCODE, // 69 = 0x45
JUMP_ABOVE_OPCODE, // 70 = 0x46
JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47
JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48
JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49
TEST_REG_OPCODE, // 74 = 0x4A
TEST_PS_OPCODE, // 75 = 0x4B
TEST_WS_OPCODE, // 76 = 0x4C
TEST_FB_OPCODE, // 77 = 0x4D
TEST_PLL_OPCODE, // 78 = 0x4E
TEST_MC_OPCODE, // 79 = 0x4F
DELAY_MILLISEC_OPCODE, // 80 = 0x50
DELAY_MICROSEC_OPCODE, // 81 = 0x51
CALL_TABLE_OPCODE, // 82 = 0x52
REPEAT_OPCODE, // 83 = 0x53
// Miscellaneous group
CLEAR_REG_OPCODE, // 84 = 0x54
CLEAR_PS_OPCODE, // 85 = 0x55
CLEAR_WS_OPCODE, // 86 = 0x56
CLEAR_FB_OPCODE, // 87 = 0x57
CLEAR_PLL_OPCODE, // 88 = 0x58
CLEAR_MC_OPCODE, // 89 = 0x59
NOP_OPCODE, // 90 = 0x5A
EOT_OPCODE, // 91 = 0x5B
MASK_REG_OPCODE, // 92 = 0x5C
MASK_PS_OPCODE, // 93 = 0x5D
MASK_WS_OPCODE, // 94 = 0x5E
MASK_FB_OPCODE, // 95 = 0x5F
MASK_PLL_OPCODE, // 96 = 0x60
MASK_MC_OPCODE, // 97 = 0x61
// BIOS dedicated group
POST_CARD_OPCODE, // 98 = 0x62
BEEP_OPCODE, // 99 = 0x63
SAVE_REG_OPCODE, // 100 = 0x64
RESTORE_REG_OPCODE, // 101 = 0x65
SET_DATA_BLOCK_OPCODE, // 102 = 0x66
XOR_REG_OPCODE, // 103 = 0x67
XOR_PS_OPCODE, // 104 = 0x68
XOR_WS_OPCODE, // 105 = 0x69
XOR_FB_OPCODE, // 106 = 0x6a
XOR_PLL_OPCODE, // 107 = 0x6b
XOR_MC_OPCODE, // 108 = 0x6c
SHL_REG_OPCODE, // 109 = 0x6d
SHL_PS_OPCODE, // 110 = 0x6e
SHL_WS_OPCODE, // 111 = 0x6f
SHL_FB_OPCODE, // 112 = 0x70
SHL_PLL_OPCODE, // 113 = 0x71
SHL_MC_OPCODE, // 114 = 0x72
SHR_REG_OPCODE, // 115 = 0x73
SHR_PS_OPCODE, // 116 = 0x74
SHR_WS_OPCODE, // 117 = 0x75
SHR_FB_OPCODE, // 118 = 0x76
SHR_PLL_OPCODE, // 119 = 0x77
SHR_MC_OPCODE, // 120 = 0x78
DEBUG_OPCODE, // 121 = 0x79
CTB_DS_OPCODE, // 122 = 0x7A
LastValidCommand = CTB_DS_OPCODE,
// Extension specificaTOR
Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well
Reserved_FF = 255 // 255 = 0xFF
}OPCODE;
#endif // _CD_OPCODES_H_

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/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*++
Module Name:
CD_Struct.h
Abstract:
Defines Script Language commands
Revision History:
NEG:26.08.2002 Initiated.
--*/
#ifndef _CD_STRUCTS_H_
#define _CD_STRUCTS_H_
#include "CD_binding.h"
/* Endaianness should be specified before inclusion,
* default to little endian
*/
#ifndef ATOM_BIG_ENDIAN
#error Endian not specified
#endif
#ifdef UEFI_BUILD
typedef UINT16** PTABLE_UNIT_TYPE;
typedef UINTN TABLE_UNIT_TYPE;
#else
typedef UINT16* PTABLE_UNIT_TYPE;
typedef UINT16 TABLE_UNIT_TYPE;
#endif
#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!!
#define PARSER_MAJOR_REVISION 5
#define PARSER_MINOR_REVISION 0
//#include "atombios.h"
#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
#ifdef FGL_LINUX
#pragma pack(push,1)
#else
#pragma pack(push)
#pragma pack(1)
#endif
#endif
#include "CD_Common_Types.h"
#include "CD_Opcodes.h"
typedef UINT16 WORK_SPACE_SIZE;
typedef enum _CD_STATUS{
CD_SUCCESS,
CD_CALL_TABLE,
CD_COMPLETED=0x10,
CD_GENERAL_ERROR=0x80,
CD_INVALID_OPCODE,
CD_NOT_IMPLEMENTED,
CD_EXEC_TABLE_NOT_FOUND,
CD_EXEC_PARAMETER_ERROR,
CD_EXEC_PARSER_ERROR,
CD_INVALID_DESTINATION_TYPE,
CD_UNEXPECTED_BEHAVIOR,
CD_INVALID_SWITCH_OPERAND_SIZE
}CD_STATUS;
#define PARSER_STRINGS 0
#define PARSER_DEC 1
#define PARSER_HEX 2
#define DB_CURRENT_COMMAND_TABLE 0xFF
#define TABLE_FORMAT_BIOS 0
#define TABLE_FORMAT_EASF 1
#define EASF_TABLE_INDEX_MASK 0xfc
#define EASF_TABLE_ATTR_MASK 0x03
#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED)
#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS)
#if (BIOS_PARSER==1)
#ifdef _H2INC
#define STACK_BASED
#else
extern __segment farstack;
#define STACK_BASED __based(farstack)
#endif
#else
#define STACK_BASED
#endif
typedef enum _COMPARE_FLAGS{
Below,
Equal,
Above,
NotEqual,
Overflow,
NoCondition
}COMPARE_FLAGS;
typedef UINT16 IO_BASE_ADDR;
typedef struct _BUS_DEV_FUNC_PCI_ADDR{
UINT8 Register;
UINT8 Function;
UINT8 Device;
UINT8 Bus;
} BUS_DEV_FUNC_PCI_ADDR;
typedef struct _BUS_DEV_FUNC{
UINT8 Function : 3;
UINT8 Device : 5;
UINT8 Bus;
} BUS_DEV_FUNC;
#ifndef UEFI_BUILD
typedef struct _PCI_CONFIG_ACCESS_CF8{
UINT32 Reg : 8;
UINT32 Func : 3;
UINT32 Dev : 5;
UINT32 Bus : 8;
UINT32 Reserved: 7;
UINT32 Enable : 1;
} PCI_CONFIG_ACCESS_CF8;
#endif
typedef enum _MEM_RESOURCE {
Stack_Resource,
FrameBuffer_Resource,
BIOS_Image_Resource
}MEM_RESOURCE;
typedef enum _PORTS{
ATI_RegsPort,
PCI_Port,
SystemIO_Port
}PORTS;
typedef enum _OPERAND_TYPE {
typeRegister,
typeParamSpace,
typeWorkSpace,
typeFrameBuffer,
typeIndirect,
typeDirect,
typePLL,
typeMC
}OPERAND_TYPE;
typedef enum _DESTINATION_OPERAND_TYPE {
destRegister,
destParamSpace,
destWorkSpace,
destFrameBuffer,
destPLL,
destMC
}DESTINATION_OPERAND_TYPE;
typedef enum _SOURCE_OPERAND_TYPE {
sourceRegister,
sourceParamSpace,
sourceWorkSpace,
sourceFrameBuffer,
sourceIndirect,
sourceDirect,
sourcePLL,
sourceMC
}SOURCE_OPERAND_TYPE;
typedef enum _ALIGNMENT_TYPE {
alignmentDword,
alignmentLowerWord,
alignmentMiddleWord,
alignmentUpperWord,
alignmentByte0,
alignmentByte1,
alignmentByte2,
alignmentByte3
}ALIGNMENT_TYPE;
#define INDIRECT_IO_READ 0
#define INDIRECT_IO_WRITE 0x80
#define INDIRECT_IO_MM 0
#define INDIRECT_IO_PLL 1
#define INDIRECT_IO_MC 2
typedef struct _PARAMETERS_TYPE{
UINT8 Destination;
UINT8 Source;
}PARAMETERS_TYPE;
/* The following structures don't used to allocate any type of objects(variables).
they are serve the only purpose: Get proper access to data(commands), found in the tables*/
typedef struct _PA_BYTE_BYTE{
UINT8 PA_Destination;
UINT8 PA_Source;
UINT8 PA_Padding[8];
}PA_BYTE_BYTE;
typedef struct _PA_BYTE_WORD{
UINT8 PA_Destination;
UINT16 PA_Source;
UINT8 PA_Padding[7];
}PA_BYTE_WORD;
typedef struct _PA_BYTE_DWORD{
UINT8 PA_Destination;
UINT32 PA_Source;
UINT8 PA_Padding[5];
}PA_BYTE_DWORD;
typedef struct _PA_WORD_BYTE{
UINT16 PA_Destination;
UINT8 PA_Source;
UINT8 PA_Padding[7];
}PA_WORD_BYTE;
typedef struct _PA_WORD_WORD{
UINT16 PA_Destination;
UINT16 PA_Source;
UINT8 PA_Padding[6];
}PA_WORD_WORD;
typedef struct _PA_WORD_DWORD{
UINT16 PA_Destination;
UINT32 PA_Source;
UINT8 PA_Padding[4];
}PA_WORD_DWORD;
typedef struct _PA_WORD_XX{
UINT16 PA_Destination;
UINT8 PA_Padding[8];
}PA_WORD_XX;
typedef struct _PA_BYTE_XX{
UINT8 PA_Destination;
UINT8 PA_Padding[9];
}PA_BYTE_XX;
/*The following 6 definitions used for Mask operation*/
typedef struct _PA_BYTE_BYTE_BYTE{
UINT8 PA_Destination;
UINT8 PA_AndMaskByte;
UINT8 PA_OrMaskByte;
UINT8 PA_Padding[7];
}PA_BYTE_BYTE_BYTE;
typedef struct _PA_BYTE_WORD_WORD{
UINT8 PA_Destination;
UINT16 PA_AndMaskWord;
UINT16 PA_OrMaskWord;
UINT8 PA_Padding[5];
}PA_BYTE_WORD_WORD;
typedef struct _PA_BYTE_DWORD_DWORD{
UINT8 PA_Destination;
UINT32 PA_AndMaskDword;
UINT32 PA_OrMaskDword;
UINT8 PA_Padding;
}PA_BYTE_DWORD_DWORD;
typedef struct _PA_WORD_BYTE_BYTE{
UINT16 PA_Destination;
UINT8 PA_AndMaskByte;
UINT8 PA_OrMaskByte;
UINT8 PA_Padding[6];
}PA_WORD_BYTE_BYTE;
typedef struct _PA_WORD_WORD_WORD{
UINT16 PA_Destination;
UINT16 PA_AndMaskWord;
UINT16 PA_OrMaskWord;
UINT8 PA_Padding[4];
}PA_WORD_WORD_WORD;
typedef struct _PA_WORD_DWORD_DWORD{
UINT16 PA_Destination;
UINT32 PA_AndMaskDword;
UINT32 PA_OrMaskDword;
}PA_WORD_DWORD_DWORD;
typedef union _PARAMETER_ACCESS {
PA_BYTE_XX ByteXX;
PA_BYTE_BYTE ByteByte;
PA_BYTE_WORD ByteWord;
PA_BYTE_DWORD ByteDword;
PA_WORD_BYTE WordByte;
PA_WORD_WORD WordWord;
PA_WORD_DWORD WordDword;
PA_WORD_XX WordXX;
/*The following 6 definitions used for Mask operation*/
PA_BYTE_BYTE_BYTE ByteByteAndByteOr;
PA_BYTE_WORD_WORD ByteWordAndWordOr;
PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr;
PA_WORD_BYTE_BYTE WordByteAndByteOr;
PA_WORD_WORD_WORD WordWordAndWordOr;
PA_WORD_DWORD_DWORD WordDwordAndDwordOr;
}PARAMETER_ACCESS;
typedef struct _COMMAND_ATTRIBUTE {
#if ATOM_BIG_ENDIAN
UINT8 DestinationAlignment:2;
UINT8 SourceAlignment:3;
UINT8 Source:3;
#else
UINT8 Source:3;
UINT8 SourceAlignment:3;
UINT8 DestinationAlignment:2;
#endif
}COMMAND_ATTRIBUTE;
typedef struct _SOURCE_DESTINATION_ALIGNMENT{
UINT8 DestAlignment;
UINT8 SrcAlignment;
}SOURCE_DESTINATION_ALIGNMENT;
typedef struct _MULTIPLICATION_RESULT{
UINT32 Low32Bit;
UINT32 High32Bit;
}MULTIPLICATION_RESULT;
typedef struct _DIVISION_RESULT{
UINT32 Quotient32;
UINT32 Reminder32;
}DIVISION_RESULT;
typedef union _DIVISION_MULTIPLICATION_RESULT{
MULTIPLICATION_RESULT Multiplication;
DIVISION_RESULT Division;
}DIVISION_MULTIPLICATION_RESULT;
typedef struct _COMMAND_HEADER {
UINT8 Opcode;
COMMAND_ATTRIBUTE Attribute;
}COMMAND_HEADER;
typedef struct _GENERIC_ATTRIBUTE_COMMAND{
COMMAND_HEADER Header;
PARAMETER_ACCESS Parameters;
} GENERIC_ATTRIBUTE_COMMAND;
typedef struct _COMMAND_TYPE_1{
UINT8 Opcode;
PARAMETER_ACCESS Parameters;
} COMMAND_TYPE_1;
typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{
UINT8 Opcode;
UINT16 CD_Offset16;
} COMMAND_TYPE_OPCODE_OFFSET16;
typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{
UINT8 Opcode;
UINT32 CD_Offset32;
} COMMAND_TYPE_OPCODE_OFFSET32;
typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{
UINT8 Opcode;
UINT8 Value;
} COMMAND_TYPE_OPCODE_VALUE_BYTE;
typedef union _COMMAND_SPECIFIC_UNION{
UINT8 ContinueSwitch;
UINT8 ControlOperandSourcePosition;
UINT8 IndexInMasterTable;
} COMMAND_SPECIFIC_UNION;
typedef struct _CD_GENERIC_BYTE{
#if ATOM_BIG_ENDIAN
UINT16 PS_SizeInDwordsUsedByCallingTable:5;
UINT16 CurrentPort:2;
UINT16 CommandAccessType:3;
UINT16 CurrentParameterSize:3;
UINT16 CommandType:3;
#else
UINT16 CommandType:3;
UINT16 CurrentParameterSize:3;
UINT16 CommandAccessType:3;
UINT16 CurrentPort:2;
UINT16 PS_SizeInDwordsUsedByCallingTable:5;
#endif
}CD_GENERIC_BYTE;
typedef UINT8 COMMAND_TYPE_OPCODE_ONLY;
typedef UINT8 COMMAND_HEADER_POINTER;
#if (PARSER_TYPE==BIOS_TYPE_PARSER)
typedef struct _DEVICE_DATA {
UINT32 STACK_BASED *pParameterSpace;
UINT8 *pBIOS_Image;
UINT8 format;
#if (IO_INTERFACE==PARSER_INTERFACE)
IO_BASE_ADDR IOBase;
#endif
} DEVICE_DATA;
#else
typedef struct _DEVICE_DATA {
UINT32 *pParameterSpace;
VOID *CAIL;
UINT8 *pBIOS_Image;
UINT32 format;
} DEVICE_DATA;
#endif
struct _PARSER_TEMP_DATA;
typedef UINT32 WORKSPACE_POINTER;
struct _WORKING_TABLE_DATA{
UINT8 * pTableHead;
COMMAND_HEADER_POINTER * IP; // Commands pointer
WORKSPACE_POINTER STACK_BASED * pWorkSpace;
struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData;
};
typedef struct _PARSER_TEMP_DATA{
DEVICE_DATA STACK_BASED *pDeviceData;
struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData;
UINT32 SourceData32;
UINT32 DestData32;
DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision;
UINT32 Index;
UINT32 CurrentFB_Window;
UINT32 IndirectData;
UINT16 CurrentRegBlock;
TABLE_UNIT_TYPE CurrentDataBlock;
UINT16 AttributesData;
// UINT8 *IndirectIOTable;
UINT8 *IndirectIOTablePointer;
GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand;
SOURCE_DESTINATION_ALIGNMENT CD_Mask;
PARAMETERS_TYPE ParametersType;
CD_GENERIC_BYTE Multipurpose;
UINT8 CompareFlags;
COMMAND_SPECIFIC_UNION CommandSpecific;
CD_STATUS Status;
UINT8 Shift2MaskConverter;
UINT8 CurrentPortID;
} PARSER_TEMP_DATA;
typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA;
typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
typedef struct _COMMANDS_PROPERTIES
{
COMMANDS_DECODER function;
UINT8 destination;
UINT8 headersize;
} COMMANDS_PROPERTIES;
typedef struct _INDIRECT_IO_PARSER_COMMANDS
{
COMMANDS_DECODER func;
UINT8 csize;
} INDIRECT_IO_PARSER_COMMANDS;
#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
#pragma pack(pop)
#endif
#endif

46
src/AtomBios/includes/CD_binding.h
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@ -1,46 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef NT_BUILD
#ifdef LH_BUILD
#include <ntddk.h>
#else
#include <miniport.h>
#endif // LH_BUILD
#endif // NT_BUILD
#if ((defined DBG) || (defined DEBUG))
#define DEBUG_PARSER 1 // enable parser debug output
#endif
#define USE_SWITCH_COMMAND 1
#define DRIVER_TYPE_PARSER 0x48
#define PARSER_TYPE DRIVER_TYPE_PARSER
#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y)
#define FreeWorkSpace(x,y) ReleaseMemory(x,y)
#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image))
#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead))

318
src/AtomBios/includes/CD_hw_services.h
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/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _HW_SERVICES_INTERFACE_
#define _HW_SERVICES_INTERFACE_
#include "CD_Common_Types.h"
#include "CD_Structs.h"
// CD - from Command Decoder
typedef UINT16 CD_REG_INDEX;
typedef UINT8 CD_PCI_OFFSET;
typedef UINT16 CD_FB_OFFSET;
typedef UINT16 CD_SYS_IO_PORT;
typedef UINT8 CD_MEM_TYPE;
typedef UINT8 CD_MEM_SIZE;
typedef VOID * CD_VIRT_ADDR;
typedef UINT32 CD_PHYS_ADDR;
typedef UINT32 CD_IO_ADDR;
/***********************ATI Registers access routines**************************/
VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
/************************PCI Registers access routines*************************/
UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
/***************************Frame buffer access routines************************/
UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
/******************System IO Registers access routines********************/
UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
/****************************Delay routines****************************************/
VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value
VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
//************************Tracing/Debugging routines and macroses******************/
#define KEYPRESSED -1
#if (DEBUG_PARSER != 0)
#ifdef DRIVER_PARSER
VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str);
VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type );
// Level 1 : can use WorkingTableData or pDeviceData
#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string);
#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string)
#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC);
#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX);
// Level 2:can use pWorkingTableData
#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string)
#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC);
#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX);
// Level 3:can use pWorkingTableData
#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string)
#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC);
#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX);
#define CD_TRACE(string)
#define CD_WAIT(what)
#define CD_BREAKPOINT()
#else
VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console
VOID CD_postcode(UINT8 value); //output post code to debug console
VOID CD_print (UINT8 *str); //output text to debug console
VOID CD_print_dec(UINTN value); //output value in decimal format to debug console
VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console
VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console
VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires
VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium)
#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
#define CD_POSTCODE(value) CD_postcode(value)
#define CD_TRACE(string) CD_print(string)
#define CD_TRACETAB(string) CD_print(string)
#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value))
#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) )
#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
#define CD_WAIT(what) CD_wait((INT32)what)
#define CD_BREAKPOINT() CD_breakpoint()
#if (DEBUG_PARSER == 4)
#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
#define CD_POSTCODE_DL4(value) CD_postcode(value)
#define CD_TRACE_DL4(string) CD_print(string)
#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string)
#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value))
#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) )
#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
#define CD_WAIT_DL4(what) CD_wait((INT32)what)
#define CD_BREAKPOINT_DL4() CD_breakpoint()
#else
#define CD_ASSERT_DL4(condition)
#define CD_POSTCODE_DL4(value)
#define CD_TRACE_DL4(string)
#define CD_TRACETAB_DL4(string)
#define CD_TRACEDEC_DL4(value)
#define CD_TRACEHEX_DL4(value)
#define CD_TRACEBUF_DL4(pointer, len)
#define CD_WAIT_DL4(what)
#define CD_BREAKPOINT_DL4()
#endif
#if (DEBUG_PARSER >= 3)
#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
#define CD_POSTCODE_DL3(value) CD_postcode(value)
#define CD_TRACE_DL3(string) CD_print(string)
#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string)
#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value))
#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) )
#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
#define CD_WAIT_DL3(what) CD_wait((INT32)what)
#define CD_BREAKPOINT_DL3() CD_breakpoint()
#else
#define CD_ASSERT_DL3(condition)
#define CD_POSTCODE_DL3(value)
#define CD_TRACE_DL3(string)
#define CD_TRACETAB_DL3(string)
#define CD_TRACEDEC_DL3(value)
#define CD_TRACEHEX_DL3(value)
#define CD_TRACEBUF_DL3(pointer, len)
#define CD_WAIT_DL3(what)
#define CD_BREAKPOINT_DL3()
#endif
#if (DEBUG_PARSER >= 2)
#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
#define CD_POSTCODE_DL2(value) CD_postcode(value)
#define CD_TRACE_DL2(string) CD_print(string)
#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string)
#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value))
#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) )
#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
#define CD_WAIT_DL2(what) CD_wait((INT32)what)
#define CD_BREAKPOINT_DL2() CD_breakpoint()
#else
#define CD_ASSERT_DL2(condition)
#define CD_POSTCODE_DL2(value)
#define CD_TRACE_DL2(string)
#define CD_TRACETAB_DL2(string)
#define CD_TRACEDEC_DL2(value)
#define CD_TRACEHEX_DL2(value)
#define CD_TRACEBUF_DL2(pointer, len)
#define CD_WAIT_DL2(what)
#define CD_BREAKPOINT_DL2()
#endif
#if (DEBUG_PARSER >= 1)
#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
#define CD_POSTCODE_DL1(value) CD_postcode(value)
#define CD_TRACE_DL1(string) CD_print(string)
#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string)
#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value))
#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) )
#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
#define CD_WAIT_DL1(what) CD_wait((INT32)what)
#define CD_BREAKPOINT_DL1() CD_breakpoint()
#else
#define CD_ASSERT_DL1(condition)
#define CD_POSTCODE_DL1(value)
#define CD_TRACE_DL1(string)
#define CD_TRACETAB_DL1(string)
#define CD_TRACEDEC_DL1(value)
#define CD_TRACEHEX_DL1(value)
#define CD_TRACEBUF_DL1(pointer, len)
#define CD_WAIT_DL1(what)
#define CD_BREAKPOINT_DL1()
#endif
#endif //#ifdef DRIVER_PARSER
#else
#define CD_ASSERT(condition)
#define CD_POSTCODE(value)
#define CD_TRACE(string)
#define CD_TRACEDEC(value)
#define CD_TRACEHEX(value)
#define CD_TRACEBUF(pointer, len)
#define CD_WAIT(what)
#define CD_BREAKPOINT()
#define CD_ASSERT_DL4(condition)
#define CD_POSTCODE_DL4(value)
#define CD_TRACE_DL4(string)
#define CD_TRACETAB_DL4(string)
#define CD_TRACEDEC_DL4(value)
#define CD_TRACEHEX_DL4(value)
#define CD_TRACEBUF_DL4(pointer, len)
#define CD_WAIT_DL4(what)
#define CD_BREAKPOINT_DL4()
#define CD_ASSERT_DL3(condition)
#define CD_POSTCODE_DL3(value)
#define CD_TRACE_DL3(string)
#define CD_TRACETAB_DL3(string)
#define CD_TRACEDEC_DL3(value)
#define CD_TRACEHEX_DL3(value)
#define CD_TRACEBUF_DL3(pointer, len)
#define CD_WAIT_DL3(what)
#define CD_BREAKPOINT_DL3()
#define CD_ASSERT_DL2(condition)
#define CD_POSTCODE_DL2(value)
#define CD_TRACE_DL2(string)
#define CD_TRACETAB_DL2(string)
#define CD_TRACEDEC_DL2(value)
#define CD_TRACEHEX_DL2(value)
#define CD_TRACEBUF_DL2(pointer, len)
#define CD_WAIT_DL2(what)
#define CD_BREAKPOINT_DL2()
#define CD_ASSERT_DL1(condition)
#define CD_POSTCODE_DL1(value)
#define CD_TRACE_DL1(string)
#define CD_TRACETAB_DL1(string)
#define CD_TRACEDEC_DL1(value)
#define CD_TRACEHEX_DL1(value)
#define CD_TRACEBUF_DL1(pointer, len)
#define CD_WAIT_DL1(what)
#define CD_BREAKPOINT_DL1()
#endif //#if (DEBUG_PARSER > 0)
#ifdef CHECKSTACK
VOID CD_fillstack(UINT16 size);
UINT16 CD_checkstack(UINT16 size);
#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize)
#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize)
#else
#define CD_CHECKSTACK(stacksize) 0
#define CD_FILLSTACK(stacksize)
#endif
#endif

107
src/AtomBios/includes/Decoder.h
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@ -1,107 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*++
Module Name:
Decoder.h
Abstract:
Includes all helper headers
Revision History:
NEG:27.08.2002 Initiated.
--*/
#ifndef _DECODER_H_
#define _DECODER_H_
#define WS_QUOTIENT_C 64
#define WS_REMINDER_C (WS_QUOTIENT_C+1)
#define WS_DATAPTR_C (WS_REMINDER_C+1)
#define WS_SHIFT_C (WS_DATAPTR_C+1)
#define WS_OR_MASK_C (WS_SHIFT_C+1)
#define WS_AND_MASK_C (WS_OR_MASK_C+1)
#define WS_FB_WINDOW_C (WS_AND_MASK_C+1)
#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1)
#define WS_REGPTR_C (WS_ATTRIBUTES_C+1)
#define PARSER_VERSION_MAJOR 0x00000000
#define PARSER_VERSION_MINOR 0x0000000E
#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR)
#include "CD_Common_Types.h"
#include "atombios.h"
/* these depends on some struct defined in atombios.h */
#include "CD_binding.h"
#include "CD_hw_services.h"
#include "CD_Structs.h"
#include "CD_Opcodes.h"
#include "CD_Definitions.h"
#if ATOM_BIG_ENDIAN
extern UINT16 ATOM_BSWAP16(UINT16 x);
extern UINT32 ATOM_BSWAP32(UINT32 x);
#define CPU_TO_UINT16LE(x) ATOM_BSWAP16(x)
#define CPU_TO_UINT32LE(x) ATOM_BSWAP32(x)
#define UINT16LE_TO_CPU(x) ATOM_BSWAP16(x)
#define UINT32LE_TO_CPU(x) ATOM_BSWAP32(x)
#else
#define CPU_TO_UINT16LE(x) (x)
#define CPU_TO_UINT32LE(x) (x)
#define UINT16LE_TO_CPU(x) (x)
#define UINT32LE_TO_CPU(x) (x)
#endif
#define SOURCE_ONLY_CMD_TYPE 0//0xFE
#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD
#define DESTINATION_ONLY_CMD_TYPE 2//0xFC
#define ACCESS_TYPE_BYTE 0//0xF9
#define ACCESS_TYPE_WORD 1//0xF8
#define ACCESS_TYPE_DWORD 2//0xF7
#define SWITCH_TYPE_ACCESS 3//0xF6
#define CD_CONTINUE 0//0xFB
#define CD_STOP 1//0xFA
#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE)
#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand))
#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE))
#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE))
#define CheckCaseAndAdjustIP_Macro(size) \
if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\
pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\
pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\
}else{\
pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\
+sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\
}
#endif
/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/
// EOF

643
src/AtomBios/includes/ObjectID.h
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@ -1,643 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
#ifndef _OBJECTID_H
#define _OBJECTID_H
#if defined(_X86_)
#pragma pack(1)
#endif
/****************************************************/
/* Graphics Object Type Definition */
/****************************************************/
#define GRAPH_OBJECT_TYPE_NONE 0x0
#define GRAPH_OBJECT_TYPE_GPU 0x1
#define GRAPH_OBJECT_TYPE_ENCODER 0x2
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
/* External Third Party Encoders */
#define ENCODER_OBJECT_ID_SI170B 0x08
#define ENCODER_OBJECT_ID_CH7303 0x09
#define ENCODER_OBJECT_ID_CH7301 0x0A
#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
#define ENCODER_OBJECT_ID_TITFP513 0x0E
#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
#define ENCODER_OBJECT_ID_VT1623 0x10
#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
#define ENCODER_OBJECT_ID_VT1625 0x1A
#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
#define ENCODER_OBJECT_ID_DP_AN9801 0x1C
#define ENCODER_OBJECT_ID_DP_DP501 0x1D
#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E
#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F
#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20
#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21
#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04
#define CONNECTOR_OBJECT_ID_VGA 0x05
#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06
#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
#define CONNECTOR_OBJECT_ID_YPbPr 0x08
#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
#define CONNECTOR_OBJECT_ID_SCART 0x0B
#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
#define CONNECTOR_OBJECT_ID_LVDS 0x0E
#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F
#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10
#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
#define CONNECTOR_OBJECT_ID_eDP 0x14
#define CONNECTOR_OBJECT_ID_MXM 0x15
/* deleted */
/****************************************************/
/* Router Object ID Definition */
/****************************************************/
#define ROUTER_OBJECT_ID_NONE 0x00
#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
/****************************************************/
/* Generic Object ID Definition */
/****************************************************/
#define GENERIC_OBJECT_ID_NONE 0x00
#define GENERIC_OBJECT_ID_GLSYNC 0x01
#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
#define GENERIC_OBJECT_ID_MXM_OPM 0x03
/****************************************************/
/* Graphics Object ENUM ID Definition */
/****************************************************/
#define GRAPH_OBJECT_ENUM_ID1 0x01
#define GRAPH_OBJECT_ENUM_ID2 0x02
#define GRAPH_OBJECT_ENUM_ID3 0x03
#define GRAPH_OBJECT_ENUM_ID4 0x04
#define GRAPH_OBJECT_ENUM_ID5 0x05
#define GRAPH_OBJECT_ENUM_ID6 0x06
#define GRAPH_OBJECT_ENUM_ID7 0x07
/****************************************************/
/* Graphics Object ID Bit definition */
/****************************************************/
#define OBJECT_ID_MASK 0x00FF
#define ENUM_ID_MASK 0x0700
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
/****************************************************/
/* Graphics Object family definition */
/****************************************************/
#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
/****************************************************/
/* GPU Object ID definition - Shared with BIOS */
/****************************************************/
#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
/****************************************************/
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C
#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D
#define ENCODER_TITFP513_ENUM_ID1 0x210E
#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F
#define ENCODER_VT1623_ENUM_ID1 0x2110
#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111
#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B
#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C
#define ENCODER_DP_DP501_ENUM_ID1 0x211D
#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E
*/
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
/****************************************************/
/* Connector Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104
#define CONNECTOR_VGA_ENUM_ID1 0x3105
#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106
#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107
#define CONNECTOR_YPbPr_ENUM_ID1 0x3108
#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109
#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A
#define CONNECTOR_SCART_ENUM_ID1 0x310B
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D
#define CONNECTOR_LVDS_ENUM_ID1 0x310E
#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
*/
#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A
#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B
#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C
#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D
#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx
#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx
#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
/****************************************************/
/* Router Object ID definition - Shared with BIOS */
/****************************************************/
#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
/* deleted */
/****************************************************/
/* Generic Object ID definition - Shared with BIOS */
/****************************************************/
#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
/****************************************************/
/* Object Cap definition - Shared with BIOS */
/****************************************************/
#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
#if defined(_X86_)
#pragma pack()
#endif
#endif /*GRAPHICTYPE */

6137
src/AtomBios/includes/atombios.h
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File diff suppressed because it is too large Load diff

25
src/AtomBios/includes/regsdef.h
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@ -1,25 +0,0 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
//This is a dummy file used by driver-parser during compilation.
//Without this file, compatibility will be broken among ASICs and BIOs vs. driver
//James H. Apr. 22/03

80
src/Makefile.am
View file

@ -28,47 +28,15 @@
radeon_drv_la_LIBADD = $(LIBDRM_RADEON_LIBS)
if DRI
RADEON_DRI_SRCS = radeon_dri.c
radeon_drv_la_LIBADD += $(DRI_LIBS)
endif
RADEON_ATOMBIOS_SOURCES = \
AtomBios/CD_Operations.c \
AtomBios/Decoder.c \
AtomBios/hwserv_drv.c \
AtomBios/includes/atombios.h \
AtomBios/includes/CD_binding.h \
AtomBios/includes/CD_Common_Types.h \
AtomBios/includes/CD_Definitions.h \
AtomBios/includes/CD_hw_services.h \
AtomBios/includes/CD_Opcodes.h \
AtomBios/includes/CD_Structs.h \
AtomBios/includes/Decoder.h \
AtomBios/includes/ObjectID.h \
AtomBios/includes/regsdef.h
if XF86DRM_MODE
RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c
endif
if USE_EXA
RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c \
evergreen_exa.c evergreen_accel.c evergreen_shader.c evergreen_textured_videofuncs.c cayman_accel.c cayman_shader.c
endif
AM_CFLAGS = \
@LIBDRM_RADEON_CFLAGS@ \
@XORG_CFLAGS@ \
@DRI_CFLAGS@ \
@LIBUDEV_CFLAGS@ \
-DDISABLE_EASF \
-DENABLE_ALL_SERVICE_FUNCTIONS \
-DATOM_BIOS \
-DATOM_BIOS_PARSER \
-DDRIVER_PARSER
INCLUDES = -I$(srcdir)/AtomBios/includes
@LIBUDEV_CFLAGS@
if XSERVER_LIBPCIACCESS
ati_drv_la_LIBADD = $(PCIACCESS_LIBS)
@ -89,40 +57,14 @@ radeon_drv_la_LTLIBRARIES = radeon_drv.la
radeon_drv_la_LDFLAGS = -module -avoid-version
radeon_drv_ladir = @moduledir@/drivers
radeon_drv_la_SOURCES = \
radeon_accel.c radeon_cursor.c radeon_legacy_memory.c \
radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
radeon_vip.c radeon_misc.c radeon_probe.c \
legacy_crtc.c legacy_output.c \
radeon_textured_video.c radeon_xvmc.c radeon_pm.c \
radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \
$(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \
$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c \
radeon_accel.c radeon_legacy_memory.c \
radeon_driver.c radeon_video.c \
radeon_misc.c radeon_probe.c \
radeon_textured_video.c radeon_xvmc.c \
$(RADEON_EXA_SOURCES) \
$(RADEON_KMS_SRCS)
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
theatre_detect_drv_la_LDFLAGS = -module -avoid-version
theatre_detect_drv_ladir = @moduledir@/multimedia
theatre_detect_drv_la_SOURCES = \
theatre_detect.c theatre_detect_module.c
theatre_drv_la_LTLIBRARIES = theatre_drv.la
theatre_drv_la_LDFLAGS = -module -avoid-version
theatre_drv_ladir = @moduledir@/multimedia
theatre_drv_la_SOURCES = \
theatre.c theatre_module.c
theatre200_drv_la_LTLIBRARIES = theatre200_drv.la
theatre200_drv_la_LDFLAGS = -module -avoid-version
theatre200_drv_ladir = @moduledir@/multimedia
theatre200_drv_la_CFLAGS = \
$(AM_CFLAGS) -DMICROC_DIR=\"$(theatre200_drv_ladir)\"
theatre200_drv_la_SOURCES = \
theatre200.c theatre200_module.c
EXTRA_DIST = \
radeon_render.c \
radeon_accelfuncs.c \
radeon_textured_videofuncs.c \
r600_reg.h \
r600_reg_auto_r6xx.h \
@ -141,11 +83,8 @@ EXTRA_DIST = \
ati.h \
ativersion.h \
bicubic_table.h \
generic_bus.h \
radeon_commonfuncs.c \
radeon_dri.h \
radeon_drm.h \
radeon_dummy_bufmgr.h \
radeon_exa_render.c \
radeon_exa_funcs.c \
radeon_exa_shared.h \
@ -156,13 +95,7 @@ EXTRA_DIST = \
radeon_version.h \
radeon_vbo.h \
radeon_video.h \
radeon_tv.h \
radeon_atomwrapper.h \
simple_list.h \
theatre200.h \
theatre_detect.h \
theatre.h \
theatre_reg.h \
atipciids.h \
atipcirename.h \
ati_pciids_gen.h \
@ -172,6 +105,5 @@ EXTRA_DIST = \
radeon_pci_device_match_gen.h \
pcidb/ati_pciids.csv \
pcidb/parse_pci_ids.pl \
radeon_atombios.h \
radeon_dri2.h \
drmmode_display.h

1541
src/atombios_crtc.c
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File diff suppressed because it is too large Load diff

2775
src/atombios_output.c
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File diff suppressed because it is too large Load diff

3
src/cayman_accel.c
View file

@ -27,8 +27,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include <errno.h>
@ -304,4 +302,3 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
END_BATCH();
}
#endif

4
src/cayman_shader.c
View file

@ -28,8 +28,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include "cayman_shader.h"
@ -3131,5 +3129,3 @@ int cayman_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
return i;
}
#endif

6
src/drmmode_display.c
View file

@ -30,7 +30,6 @@
#endif
#include <errno.h>
#ifdef XF86DRM_MODE
#include <sys/ioctl.h>
#include "micmap.h"
#include "xf86cmap.h"
@ -636,7 +635,7 @@ void drmmode_crtc_hw_id(xf86CrtcPtr crtc)
ginfo.request = 0x4;
tmp = drmmode_crtc->mode_crtc->crtc_id;
ginfo.value = (uintptr_t)&tmp;
r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
if (r) {
drmmode_crtc->hw_id = -1;
return;
@ -1528,7 +1527,7 @@ void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
RADEONInfoPtr info = RADEONPTR(pScrn);
if (pRADEONEnt->fd_wakeup_registered != serverGeneration &&
info->dri->pKernelDRMVersion->version_minor >= 4) {
info->dri2.pKernelDRMVersion->version_minor >= 4) {
AddGeneralSocket(drmmode->fd);
RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA,
drm_wakeup_handler, drmmode);
@ -1868,4 +1867,3 @@ error_out:
return FALSE;
}
#endif

3
src/drmmode_display.h
View file

@ -27,8 +27,6 @@
#ifndef DRMMODE_DISPLAY_H
#define DRMMODE_DISPLAY_H
#ifdef XF86DRM_MODE
#include "xf86drmMode.h"
#ifdef HAVE_LIBUDEV
#include "libudev.h"
@ -119,4 +117,3 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct radeon_bo *new_front, void *dat
#endif
#endif

31
src/evergreen_accel.c
View file

@ -27,8 +27,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include <errno.h>
@ -209,7 +207,6 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
uint32_t tile_split, macro_aspect, bankw, bankh;
RADEONInfoPtr info = RADEONPTR(pScrn);
#if defined(XF86DRM_MODE)
if (cb_conf->surface) {
switch (cb_conf->surface->level[0].mode) {
case RADEON_SURF_MODE_1D:
@ -234,9 +231,7 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
} else
#endif
{
} else {
pitch = (cb_conf->w / 8) - 1;
h = RADEON_ALIGN(cb_conf->h, 8);
slice = ((cb_conf->w * h) / 64) - 1;
@ -371,7 +366,6 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
drmmode_crtc_private_ptr drmmode_crtc;
uint32_t offset;
if (!crtc)
return;
@ -381,21 +375,8 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix,
if (!crtc->enabled)
return;
if (info->cs) {
if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
return;
} else {
#ifdef USE_EXA
if (info->useEXA)
offset = exaGetPixmapOffset(pPix);
else
#endif
offset = pPix->devPrivate.ptr - info->FB;
/* if drawing to front buffer */
if (offset != 0)
return;
}
if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
return;
start = max(start, crtc->y);
stop = min(stop, crtc->y + crtc->mode.VDisplay);
@ -698,7 +679,6 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t
uint32_t sq_tex_resource_word5, sq_tex_resource_word6, sq_tex_resource_word7;
uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks;
#if defined(XF86DRM_MODE)
if (tex_res->surface) {
switch (tex_res->surface->level[0].mode) {
case RADEON_SURF_MODE_1D:
@ -720,9 +700,7 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
} else
#endif
{
} else {
array_mode = tex_res->array_mode;
pitch = (tex_res->pitch + 7) >> 3;
tile_split = 4;
@ -1503,4 +1481,3 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
}
#endif

10
src/evergreen_exa.c
View file

@ -28,8 +28,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include "exa.h"
@ -1769,8 +1767,6 @@ EVERGREENAllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen)
/* 512 bytes per shader for now */
int size = 512 * 9;
accel_state->shaders = NULL;
accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
RADEON_GEM_DOMAIN_VRAM, 0);
if (accel_state->shaders_bo == NULL) {
@ -1897,10 +1893,6 @@ EVERGREENDrawInit(ScreenPtr pScreen)
return FALSE;
}
/* accel requires kms */
if (!info->cs)
return FALSE;
info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
@ -1998,5 +1990,3 @@ EVERGREENDrawInit(ScreenPtr pScreen)
return TRUE;
}
#endif

4
src/evergreen_shader.c
View file

@ -28,8 +28,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include "evergreen_shader.h"
@ -3130,5 +3128,3 @@ int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
return i;
}
#endif

4
src/evergreen_state.h
View file

@ -93,9 +93,7 @@ typedef struct {
int blend_enable;
uint32_t blendcntl;
struct radeon_bo *bo;
#ifdef XF86DRM_MODE
struct radeon_surface *surface;
#endif
} cb_config_t;
/* Shader */
@ -182,9 +180,7 @@ typedef struct {
int min_lod;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
#ifdef XF86DRM_MODE
struct radeon_surface *surface;
#endif
} tex_resource_t;
/* Texture sampler */

4
src/evergreen_textured_videofuncs.c
View file

@ -28,8 +28,6 @@
#include "config.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86.h"
#include "exa.h"
@ -527,5 +525,3 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
#endif

36
src/generic_bus.h
View file

@ -1,36 +0,0 @@
#ifndef __GENERIC_BUS_H__
#define __GENERIC_BUS_H__
/* this is meant to be used for proprietary buses where abstraction is needed
but they don't occur often enough to warrant a separate helper library */
#include <stdint.h>
#define GB_IOCTL_GET_NAME 1
/* third argument is size of the buffer, fourth argument is pointer
to the buffer. Returns the name of the bus */
#define GB_IOCTL_GET_TYPE 2
/* third argument is size of the buffer, fourth argument is pointer
to the buffer. Returns the type of the bus, driver should check
this at initialization time to find out whether they are compatible
*/
typedef struct _GENERIC_BUS_Rec *GENERIC_BUS_Ptr;
typedef struct _GENERIC_BUS_Rec{
ScrnInfoPtr pScrn;
DevUnion DriverPrivate;
Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *);
Bool (*read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *);
Bool (*write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *);
Bool (*fifo_read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *);
Bool (*fifo_write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *);
} GENERIC_BUS_Rec;
#endif

1898
src/legacy_crtc.c
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File diff suppressed because it is too large Load diff

2102
src/legacy_output.c
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File diff suppressed because it is too large Load diff

680
src/r600_exa.c
View file

File diff suppressed because it is too large Load diff

136
src/r600_state.h
View file

@ -56,9 +56,7 @@ typedef struct {
int blend_enable;
uint32_t blendcntl;
struct radeon_bo *bo;
#ifdef XF86DRM_MODE
struct radeon_surface *surface;
#endif
} cb_config_t;
/* Depth buffer */
@ -145,9 +143,7 @@ typedef struct {
int interlaced;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
#ifdef XF86DRM_MODE
struct radeon_surface *surface;
#endif
} tex_resource_t;
/* Texture sampler */
@ -189,144 +185,122 @@ typedef struct {
uint32_t num_indices;
} draw_config_t;
#if defined(XF86DRM_MODE)
#define BEGIN_BATCH(n) \
do { \
if (info->cs) \
radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
} while(0)
#define END_BATCH() \
do { \
if (info->cs) \
radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
} while(0)
#define RELOC_BATCH(bo, rd, wd) \
do { \
if (info->cs) { \
int _ret; \
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
} \
int _ret; \
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
} while(0)
#define E32(ib, dword) \
#define E32(dword) \
do { \
if (info->cs) \
radeon_cs_write_dword(info->cs, (dword)); \
else { \
uint32_t *ib_head = (pointer)(char*)(ib)->address; \
ib_head[(ib)->used >> 2] = (dword); \
(ib)->used += 4; \
} \
radeon_cs_write_dword(info->cs, (dword)); \
} while (0)
#else
#define BEGIN_BATCH(n) do {(void)info;} while(0)
#define END_BATCH() do {} while(0)
#define RELOC_BATCH(bo, wd, rd) do {} while(0)
#define E32(ib, dword) \
do { \
uint32_t *ib_head = (pointer)(char*)(ib)->address; \
ib_head[(ib)->used >> 2] = (dword); \
(ib)->used += 4; \
} while (0)
#endif
#define EFLOAT(ib, val) \
#define EFLOAT(val) \
do { \
union { float f; uint32_t d; } a; \
a.f = (val); \
E32((ib), a.d); \
E32(a.d); \
} while (0)
#define PACK3(ib, cmd, num) \
#define PACK3(cmd, num) \
do { \
E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
} while (0)
/* write num registers, start at reg */
/* If register falls in a special area, special commands are issued */
#define PACK0(ib, reg, num) \
#define PACK0(reg, num) \
do { \
if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
PACK3((ib), IT_SET_CONFIG_REG, (num) + 1); \
E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2); \
PACK3(IT_SET_CONFIG_REG, (num) + 1); \
E32(((reg) - SET_CONFIG_REG_offset) >> 2); \
} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1); \
E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2); \
PACK3(IT_SET_CONTEXT_REG, (num) + 1); \
E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \
} else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
PACK3((ib), IT_SET_ALU_CONST, (num) + 1); \
E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2); \
PACK3(IT_SET_ALU_CONST, (num) + 1); \
E32(((reg) - SET_ALU_CONST_offset) >> 2); \
} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
PACK3((ib), IT_SET_RESOURCE, num + 1); \
E32((ib), ((reg) - SET_RESOURCE_offset) >> 2); \
PACK3(IT_SET_RESOURCE, num + 1); \
E32(((reg) - SET_RESOURCE_offset) >> 2); \
} else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
PACK3((ib), IT_SET_SAMPLER, (num) + 1); \
E32((ib), (reg - SET_SAMPLER_offset) >> 2); \
PACK3(IT_SET_SAMPLER, (num) + 1); \
E32((reg - SET_SAMPLER_offset) >> 2); \
} else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
PACK3((ib), IT_SET_CTL_CONST, (num) + 1); \
E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2); \
PACK3(IT_SET_CTL_CONST, (num) + 1); \
E32(((reg) - SET_CTL_CONST_offset) >> 2); \
} else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
PACK3((ib), IT_SET_LOOP_CONST, (num) + 1); \
E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2); \
PACK3(IT_SET_LOOP_CONST, (num) + 1); \
E32(((reg) - SET_LOOP_CONST_offset) >> 2); \
} else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
PACK3((ib), IT_SET_BOOL_CONST, (num) + 1); \
E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2); \
PACK3(IT_SET_BOOL_CONST, (num) + 1); \
E32(((reg) - SET_BOOL_CONST_offset) >> 2); \
} else { \
E32((ib), CP_PACKET0 ((reg), (num) - 1)); \
E32(CP_PACKET0 ((reg), (num) - 1)); \
} \
} while (0)
/* write a single register */
#define EREG(ib, reg, val) \
#define EREG(reg, val) \
do { \
PACK0((ib), (reg), 1); \
E32((ib), (val)); \
PACK0((reg), 1); \
E32((val)); \
} while (0)
void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
void R600CPFlushIndirect(ScrnInfoPtr pScrn);
void R600IBDiscard(ScrnInfoPtr pScrn);
void
r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_wait_3d_idle_clean(ScrnInfoPtr pScrn);
void
r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_wait_3d_idle(ScrnInfoPtr pScrn);
void
r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_start_3d(ScrnInfoPtr pScrn);
void
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
void
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp);
r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
void
r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
void
r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
void
r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
void
r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf);
void
r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
void
r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
void
r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s);
void
r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
void
r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
void
r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
void
r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
r600_set_default_state(ScrnInfoPtr pScrn);
void
r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices);
void
r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);

68
src/r600_textured_videofuncs.c
View file

@ -164,20 +164,12 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (vs_conf);
CLEAR (ps_conf);
#if defined(XF86DRM_MODE)
if (info->cs) {
dst_obj.offset = 0;
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
} else
#endif
{
dst_obj.offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset;
src_obj.offset = pPriv->src_offset + info->fbLocation + pScrn->fbOffset;
dst_obj.bo = src_obj.bo = NULL;
}
dst_obj.offset = 0;
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
src_obj.pitch = pPriv->src_pitch;
@ -187,9 +179,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
src_obj.tiling_flags = 0;
#ifdef XF86DRM_MODE
src_obj.surface = NULL;
#endif
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
@ -215,22 +205,22 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
r600_set_default_state(pScrn, accel_state->ib);
r600_set_default_state(pScrn);
r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* PS bool constant */
switch(pPriv->id) {
case FOURCC_YV12:
case FOURCC_I420:
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0));
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0));
break;
}
@ -240,7 +230,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.shader_size = accel_state->ps_size;
@ -250,10 +240,10 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
/* PS alu constants */
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
/* Texture */
@ -274,9 +264,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
#ifdef XF86DRM_MODE
tex_res.surface = NULL;
#endif
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
@ -291,7 +279,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.interlaced = 0;
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
tex_samp.id = 0;
@ -305,7 +293,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, &tex_samp);
/* U or V texture */
tex_res.id = 1;
@ -324,11 +312,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
tex_samp.id = 1;
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, &tex_samp);
/* U or V texture */
tex_res.id = 2;
@ -347,11 +335,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
tex_samp.id = 2;
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, &tex_samp);
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
@ -387,7 +375,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.interlaced = 0;
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* YUV sampler */
tex_samp.id = 0;
@ -401,7 +389,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
r600_set_tex_sampler(pScrn, &tex_samp);
break;
}
@ -411,9 +399,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
#ifdef XF86DRM_MODE
cb_conf.surface = accel_state->dst_obj.surface;
#endif
switch (accel_state->dst_obj.bpp) {
case 16:
@ -445,9 +431,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.rop = 3;
if (accel_state->dst_obj.tiling_flags == 0)
cb_conf.array_mode = 1;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
r600_set_spi(pScrn, (1 - 1), 1);
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
@ -455,7 +441,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_alu_consts[3] = 0.0;
/* VS alu constants */
r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs,
r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs,
sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
if (pPriv->vsync) {
@ -469,7 +455,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
r600_cp_wait_vline_sync(pScrn, pPixmap,
crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);

690
src/r6xx_accel.c
View file

File diff suppressed because it is too large Load diff

939
src/radeon.h
View file

File diff suppressed because it is too large Load diff

1242
src/radeon_accel.c
View file

File diff suppressed because it is too large Load diff

1385
src/radeon_accelfuncs.c
View file

File diff suppressed because it is too large Load diff

3022
src/radeon_atombios.c
View file

File diff suppressed because it is too large Load diff

293
src/radeon_atombios.h
View file

@ -1,293 +0,0 @@
/*
* Copyright 2007 Egbert Eich <eich@novell.com>
* Copyright 2007 Luc Verhaegen <lverhaegen@novell.com>
* Copyright 2007 Matthias Hopf <mhopf@novell.com>
* Copyright 2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RHD_ATOMBIOS_H_
# define RHD_ATOMBIOS_H_
//#include "radeon.h"
# ifdef ATOM_BIOS
typedef enum _AtomBiosRequestID {
ATOMBIOS_INIT,
ATOMBIOS_TEARDOWN,
# ifdef ATOM_BIOS_PARSER
ATOMBIOS_EXEC,
#endif
ATOMBIOS_ALLOCATE_FB_SCRATCH,
ATOMBIOS_GET_CONNECTORS,
ATOMBIOS_GET_PANEL_MODE,
ATOMBIOS_GET_PANEL_EDID,
GET_DEFAULT_ENGINE_CLOCK,
GET_DEFAULT_MEMORY_CLOCK,
GET_MAX_PIXEL_CLOCK_PLL_OUTPUT,
GET_MIN_PIXEL_CLOCK_PLL_OUTPUT,
GET_MAX_PIXEL_CLOCK_PLL_INPUT,
GET_MIN_PIXEL_CLOCK_PLL_INPUT,
GET_MAX_PIXEL_CLK,
GET_REF_CLOCK,
GET_FW_FB_START,
GET_FW_FB_SIZE,
ATOM_TMDS_FREQUENCY,
ATOM_TMDS_PLL_CHARGE_PUMP,
ATOM_TMDS_PLL_DUTY_CYCLE,
ATOM_TMDS_PLL_VCO_GAIN,
ATOM_TMDS_PLL_VOLTAGE_SWING,
ATOM_LVDS_SUPPORTED_REFRESH_RATE,
ATOM_LVDS_OFF_DELAY,
ATOM_LVDS_SEQ_DIG_ONTO_DE,
ATOM_LVDS_SEQ_DE_TO_BL,
ATOM_LVDS_DITHER,
ATOM_LVDS_DUALLINK,
ATOM_LVDS_24BIT,
ATOM_LVDS_GREYLVL,
ATOM_LVDS_FPDI,
ATOM_GPIO_QUERIES,
ATOM_GPIO_I2C_CLK_MASK,
ATOM_DAC1_BG_ADJ,
ATOM_DAC1_DAC_ADJ,
ATOM_DAC1_FORCE,
ATOM_DAC2_CRTC2_BG_ADJ,
ATOM_DAC2_CRTC2_DAC_ADJ,
ATOM_DAC2_CRTC2_FORCE,
ATOM_DAC2_CRTC2_MUX_REG_IND,
ATOM_DAC2_CRTC2_MUX_REG_INFO,
ATOMBIOS_GET_CV_MODES,
FUNC_END
} AtomBiosRequestID;
typedef enum _AtomBiosResult {
ATOM_SUCCESS,
ATOM_FAILED,
ATOM_NOT_IMPLEMENTED
} AtomBiosResult;
typedef struct AtomExec {
int index;
pointer pspace;
pointer *dataSpace;
} AtomExecRec, *AtomExecPtr;
typedef struct AtomFb {
unsigned int start;
unsigned int size;
} AtomFbRec, *AtomFbPtr;
typedef union AtomBiosArg
{
uint32_t val;
struct rhdConnectorInfo *connectorInfo;
unsigned char* EDIDBlock;
atomBiosHandlePtr atomhandle;
DisplayModePtr modes;
AtomExecRec exec;
AtomFbRec fb;
ScrnInfoPtr pScrn;
} AtomBiosArgRec, *AtomBiosArgPtr;
extern AtomBiosResult
RHDAtomBiosFunc(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
AtomBiosRequestID id, AtomBiosArgPtr data);
extern Bool
RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn);
extern Bool
RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn);
extern int
atombios_clk_gating_setup(ScrnInfoPtr pScrn, Bool enable);
extern int
atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, Bool enable);
extern int
atombios_set_engine_clock(ScrnInfoPtr pScrn, uint32_t engclock);
extern int
atombios_set_memory_clock(ScrnInfoPtr pScrn, uint32_t memclock);
extern Bool
RADEONGetATOMTVInfo(xf86OutputPtr output);
extern int
atombios_external_tmds_setup(xf86OutputPtr output, int action);
extern void
atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor);
extern xf86MonPtr
radeon_atom_get_edid(xf86OutputPtr output);
Bool
rhdAtomASICInit(atomBiosHandlePtr handle);
# include "xf86int10.h"
# ifdef ATOM_BIOS_PARSER
# define INT8 INT8
# define INT16 INT16
# define INT32 INT32
# include "CD_Common_Types.h"
# else
# ifndef ULONG
typedef unsigned int ULONG;
# define ULONG ULONG
# endif
# ifndef UCHAR
typedef unsigned char UCHAR;
# define UCHAR UCHAR
# endif
# ifndef USHORT
typedef unsigned short USHORT;
# define USHORT USHORT
# endif
# endif
# include "atombios.h"
# include "ObjectID.h"
/*
* This works around a bug in atombios.h where
* ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly.
*/
#define ATOM_MAX_SUPPORTED_DEVICE_INFO_HD (ATOM_DEVICE_RESERVEDF_INDEX+1)
typedef struct _ATOM_SUPPORTED_DEVICES_INFO_HD
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usDeviceSupport;
ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
} ATOM_SUPPORTED_DEVICES_INFO_HD;
typedef struct _atomDataTables
{
unsigned char *UtilityPipeLine;
ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo;
ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo;
ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing;
union {
void *base;
ATOM_FIRMWARE_INFO *FirmwareInfo;
ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2;
ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3;
ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4;
ATOM_FIRMWARE_INFO_V2_1 *FirmwareInfo_V_2_1;
} FirmwareInfo;
ATOM_DAC_INFO *DAC_Info;
union {
void *base;
ATOM_LVDS_INFO *LVDS_Info;
ATOM_LVDS_INFO_V12 *LVDS_Info_v12;
} LVDS_Info;
ATOM_TMDS_INFO *TMDS_Info;
union {
void *base;
ATOM_ANALOG_TV_INFO *AnalogTV_Info;
ATOM_ANALOG_TV_INFO_V1_2 *AnalogTV_Info_v1_2;
} AnalogTV_Info;
union {
void *base;
ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo;
ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2;
ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1;
ATOM_SUPPORTED_DEVICES_INFO_HD *SupportedDevicesInfo_HD;
} SupportedDevicesInfo;
ATOM_GPIO_I2C_INFO *GPIO_I2C_Info;
ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware;
ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT;
ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT;
union {
void *base;
ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo;
ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21;
} ComponentVideoInfo;
/**/unsigned char *PowerPlayInfo;
COMPASSIONATE_DATA *CompassionateData;
ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo;
/**/unsigned char *PPLL_SS_Info;
ATOM_OEM_INFO *OemInfo;
ATOM_XTMDS_INFO *XTMDS_Info;
ATOM_ASIC_MVDD_INFO *MclkSS_Info;
ATOM_OBJECT_HEADER *Object_Header;
INDIRECT_IO_ACCESS *IndirectIOAccess;
ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter;
/**/unsigned char *ASIC_VDDC_Info;
ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info;
/**/unsigned char *TV_VideoMode;
union {
void *base;
ATOM_VRAM_INFO_V2 *VRAM_Info_v2;
ATOM_VRAM_INFO_V3 *VRAM_Info_v3;
} VRAM_Info;
ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo;
union {
void *base;
ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo;
ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2;
} IntegratedSystemInfo;
ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo;
ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo;
ATOM_POWER_SOURCE_INFO *PowerSourceInfo;
} atomDataTables, *atomDataTablesPtr;
typedef struct _atomBiosHandle {
ScrnInfoPtr pScrn;
unsigned char *BIOSBase;
atomDataTablesPtr atomDataPtr;
unsigned int cmd_offset;
pointer *scratchBase;
uint32_t fbBase;
#if XSERVER_LIBPCIACCESS
struct pci_device *device;
#else
PCITAG PciTag;
#endif
unsigned int BIOSImageSize;
} atomBiosHandleRec;
# endif
extern Bool
RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, DisplayModePtr mode);
extern void
RADEONATOMGetIGPInfo(ScrnInfoPtr pScrn);
extern Bool
RADEONGetATOMClockInfo(ScrnInfoPtr pScrn);
extern uint32_t
radeon_get_device_index(uint32_t device_support);
extern radeon_encoder_ptr
radeon_get_encoder(xf86OutputPtr output);
extern Bool
radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_support);
extern uint32_t
radeon_get_encoder_id_from_supported_device(ScrnInfoPtr pScrn, uint32_t supported_device, int dac);
void atombios_set_output_crtc_source(xf86OutputPtr output);
#endif /* RHD_ATOMBIOS_H_ */

102
src/radeon_atomwrapper.c
View file

@ -1,102 +0,0 @@
/*
* Copyright 2007 Luc Verhaegen <lverhaegen@novell.com>
* Copyright 2007 Matthias Hopf <mhopf@novell.com>
* Copyright 2007 Egbert Eich <eich@novell.com>
* Copyright 2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include "radeon_atomwrapper.h"
#define INT32 INT32
#include "CD_Common_Types.h"
#include "atombios.h"
#include "CD_Definitions.h"
int
ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase,
char **msg_return)
{
DEVICE_DATA deviceData;
int ret = 0;
/* FILL OUT PARAMETER SPACE */
deviceData.pParameterSpace = (UINT32*) pspace;
deviceData.CAIL = handle;
deviceData.pBIOS_Image = BIOSBase;
deviceData.format = TABLE_FORMAT_BIOS;
switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */
case CD_SUCCESS:
ret = 1;
*msg_return = "ParseTable said: CD_SUCCESS";
break;
case CD_CALL_TABLE:
ret = 1;
*msg_return = "ParseTable said: CD_CALL_TABLE";
break;
case CD_COMPLETED:
ret = 1;
*msg_return = "ParseTable said: CD_COMPLETED";
break;
case CD_GENERAL_ERROR:
ret = 0;
*msg_return = " ParseTable said: CD_GENERAL_ERROR";
break;
case CD_INVALID_OPCODE:
ret = 0;
*msg_return = " ParseTable said: CD_INVALID_OPCODE";
break;
case CD_NOT_IMPLEMENTED:
ret = 0;
*msg_return = " ParseTable said: CD_NOT_IMPLEMENTED";
break;
case CD_EXEC_TABLE_NOT_FOUND:
ret = 0;
*msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND";
break;
case CD_EXEC_PARAMETER_ERROR:
ret = 0;
*msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR";
break;
case CD_EXEC_PARSER_ERROR:
ret = 0;
*msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR";
break;
case CD_INVALID_DESTINATION_TYPE:
ret = 0;
*msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE";
break;
case CD_UNEXPECTED_BEHAVIOR:
ret = 0;
*msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR";
break;
case CD_INVALID_SWITCH_OPERAND_SIZE:
ret = 0;
*msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n";
break;
}
return ret;
}

31
src/radeon_atomwrapper.h
View file

@ -1,31 +0,0 @@
/*
* Copyright 2007 Luc Verhaegen <lverhaegen@novell.com>
* Copyright 2007 Matthias Hopf <mhopf@novell.com>
* Copyright 2007 Egbert Eich <eich@novell.com>
* Copyright 2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RHD_ATOMWRAPPER_H_
# define RHD_ATOMWRAPPER_H_
extern int ParseTableWrapper(void *pspace, int index, void *CAIL,
void *BIOSBase, char **msg_return);
#endif /* RHD_ATOMWRAPPER_H_ */

2052
src/radeon_bios.c
View file

File diff suppressed because it is too large Load diff

265
src/radeon_commonfuncs.c
View file

@ -32,31 +32,18 @@
#include "ati_pciids_gen.h"
#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
#error Cannot define both MMIO and CP acceleration!
#endif
#if !defined(UNIXCPP) || defined(ANSICPP)
#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
#else
#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
#endif
#ifdef ACCEL_MMIO
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
#else
#ifdef ACCEL_CP
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
#else
#error No accel type defined!
#endif
#endif
static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t gb_tile_config, su_reg_dest, vap_cntl;
int size;
uint32_t gb_tile_config, vap_cntl;
ACCEL_PREAMBLE();
info->accel_state->texW[0] = info->accel_state->texH[0] =
@ -64,14 +51,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
if (IS_R300_3D || IS_R500_3D) {
if (!info->cs) {
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
}
gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch(info->accel_state->num_gb_pipes) {
@ -82,28 +61,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
}
if (!info->cs) {
size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4;
BEGIN_ACCEL(size);
OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
if (info->ChipFamily >= CHIP_FAMILY_R420)
OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
OUT_ACCEL_REG(R300_GB_SELECT, 0);
OUT_ACCEL_REG(R300_GB_ENABLE, 0);
FINISH_ACCEL();
}
if (IS_R500_3D) {
if (!info->cs) {
su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1);
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
FINISH_ACCEL();
}
}
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
@ -116,27 +73,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
FINISH_ACCEL();
if (!info->cs) {
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) |
(6 << R300_MS_Y0_SHIFT) |
(6 << R300_MS_X1_SHIFT) |
(6 << R300_MS_Y1_SHIFT) |
(6 << R300_MS_X2_SHIFT) |
(6 << R300_MS_Y2_SHIFT) |
(6 << R300_MSBD0_Y_SHIFT) |
(6 << R300_MSBD0_X_SHIFT)));
OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) |
(6 << R300_MS_Y3_SHIFT) |
(6 << R300_MS_X4_SHIFT) |
(6 << R300_MS_Y4_SHIFT) |
(6 << R300_MS_X5_SHIFT) |
(6 << R300_MS_Y5_SHIFT) |
(6 << R300_MSBD1_SHIFT)));
OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
FINISH_ACCEL();
}
BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
@ -833,7 +769,7 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
xf86CrtcPtr crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t offset;
drmmode_crtc_private_ptr drmmode_crtc;
ACCEL_PREAMBLE();
if (!crtc)
@ -842,21 +778,8 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
if (!crtc->enabled)
return;
if (info->cs) {
if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
return;
} else {
#ifdef USE_EXA
if (info->useEXA)
offset = exaGetPixmapOffset(pPix);
else
#endif
offset = pPix->devPrivate.ptr - info->FB;
/* if drawing to front buffer */
if (offset != 0)
return;
}
if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
return;
start = max(start, crtc->y);
stop = min(stop, crtc->y + crtc->mode.VDisplay);
@ -870,168 +793,26 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
stop -= crtc->y;
}
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs) {
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
drmmode_crtc = crtc->driver_private;
BEGIN_ACCEL(3);
if (IS_AVIVO_VARIANT) {
OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
(stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
AVIVO_D1MODE_VLINE_INV));
} else {
OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
RADEON_CRTC_GUI_TRIG_VLINE_INV |
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
}
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
RADEON_ENG_DISPLAY_SELECT_CRTC0));
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
FINISH_ACCEL();
} else
#endif
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
BEGIN_ACCEL(2);
if (IS_AVIVO_VARIANT) {
OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
(stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
AVIVO_D1MODE_VLINE_INV));
} else {
if (radeon_crtc->crtc_id == 0)
OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
RADEON_CRTC_GUI_TRIG_VLINE_INV |
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
else
OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
RADEON_CRTC_GUI_TRIG_VLINE_INV |
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
}
if (radeon_crtc->crtc_id == 0)
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
RADEON_ENG_DISPLAY_SELECT_CRTC0));
else
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
RADEON_ENG_DISPLAY_SELECT_CRTC1));
FINISH_ACCEL();
}
}
/* MMIO:
*
* Wait for the graphics engine to be completely idle: the FIFO has
* drained, the Pixel Cache is flushed, and the engine is idle. This is
* a standard "sync" function that will make the hardware "quiescent".
*
* CP:
*
* Wait until the CP is completely idle: the FIFO has drained and the CP
* is idle.
*/
void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int i = 0;
#ifdef ACCEL_CP
/* Make sure the CP is idle first */
if (info->cp->CPStarted) {
int ret;
FLUSH_RING();
for (;;) {
do {
ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE);
if (ret && ret != -EBUSY) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP idle %d\n", __FUNCTION__, ret);
}
} while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT));
if (ret == 0) return;
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
if (info->ChipFamily < CHIP_FAMILY_R600) {
RADEONEngineReset(pScrn);
RADEONEngineRestore(pScrn);
} else
R600EngineReset(pScrn);
/* Always restart the engine when doing CP 2D acceleration */
RADEONCP_RESET(pScrn, info);
RADEONCP_START(pScrn, info);
}
}
#endif
if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (!info->accelOn)
return;
/* Wait for the engine to go idle */
if (info->ChipFamily >= CHIP_FAMILY_RV770)
R600WaitForFifoFunction(pScrn, 8);
else
R600WaitForFifoFunction(pScrn, 16);
for (;;) {
for (i = 0; i < RADEON_TIMEOUT; i++) {
if (!(INREG(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
return;
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Idle timed out: stat=0x%08x\n",
(unsigned int)INREG(R600_GRBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
R600EngineReset(pScrn);
#ifdef XF86DRI
if (info->directRenderingEnabled) {
RADEONCP_RESET(pScrn, info);
RADEONCP_START(pScrn, info);
}
#endif
}
BEGIN_ACCEL(3);
if (IS_AVIVO_VARIANT) {
OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
(stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
AVIVO_D1MODE_VLINE_INV));
} else {
/* Wait for the engine to go idle */
RADEONWaitForFifoFunction(pScrn, 64);
for (;;) {
for (i = 0; i < RADEON_TIMEOUT; i++) {
if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) {
RADEONEngineFlush(pScrn);
return;
}
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Idle timed out: %u entries, stat=0x%08x\n",
(unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
(unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
RADEONEngineRestore(pScrn);
#ifdef XF86DRI
if (info->directRenderingEnabled) {
RADEONCP_RESET(pScrn, info);
RADEONCP_START(pScrn, info);
}
#endif
}
OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
RADEON_CRTC_GUI_TRIG_VLINE_INV |
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
}
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
RADEON_ENG_DISPLAY_SELECT_CRTC0));
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
FINISH_ACCEL();
}

1128
src/radeon_crtc.c
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File diff suppressed because it is too large Load diff

449
src/radeon_cursor.c
View file

@ -1,449 +0,0 @@
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#define RADEONCTRACE(x)
/*#define RADEONCTRACE(x) RADEONTRACE(x) */
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
*
* References:
*
* !!!! FIXME !!!!
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
/* Driver data structures */
#include "radeon.h"
#include "radeon_version.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
/* X and server generic header files */
#include "xf86.h"
#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64
/*
* The cursor bits are always 32bpp. On MSBFirst buses,
* configure byte swapping to swap 32 bit units when writing
* the cursor image. Byte swapping must always be returned
* to its previous value before returning.
*/
#if X_BYTE_ORDER == X_BIG_ENDIAN
#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO;
#define CURSOR_SWAPPING_START() \
do { \
if (info->ChipFamily < CHIP_FAMILY_R600) \
OUTREG(RADEON_SURFACE_CNTL, \
(info->ModeReg->surface_cntl | \
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
} while (0)
#define CURSOR_SWAPPING_END() \
do { \
if (info->ChipFamily < CHIP_FAMILY_R600) \
OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \
} while (0)
#else
#define CURSOR_SWAPPING_DECL_MMIO
#define CURSOR_SWAPPING_START()
#define CURSOR_SWAPPING_END()
#endif
static void
avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
/* always use the same cursor mode even if the cursor is disabled,
* otherwise you may end up with cursor curruption bands
*/
OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
if (enable) {
uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset;
if (info->ChipFamily >= CHIP_FAMILY_RV770) {
if (radeon_crtc->crtc_id)
OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf);
else
OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf);
}
OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset);
OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
}
}
static void
avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t tmp;
tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
if (lock)
tmp |= AVIVO_D1CURSOR_UPDATE_LOCK;
else
tmp &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
}
static void
evergreen_setup_cursor(xf86CrtcPtr crtc, Bool enable)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
/* always use the same cursor mode even if the cursor is disabled,
* otherwise you may end up with cursor curruption bands
*/
OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
if (enable) {
uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset;
OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
(location >> 32) & 0xf);
OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
location & EVERGREEN_CUR_SURFACE_ADDRESS_MASK);
OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
EVERGREEN_CURSOR_EN | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
}
}
static void
evergreen_lock_cursor(xf86CrtcPtr crtc, Bool lock)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t tmp;
tmp = INREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
if (lock)
tmp |= EVERGREEN_CURSOR_UPDATE_LOCK;
else
tmp &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
OUTREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
}
void
radeon_crtc_show_cursor (xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
int crtc_id = radeon_crtc->crtc_id;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
if (IS_DCE4_VARIANT) {
evergreen_lock_cursor(crtc, TRUE);
evergreen_setup_cursor(crtc, TRUE);
evergreen_lock_cursor(crtc, FALSE);
} else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
avivo_setup_cursor(crtc, TRUE);
avivo_lock_cursor(crtc, FALSE);
} else {
switch (crtc_id) {
case 0:
OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
break;
case 1:
OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
break;
default:
return;
}
OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
}
void
radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
int crtc_id = radeon_crtc->crtc_id;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
if (IS_DCE4_VARIANT) {
evergreen_lock_cursor(crtc, TRUE);
evergreen_setup_cursor(crtc, FALSE);
evergreen_lock_cursor(crtc, FALSE);
} else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
avivo_setup_cursor(crtc, FALSE);
avivo_lock_cursor(crtc, FALSE);
} else {
switch(crtc_id) {
case 0:
OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
break;
case 1:
OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
break;
default:
return;
}
OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
}
}
void
radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
int crtc_id = radeon_crtc->crtc_id;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int xorigin = 0, yorigin = 0;
int stride = 256;
DisplayModePtr mode = &crtc->mode;
int w = CURSOR_WIDTH;
if (x < 0) xorigin = -x+1;
if (y < 0) yorigin = -y+1;
if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1;
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
if (IS_AVIVO_VARIANT) {
/* avivo cursor spans the full fb width */
if (crtc->rotatedData == NULL) {
x += crtc->x;
y += crtc->y;
}
if (pRADEONEnt->Controller[0]->enabled &&
pRADEONEnt->Controller[1]->enabled) {
int cursor_end, frame_end;
cursor_end = x - xorigin + w;
frame_end = crtc->x + mode->CrtcHDisplay;
if (cursor_end >= frame_end) {
w = w - (cursor_end - frame_end);
if (!(frame_end & 0x7f))
w--;
} else {
if (!(cursor_end & 0x7f))
w--;
}
if (w <= 0)
w = 1;
}
}
if (IS_DCE4_VARIANT) {
evergreen_lock_cursor(crtc, TRUE);
OUTREG(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y));
OUTREG(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
OUTREG(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
((w - 1) << 16) | (CURSOR_HEIGHT - 1));
evergreen_lock_cursor(crtc, FALSE);
} else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y));
OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((w - 1) << 16) | (CURSOR_HEIGHT - 1));
avivo_lock_cursor(crtc, FALSE);
} else {
if (mode->Flags & V_DBLSCAN)
y *= 2;
if (crtc_id == 0) {
OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
| (xorigin << 16)
| yorigin));
OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
| ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y)));
RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
OUTREG(RADEON_CUR_OFFSET,
radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
} else if (crtc_id == 1) {
OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
| (xorigin << 16)
| yorigin));
OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
| ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y)));
RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
OUTREG(RADEON_CUR2_OFFSET,
radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
}
}
}
void
radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t *pixels = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset);
int pixel, i;
CURSOR_SWAPPING_DECL_MMIO
RADEONCTRACE(("RADEONSetCursorColors\n"));
#ifdef ARGB_CURSOR
/* Don't recolour cursors set with SetCursorARGB. */
if (info->cursor_argb)
return;
#endif
fg |= 0xff000000;
bg |= 0xff000000;
/* Don't recolour the image if we don't have to. */
if (fg == info->cursor_fg && bg == info->cursor_bg)
return;
CURSOR_SWAPPING_START();
/* Note: We assume that the pixels are either fully opaque or fully
* transparent, so we won't premultiply them, and we can just
* check for non-zero pixel values; those are either fg or bg
*/
for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
if ((pixel = *pixels))
*pixels = (pixel == info->cursor_fg) ? fg : bg;
CURSOR_SWAPPING_END();
info->cursor_fg = fg;
info->cursor_bg = bg;
}
#ifdef ARGB_CURSOR
void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
{
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
CURSOR_SWAPPING_DECL_MMIO
uint32_t *d = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
info->cursor_argb = TRUE;
CURSOR_SWAPPING_START();
memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4);
CURSOR_SWAPPING_END ();
}
#endif
/* Initialize hardware cursor support. */
Bool RADEONCursorInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int c;
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
if (!info->useEXA) {
int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
int align = IS_AVIVO_VARIANT ? 4096 : 256;
radeon_crtc->cursor_offset =
radeon_legacy_allocate_memory(pScrn, &radeon_crtc->cursor_mem,
size_bytes, align, RADEON_GEM_DOMAIN_VRAM);
if (radeon_crtc->cursor_offset == 0)
return FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for hardware cursor %d at offset 0x%08x\n",
(size_bytes * xf86_config->num_crtc) / 1024,
c,
(unsigned int)radeon_crtc->cursor_offset);
}
/* set the cursor mode the same on both crtcs to avoid corruption */
/* XXX check if this is needed on evergreen */
if (IS_AVIVO_VARIANT)
OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
}
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
HARDWARE_CURSOR_ARGB));
}

2347
src/radeon_dri.c
View file

File diff suppressed because it is too large Load diff

91
src/radeon_dri.h
View file

@ -1,91 +0,0 @@
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
*
*/
#ifndef _RADEON_DRI_
#define _RADEON_DRI_
#include "xf86drm.h"
/* DRI Driver defaults */
#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */
#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */
#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */
#define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */
#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
#define RADEON_CARD_TYPE_RADEON 1
typedef struct {
/* DRI screen private data */
int deviceID; /* PCI device ID */
int width; /* Width in pixels of display */
int height; /* Height in scanlines of display */
int depth; /* Depth of display (8, 15, 16, 24) */
int bpp; /* Bit depth of display (8, 16, 24, 32) */
int IsPCI; /* Current card is a PCI card */
int AGPMode;
int frontOffset; /* Start of front buffer */
int frontPitch;
int backOffset; /* Start of shared back buffer */
int backPitch;
int depthOffset; /* Start of shared depth buffer */
int depthPitch;
int textureOffset;/* Start of texture data in frame buffer */
int textureSize;
int log2TexGran;
/* MMIO register data */
drm_handle_t registerHandle;
drmSize registerSize;
/* CP in-memory status information */
drm_handle_t statusHandle;
drmSize statusSize;
/* CP GART Texture data */
drm_handle_t gartTexHandle;
drmSize gartTexMapSize;
int log2GARTTexGran;
int gartTexOffset;
unsigned int sarea_priv_offset;
} RADEONDRIRec, *RADEONDRIPtr;
#endif

9
src/radeon_dri2.c
View file

@ -49,7 +49,6 @@
#endif
#endif
#ifdef RADEON_DRI2
#include "radeon_bo_gem.h"
@ -1319,11 +1318,6 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
Bool scheduling_works = TRUE;
#endif
if (!info->useEXA) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requires EXA\n");
return FALSE;
}
info->dri2.device_name = drmGetDeviceNameFromFd(info->dri2.drm_fd);
if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) {
@ -1349,7 +1343,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
dri2_info.CopyRegion = radeon_dri2_copy_region;
#ifdef USE_DRI2_SCHEDULING
if (info->dri->pKernelDRMVersion->version_minor < 4) {
if (info->dri2.pKernelDRMVersion->version_minor < 4) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for "
"sync extension\n");
scheduling_works = FALSE;
@ -1426,4 +1420,3 @@ void radeon_dri2_close_screen(ScreenPtr pScreen)
drmFree(info->dri2.device_name);
}
#endif

3
src/radeon_dri2.h
View file

@ -28,16 +28,15 @@
#define RADEON_DRI2_H
struct radeon_dri2 {
drmVersionPtr pKernelDRMVersion;
int drm_fd;
Bool enabled;
char *device_name;
};
#ifdef RADEON_DRI2
#include "dri2.h"
Bool radeon_dri2_screen_init(ScreenPtr pScreen);
void radeon_dri2_close_screen(ScreenPtr pScreen);
#endif
int drmmode_get_crtc_id(xf86CrtcPtr crtc);
xf86CrtcPtr radeon_covering_crtc(ScrnInfoPtr pScrn, BoxPtr box,

6219
src/radeon_driver.c
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File diff suppressed because it is too large Load diff

62
src/radeon_dummy_bufmgr.h
View file

@ -1,62 +0,0 @@
#ifndef RADEON_DUMMY_BUFMGR_H
#define RADEON_DUMMY_BUFMGR_H
/* when we don't have modesetting but we still need these functions */
struct radeon_bo {
int dummy;
void *ptr;
};
static inline int radeon_cs_begin(Bool dummy, int d2, const char *file,
const char *func, int line)
{
return 0;
}
static inline int radeon_cs_end(Bool dummy, const char *file,
const char *func, int line)
{
return 0;
}
static inline void radeon_cs_write_dword(Bool cs, uint32_t dword)
{
}
static inline int radeon_cs_write_reloc(Bool cs,
struct radeon_bo *bo,
uint32_t read_domain,
uint32_t write_domain,
uint32_t flags)
{
return 0;
}
static inline int radeon_bo_map(struct radeon_bo *bo, int write) {return 0;}
static inline void radeon_bo_ref(struct radeon_bo *bo) {return;}
static inline struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo) {return NULL;}
static inline void radeon_bo_unmap(struct radeon_bo *bo) {return;}
static inline int radeon_bo_wait(struct radeon_bo *bo) {return 0;}
static inline int radeon_cs_space_add_persistent_bo(Bool cs, struct radeon_bo *bo,
uint32_t read_domains, uint32_t write_domain)
{
return 0;
}
static inline int radeon_cs_space_check(Bool cs)
{
return 0;
}
static inline void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
{
}
static inline void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int n,
const char *file, const char *func, int line)
{
}
#endif

325
src/radeon_exa.c
View file

@ -36,9 +36,7 @@
#include "radeon.h"
#include "radeon_reg.h"
#include "r600_reg.h"
#ifdef XF86DRI
#include "radeon_drm.h"
#endif
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
@ -128,22 +126,7 @@ Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type)
static Bool RADEONPixmapIsColortiled(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
#ifdef XF86DRM_MODE
if (info->cs) {
/* Taken care of by the kernel relocation handling */
return FALSE;
}
#endif
/* This doesn't account for the back buffer, which we may want to wrap in
* a pixmap at some point for the purposes of DRI buffer moves.
*/
if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0)
return TRUE;
else
return FALSE;
return FALSE;
}
static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset,
@ -194,110 +177,6 @@ Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t)
return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1);
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
static unsigned long swapper_surfaces[6];
static Bool RADEONPrepareAccess_BE(PixmapPtr pPix, int index)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t offset = exaGetPixmapOffset(pPix);
int bpp, soff;
uint32_t size, flags;
/* Front buffer is always set with proper swappers */
if (offset == 0)
return TRUE;
/* If same bpp as front buffer, just do nothing as the main
* swappers will apply
*/
bpp = pPix->drawable.bitsPerPixel;
if (bpp == pScrn->bitsPerPixel)
return TRUE;
/* We need to setup a separate swapper, let's request a
* surface. We need to align the size first
*/
size = exaGetPixmapSize(pPix);
size = RADEON_ALIGN(size, RADEON_GPU_PAGE_SIZE);
/* Set surface to tiling disabled with appropriate swapper */
switch (bpp) {
case 16:
flags = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
break;
case 32:
flags = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
break;
default:
flags = 0;
}
#if defined(XF86DRI)
if (info->directRenderingEnabled && info->allowColorTiling) {
struct drm_radeon_surface_alloc drmsurfalloc;
int rc;
drmsurfalloc.address = offset;
drmsurfalloc.size = size;
drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */
rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (rc < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"drm: could not allocate surface for access"
" swapper, err: %d!\n", rc);
return FALSE;
}
swapper_surfaces[index] = offset;
return TRUE;
}
#endif
soff = (index + 1) * 0x10;
OUTREG(RADEON_SURFACE0_INFO + soff, flags);
OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset);
OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1);
swapper_surfaces[index] = offset;
return TRUE;
}
static void RADEONFinishAccess_BE(PixmapPtr pPix, int index)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t offset = exaGetPixmapOffset(pPix);
int soff;
/* Front buffer is always set with proper swappers */
if (offset == 0)
return;
if (swapper_surfaces[index] == 0)
return;
#if defined(XF86DRI)
if (info->directRenderingEnabled && info->allowColorTiling) {
struct drm_radeon_surface_free drmsurffree;
drmsurffree.address = offset;
drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
swapper_surfaces[index] = 0;
return;
}
#endif
soff = (index + 1) * 0x10;
OUTREG(RADEON_SURFACE0_INFO + soff, 0);
OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0);
OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0);
swapper_surfaces[index] = 0;
}
#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
#ifdef XF86DRM_MODE
Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
{
ScreenPtr pScreen = pPix->drawable.pScreen;
@ -457,9 +336,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
uint32_t size, heighta;
uint32_t tiling = 0;
int cpp = bitsPerPixel / 8;
#ifdef XF86DRM_MODE
struct radeon_surface surface;
#endif
#ifdef EXA_MIXED_PIXMAPS
if (info->accel_state->exa->flags & EXA_MIXED_PIXMAPS) {
@ -497,7 +374,6 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
memset(&surface, 0, sizeof(struct radeon_surface));
#ifdef XF86DRM_MODE
if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
if (width) {
surface.npix_x = width;
@ -560,7 +436,6 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
}
}
}
#endif
new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
if (!new_priv) {
@ -607,14 +482,12 @@ struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
return driver_priv->bo;
}
#if defined(XF86DRM_MODE)
struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix)
{
struct radeon_exa_pixmap_priv *driver_priv;
driver_priv = exaGetPixmapDriverPrivate(pPix);
return &driver_priv->surface;
}
#endif
uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix)
{
@ -653,39 +526,13 @@ Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
return TRUE;
return FALSE;
}
#endif
#define ENTER_DRAW(x) TRACE
#define LEAVE_DRAW(x) TRACE
/***********************************************************************/
#define ACCEL_MMIO
#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
#define OUT_RELOC(x, read, write) do {} while(0)
#define FINISH_ACCEL()
#ifdef RENDER
#include "radeon_exa_render.c"
#endif
#include "radeon_exa_funcs.c"
#undef ACCEL_MMIO
#undef ACCEL_PREAMBLE
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
#undef OUT_ACCEL_REG_F
#undef FINISH_ACCEL
#undef OUT_RELOC
#ifdef XF86DRI
#define ACCEL_CP
#define ACCEL_PREAMBLE() \
RING_LOCALS; \
RADEONCP_REFRESH(pScrn, info)
RING_LOCALS;
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
#define FINISH_ACCEL() ADVANCE_RING()
@ -698,178 +545,10 @@ Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
#endif
#include "radeon_exa_funcs.c"
#undef ACCEL_CP
#undef ACCEL_PREAMBLE
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
#undef FINISH_ACCEL
#undef OUT_RING_F
#endif /* XF86DRI */
/*
* Once screen->off_screen_base is set, this function
* allocates the remaining memory appropriately
*/
Bool RADEONSetupMemEXA (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
int screen_size;
int byteStride = pScrn->displayWidth * cpp;
if (info->accel_state->exa != NULL) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
return FALSE;
}
info->accel_state->exa = exaDriverAlloc();
if (info->accel_state->exa == NULL)
return FALSE;
/* Need to adjust screen size for 16 line tiles, and then make it align to.
* the buffer alignment requirement.
*/
if (info->allowColorTiling)
screen_size = RADEON_ALIGN(pScrn->virtualY, 16) * byteStride;
else
screen_size = pScrn->virtualY * byteStride;
info->accel_state->exa->memoryBase = info->FB;
info->accel_state->exa->memorySize = info->FbMapSize - info->FbSecureSize;
info->accel_state->exa->offScreenBase = screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocating from a screen of %ld kb\n",
info->accel_state->exa->memorySize / 1024);
/* Reserve static area for hardware cursor */
if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
int cursor_size = 64 * 4 * 64;
int align = IS_AVIVO_VARIANT ? 4096 : 256;
int c;
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
radeon_crtc->cursor_offset =
RADEON_ALIGN(info->accel_state->exa->offScreenBase, align);
info->accel_state->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for hardware cursor %d at offset 0x%08x\n",
(cursor_size * xf86_config->num_crtc) / 1024,
c,
(unsigned int)radeon_crtc->cursor_offset);
}
}
#if defined(XF86DRI)
if (info->directRenderingEnabled) {
int depthCpp = (info->dri->depthBits - 8) / 4, l, next, depth_size;
info->dri->frontOffset = 0;
info->dri->frontPitch = pScrn->displayWidth;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for front buffer at offset 0x%08x\n",
screen_size / 1024, info->dri->frontOffset);
RADEONDRIAllocatePCIGARTTable(pScreen);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for PCI GART at offset 0x%08x\n",
info->dri->pciGartSize / 1024,
(int)info->dri->pciGartOffset);
/* Reserve a static area for the back buffer the same size as the
* visible screen. XXX: This would be better initialized in ati_dri.c
* when GLX is set up, but the offscreen memory manager's allocations
* don't last through VT switches, while the kernel's understanding of
* offscreen locations does.
*/
info->dri->backPitch = pScrn->displayWidth;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE);
if (!info->dri->noBackBuffer &&
next + screen_size <= info->accel_state->exa->memorySize)
{
info->dri->backOffset = next;
info->accel_state->exa->offScreenBase = next + screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for back buffer at offset 0x%08x\n",
screen_size / 1024, info->dri->backOffset);
}
/* Reserve the static depth buffer, and adjust pitch and height to
* handle tiling.
*/
info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE);
if (next + depth_size <= info->accel_state->exa->memorySize)
{
info->dri->depthOffset = next;
info->accel_state->exa->offScreenBase = next + depth_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for depth buffer at offset 0x%08x\n",
depth_size / 1024, info->dri->depthOffset);
}
info->dri->textureSize *= (info->accel_state->exa->memorySize -
info->accel_state->exa->offScreenBase) / 100;
l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
info->dri->textureSize = (info->dri->textureSize >> l) << l;
if (info->dri->textureSize >= 512 * 1024) {
info->dri->textureOffset = info->accel_state->exa->offScreenBase;
info->accel_state->exa->offScreenBase += info->dri->textureSize;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%08x\n",
info->dri->textureSize / 1024, info->dri->textureOffset);
} else {
/* Minimum texture size is for 2 256x256x32bpp textures */
info->dri->textureSize = 0;
}
} else
#endif /* XF86DRI */
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for front buffer at offset 0x%08x\n",
screen_size / 1024, 0);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %ld kb for X Server offscreen at offset 0x%08lx\n",
(info->accel_state->exa->memorySize - info->accel_state->exa->offScreenBase) /
1024, info->accel_state->exa->offScreenBase);
return TRUE;
}
#ifdef XF86DRI
#ifndef ExaOffscreenMarkUsed
extern void ExaOffscreenMarkUsed(PixmapPtr);
#endif
unsigned long long
RADEONTexOffsetStart(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
unsigned long long offset;
if (exaGetPixmapDriverPrivate(pPix))
return -1;
exaMoveInPixmap(pPix);
ExaOffscreenMarkUsed(pPix);
offset = exaGetPixmapOffset(pPix);
if (offset > info->FbMapSize)
return ~0ULL;
else
return info->fbLocation + offset;
}
#endif

303
src/radeon_exa_funcs.c
View file

@ -31,25 +31,13 @@
*
*/
#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
#error Cannot define both MMIO and CP acceleration!
#endif
#if !defined(UNIXCPP) || defined(ANSICPP)
#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
#else
#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
#endif
#ifdef ACCEL_MMIO
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
#else
#ifdef ACCEL_CP
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
#else
#error No accel type defined!
#endif
#endif
#include <errno.h>
#include <string.h>
@ -71,20 +59,7 @@ FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
static void
FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cs)
return;
TRACE;
if (info->accel_state->exaMarkerSynced != marker) {
FUNC_NAME(RADEONWaitForIdle)(pScrn);
info->accel_state->exaMarkerSynced = marker;
}
RADEONPTR(pScrn)->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
}
static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
@ -97,7 +72,7 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
if (info->state_2d.op == 0 && op == 0)
return;
has_src = info->state_2d.src_pitch_offset || (info->cs && info->state_2d.src_bo);
has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo;
if (has_src) {
BEGIN_ACCEL_RELOC(10, 2);
@ -114,21 +89,17 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
OUT_ACCEL_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
if (info->cs)
OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
if (has_src) {
OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
if (info->cs)
OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
}
FINISH_ACCEL();
if (op)
info->state_2d.op = op;
if (info->cs)
info->reemit_current2d = FUNC_NAME(Emit2DState);
info->reemit_current2d = FUNC_NAME(Emit2DState);
}
static void
@ -160,6 +131,8 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
uint32_t datatype, dst_pitch_offset;
struct radeon_exa_pixmap_priv *driver_priv;
int ret;
TRACE;
@ -172,25 +145,18 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
RADEON_SWITCH_TO_2D();
#ifdef XF86DRM_MODE
if (info->cs) {
struct radeon_exa_pixmap_priv *driver_priv;
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_reset_bos(info->cs);
driver_priv = exaGetPixmapDriverPrivate(pPix);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
driver_priv = exaGetPixmapDriverPrivate(pPix);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
driver_priv = exaGetPixmapDriverPrivate(pPix);
if (driver_priv)
info->state_2d.dst_bo = driver_priv->bo;
}
#endif
driver_priv = exaGetPixmapDriverPrivate(pPix);
if (driver_priv)
info->state_2d.dst_bo = driver_priv->bo;
info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX |
RADEON_DEFAULT_SC_BOTTOM_MAX);
@ -226,12 +192,10 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
TRACE;
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
if (CS_FULL(info->cs)) {
FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif
if (info->accel_state->vsync)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix,
@ -283,6 +247,8 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
uint32_t datatype, src_pitch_offset, dst_pitch_offset;
struct radeon_exa_pixmap_priv *driver_priv;
int ret;
TRACE;
if (pDst->drawable.bitsPerPixel == 24)
@ -296,26 +262,19 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
RADEON_SWITCH_TO_2D();
#ifdef XF86DRM_MODE
if (info->cs) {
struct radeon_exa_pixmap_priv *driver_priv;
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_reset_bos(info->cs);
driver_priv = exaGetPixmapDriverPrivate(pSrc);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
info->state_2d.src_bo = driver_priv->bo;
driver_priv = exaGetPixmapDriverPrivate(pSrc);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
info->state_2d.src_bo = driver_priv->bo;
driver_priv = exaGetPixmapDriverPrivate(pDst);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
info->state_2d.dst_bo = driver_priv->bo;
driver_priv = exaGetPixmapDriverPrivate(pDst);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
info->state_2d.dst_bo = driver_priv->bo;
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n"));
}
#endif
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n"));
info->accel_state->xdir = xdir;
info->accel_state->ydir = ydir;
@ -338,12 +297,10 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
TRACE;
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
if (CS_FULL(info->cs)) {
FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif
if (info->accel_state->xdir < 0) {
srcX += w - 1;
@ -368,50 +325,6 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
FINISH_ACCEL();
}
#ifdef ACCEL_CP
static Bool
RADEONUploadToScreenCP(PixmapPtr pDst, int x, int y, int w, int h,
char *src, int src_pitch)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
unsigned int bpp = pDst->drawable.bitsPerPixel;
unsigned int hpass;
uint32_t buf_pitch, dst_pitch_off;
TRACE;
if (bpp < 8)
return FALSE;
if (info->directRenderingEnabled &&
RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) {
uint8_t *buf;
int cpp = bpp / 8;
ACCEL_PREAMBLE();
RADEON_SWITCH_TO_2D();
if (info->accel_state->vsync)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst,
radeon_pick_best_crtc(pScrn, x, x + w, y, y + h),
y, y + h);
while ((buf = RADEONHostDataBlit(pScrn,
cpp, w, dst_pitch_off, &buf_pitch,
x, &y, (unsigned int*)&h, &hpass)) != 0) {
RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (uint8_t *)src,
hpass, buf_pitch, src_pitch);
src += hpass * src_pitch;
}
exaMarkSync(pDst->drawable.pScreen);
return TRUE;
}
return FALSE;
}
/* Emit blit with arbitrary source and destination offsets and pitches */
static void
RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
@ -459,7 +372,6 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
FINISH_ACCEL();
}
#if defined(XF86DRM_MODE)
static Bool
RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
char *src, int src_pitch)
@ -672,118 +584,6 @@ out:
radeon_bo_unref(scratch);
return r;
}
#endif
static Bool
RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h,
char *dst, int dst_pitch)
{
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
uint8_t *src = info->FB + exaGetPixmapOffset(pSrc);
int bpp = pSrc->drawable.bitsPerPixel;
uint32_t datatype, src_pitch_offset, scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64), scratch_off = 0;
drmBufPtr scratch;
TRACE;
/*
* Try to accelerate download. Use an indirect buffer as scratch space,
* blitting the bits to one half while copying them out of the other one and
* then swapping the halves.
*/
if (bpp != 24 && RADEONGetDatatypeBpp(bpp, &datatype) &&
RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) &&
(scratch = RADEONCPGetBuffer(pScrn)))
{
int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8;
int hpass = min(h, scratch->total/2 / scratch_pitch);
uint32_t scratch_pitch_offset = scratch_pitch << 16
| (info->gartLocation + info->dri->bufStart
+ scratch->idx * scratch->total) >> 10;
drm_radeon_indirect_t indirect;
ACCEL_PREAMBLE();
RADEON_SWITCH_TO_2D();
/* Kick the first blit as early as possible */
RADEONBlitChunk(pScrn, NULL, NULL, datatype, src_pitch_offset,
scratch_pitch_offset, x, y, 0, 0, w, hpass, 0, 0);
FLUSH_RING();
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 16:
swap = RADEON_HOST_DATA_SWAP_16BIT;
break;
case 32:
swap = RADEON_HOST_DATA_SWAP_32BIT;
break;
}
#endif
while (h) {
int oldhpass = hpass, i = 0;
src = (uint8_t*)scratch->address + scratch_off;
y += oldhpass;
h -= oldhpass;
hpass = min(h, scratch->total/2 / scratch_pitch);
/* Prepare next blit if anything's left */
if (hpass) {
scratch_off = scratch->total/2 - scratch_off;
RADEONBlitChunk(pScrn, NULL, NULL, datatype, src_pitch_offset,
scratch_pitch_offset + (scratch_off >> 10),
x, y, 0, 0, w, hpass, 0, 0);
}
/*
* Wait for previous blit to complete.
*
* XXX: Doing here essentially the same things this ioctl does in
* the DRM results in corruption with 'small' transfers, apparently
* because the data doesn't actually land in system RAM before the
* memcpy. I suspect the ioctl helps mostly due to its latency; what
* we'd really need is a way to reliably wait for the host interface
* to be done with pushing the data to the host.
*/
while ((drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
&& (i++ < RADEON_TIMEOUT))
;
/* Kick next blit */
if (hpass)
FLUSH_RING();
/* Copy out data from previous blit */
if (wpass == scratch_pitch && wpass == dst_pitch) {
RADEONCopySwap((uint8_t*)dst, src, wpass * oldhpass, swap);
dst += dst_pitch * oldhpass;
} else while (oldhpass--) {
RADEONCopySwap((uint8_t*)dst, src, wpass, swap);
src += scratch_pitch;
dst += dst_pitch;
}
}
indirect.idx = scratch->idx;
indirect.start = indirect.end = 0;
indirect.discard = 1;
drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drm_radeon_indirect_t));
info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker;
return TRUE;
}
return FALSE;
}
#endif /* def ACCEL_CP */
Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
{
@ -807,24 +607,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
info->accel_state->exa->MarkSync = FUNC_NAME(RADEONMarkSync);
info->accel_state->exa->WaitMarker = FUNC_NAME(RADEONSync);
#ifdef ACCEL_CP
if (!info->kms_enabled) {
info->accel_state->exa->UploadToScreen = RADEONUploadToScreenCP;
if (info->accelDFS)
info->accel_state->exa->DownloadFromScreen = RADEONDownloadFromScreenCP;
}
# if defined(XF86DRM_MODE)
else {
info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS;
}
# endif
#endif
#if X_BYTE_ORDER == X_BIG_ENDIAN
info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_BE;
info->accel_state->exa->FinishAccess = RADEONFinishAccess_BE;
#endif
info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS;
info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS;
#ifdef EXA_SUPPORTS_PREPARE_AUX
@ -838,21 +623,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
info->accel_state->exa->pixmapPitchAlign = 64;
#ifdef EXA_HANDLES_PIXMAPS
if (info->cs) {
info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS;
info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS;
#ifdef EXA_MIXED_PIXMAPS
info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS;
info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS;
#endif
}
#endif
#ifdef RENDER
if (info->RenderAccel) {
if (IS_R300_3D || IS_R500_3D) {
if ((info->ChipFamily < CHIP_FAMILY_RS400)
#ifdef XF86DRI
|| (info->directRenderingEnabled)
#endif
) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R300/R400/R500 type cards.\n");
@ -883,18 +664,14 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
}
#endif
#ifdef XF86DRM_MODE
#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
if (info->cs) {
info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5)
info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
#endif
}
info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
#endif
#endif

142
src/radeon_exa_render.c
View file

@ -30,29 +30,15 @@
*
*/
#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
#error Cannot define both MMIO and CP acceleration!
#endif
#if !defined(UNIXCPP) || defined(ANSICPP)
#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
#else
#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
#endif
#ifdef ACCEL_MMIO
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
#else
#ifdef ACCEL_CP
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
#else
#error No accel type defined!
#endif
#endif
#ifndef ACCEL_CP
#define ONLY_ONCE
#endif
/* Only include the following (generic) bits once. */
#ifdef ONLY_ONCE
@ -404,8 +390,6 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txpitch = exaGetPixmapPitch(pPix);
txoffset = 0;
CHECK_OFFSET(pPix, 0x1f, "texture");
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
@ -581,6 +565,7 @@ RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture
PixmapPtr pDst)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
int ret;
info->accel_state->composite_op = op;
info->accel_state->dst_pic = pDstPicture;
@ -590,25 +575,19 @@ RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture
info->accel_state->msk_pix = pMask;
info->accel_state->src_pix = pSrc;
#ifdef XF86DRM_MODE
if (info->cs) {
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_reset_bos(info->cs);
radeon_add_pixmap(info->cs, pSrc,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pSrc,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pMask)
radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pMask)
radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
}
#endif
ret = radeon_cs_space_check(info->cs);
if (ret)
RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
return TRUE;
}
@ -646,8 +625,6 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
if (RADEONPixmapIsColortiled(pDst))
colorpitch |= RADEON_COLOR_TILE_ENABLE;
CHECK_OFFSET(pDst, 0x0f, "destination");
if (!pSrc) {
pSrc = RADEONSolidPixmap(pScreen, cpu_to_le32(pSrcPicture->pSourcePict->solidFill.color));
if (!pSrc)
@ -821,7 +798,6 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txpitch = exaGetPixmapPitch(pPix);
txoffset = 0;
CHECK_OFFSET(pPix, 0x1f, "texture");
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
@ -1019,8 +995,6 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
if (RADEONPixmapIsColortiled(pDst))
colorpitch |= RADEON_COLOR_TILE_ENABLE;
CHECK_OFFSET(pDst, 0xf, "destination");
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
@ -1139,9 +1113,6 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
int unit,
Bool is_r500)
{
ScreenPtr pScreen = pDstPict->pDrawable->pScreen;
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone;
int i;
@ -1155,14 +1126,14 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
(int)pPict->format));
if (pPict->pDrawable && !RADEONCheckTexturePOT(pPict, unit == 0)) {
if (info->cs) {
struct radeon_exa_pixmap_priv *driver_priv;
#if 0
struct radeon_exa_pixmap_priv *driver_priv;
PixmapPtr pPix;
pPix = RADEONGetDrawablePixmap(pPict->pDrawable);
driver_priv = exaGetPixmapDriverPrivate(pPix);
//TODOradeon_bufmgr_gem_force_gtt(driver_priv->bo);
}
#endif
return FALSE;
}
@ -1216,8 +1187,6 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txpitch = exaGetPixmapPitch(pPix);
txoffset = 0;
CHECK_OFFSET(pPix, 0x1f, "texture");
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
@ -1527,8 +1496,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
colorpitch |= dst_format;
CHECK_OFFSET(pDst, 0x0f, "destination");
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
@ -2233,8 +2200,6 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
pScreen->DestroyPixmap(accel_state->msk_pix);
}
#ifdef ACCEL_CP
#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
OUT_RING_F(_dstX); \
@ -2253,28 +2218,6 @@ do { \
OUT_RING_F(_srcY); \
} while (0)
#else /* ACCEL_CP */
#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
} while (0)
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
} while (0)
#endif /* !ACCEL_CP */
#ifdef ONLY_ONCE
static inline void transformPoint(PictTransform *transform, xPointFixed *point)
{
@ -2306,15 +2249,9 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
/* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
#if defined(ACCEL_CP)
if ((info->cs && CS_FULL(info->cs)) ||
(!info->cs && (info->cp->indirectBuffer->used + 4 * 32) >
info->cp->indirectBuffer->total)) {
if (CS_FULL(info->cs)) {
FUNC_NAME(RadeonFinishComposite)(info->accel_state->dst_pix);
if (info->cs)
radeon_cs_flush_indirect(pScrn);
else
RADEONCPFlushIndirect(pScrn, 1);
radeon_cs_flush_indirect(pScrn);
info->accel_state->exa->PrepareComposite(info->accel_state->composite_op,
info->accel_state->src_pic,
info->accel_state->msk_pic,
@ -2323,7 +2260,6 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
info->accel_state->msk_pix,
info->accel_state->dst_pix);
}
#endif
srcTopLeft.x = IntToxFixed(srcX);
srcTopLeft.y = IntToxFixed(srcY);
@ -2371,17 +2307,11 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
dstY, dstY + h);
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
if (!info->accel_state->draw_header) {
BEGIN_RING(3);
#ifdef XF86DRM_MODE
if (info->cs)
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
else
#endif
info->accel_state->draw_header = __head;
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
info->accel_state->num_vtx = 0;
info->accel_state->vtx_count = vtx_count;
@ -2408,12 +2338,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
if (!info->accel_state->draw_header) {
BEGIN_RING(2);
#ifdef XF86DRM_MODE
if (info->cs)
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
else
#endif
info->accel_state->draw_header = __head;
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
info->accel_state->num_vtx = 0;
info->accel_state->vtx_count = vtx_count;
@ -2431,12 +2356,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
if (!info->accel_state->draw_header) {
BEGIN_RING(2);
#ifdef XF86DRM_MODE
if (info->cs)
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
else
#endif
info->accel_state->draw_header = __head;
info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
info->accel_state->num_vtx = 0;
info->accel_state->vtx_count = vtx_count;
@ -2452,28 +2372,6 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
BEGIN_RING(3 * vtx_count);
}
#else /* ACCEL_CP */
if (IS_R300_3D || IS_R500_3D)
BEGIN_ACCEL(2 + vtx_count * 4);
else
BEGIN_ACCEL(1 + vtx_count * 3);
if (info->ChipFamily < CHIP_FAMILY_R200)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
else if (IS_R300_3D || IS_R500_3D)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
else
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
#endif
if (info->accel_state->msk_pic) {
if (IS_R300_3D || IS_R500_3D) {
VTX_OUT_MASK((float)dstX, (float)dstY,
@ -2502,11 +2400,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
}
#ifdef ACCEL_CP
ADVANCE_RING();
#else
FINISH_ACCEL();
#endif /* !ACCEL_CP */
LEAVE_DRAW(0);
}

92
src/radeon_exa_shared.c
View file

@ -35,9 +35,6 @@
#endif
#include "radeon.h"
#ifdef XF86DRI
#include "radeon_drm.h"
#endif
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
@ -128,76 +125,32 @@ Bool RADEONCheckBPP(int bpp)
PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPix = pScreen->CreatePixmap(pScreen, 1, 1, 32, 0);
struct radeon_bo *bo;
exaMoveInPixmap(pPix);
#if defined(XF86DRM_MODE)
if (info->cs) {
struct radeon_bo *bo;
bo = radeon_get_pixmap_bo(pPix);
bo = radeon_get_pixmap_bo(pPix);
if (radeon_bo_map(bo, 1)) {
pScreen->DestroyPixmap(pPix);
return NULL;
}
memcpy(bo->ptr, &solid, 4);
radeon_bo_unmap(bo);
return pPix;
}
#endif
if (!exaDrawableIsOffscreen(&pPix->drawable)) {
if (radeon_bo_map(bo, 1)) {
pScreen->DestroyPixmap(pPix);
return NULL;
}
/* XXX: Big hammer... */
info->accel_state->exa->WaitMarker(pScreen, info->accel_state->exaSyncMarker);
memcpy(info->FB + exaGetPixmapOffset(pPix), &solid, 4);
memcpy(bo->ptr, &solid, 4);
radeon_bo_unmap(bo);
return pPix;
}
static Bool radeon_vb_get(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
accel_state->vbo.vb_mc_addr = info->gartLocation + info->dri->bufStart +
(accel_state->ib->idx*accel_state->ib->total)+
(accel_state->ib->total / 2);
accel_state->vbo.vb_total = (accel_state->ib->total / 2);
accel_state->vbo.vb_ptr = (pointer)((char*)accel_state->ib->address +
(accel_state->ib->total / 2));
accel_state->vbo.vb_offset = 0;
return TRUE;
}
int radeon_cp_start(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
#if defined(XF86DRM_MODE)
if (info->cs) {
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
}
accel_state->ib_reset_op = info->cs->cdw;
} else
#endif
{
accel_state->ib = RADEONCPGetBuffer(pScrn);
if (!radeon_vb_get(pScrn)) {
return -1;
}
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
}
accel_state->ib_reset_op = info->cs->cdw;
accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset;
return 0;
@ -210,30 +163,20 @@ void radeon_vb_no_space(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
#if defined(XF86DRM_MODE)
if (info->cs) {
if (vbo->vb_bo) {
if (vbo->vb_start_op != vbo->vb_offset) {
accel_state->finish_op(pScrn, vert_size);
accel_state->ib_reset_op = info->cs->cdw;
}
/* release the current VBO */
radeon_vbo_put(pScrn, vbo);
if (vbo->vb_bo) {
if (vbo->vb_start_op != vbo->vb_offset) {
accel_state->finish_op(pScrn, vert_size);
accel_state->ib_reset_op = info->cs->cdw;
}
/* get a new one */
radeon_vbo_get(pScrn, vbo);
return;
}
#endif
if (vbo->vb_start_op != -1) {
accel_state->finish_op(pScrn, vert_size);
radeon_cp_start(pScrn);
/* release the current VBO */
radeon_vbo_put(pScrn, vbo);
}
/* get a new one */
radeon_vbo_get(pScrn, vbo);
return;
}
#if defined(XF86DRM_MODE)
void radeon_ib_discard(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -277,4 +220,3 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
}
}
#endif

2
src/radeon_exa_shared.h
View file

@ -62,7 +62,6 @@ do { \
#define TRACE
#endif
#ifdef XF86DRM_MODE
static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
{
struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
@ -71,7 +70,6 @@ static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int r
}
extern void radeon_ib_discard(ScrnInfoPtr pScrn);
#endif /* XF86DRM_MODE */
extern int radeon_cp_start(ScrnInfoPtr pScrn);
extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);

156
src/radeon_kms.c
View file

@ -40,8 +40,13 @@
#include "atipciids.h"
#ifdef XF86DRM_MODE
/* DPMS */
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include "radeon_chipset_gen.h"
#include "radeon_chipinfo_gen.h"
@ -76,6 +81,8 @@ const OptionInfoRec RADEONOptions_KMS[] = {
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; }
void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -202,8 +209,6 @@ static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL)
(*pScreen->BlockHandler) (BLOCKHANDLER_ARGS);
pScreen->BlockHandler = RADEONBlockHandler_KMS;
if (info->VideoTimerCallback)
(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
radeon_cs_flush_indirect(pScrn);
}
@ -231,7 +236,7 @@ static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn)
memset(&ginfo, 0, sizeof(ginfo));
ginfo.request = RADEON_INFO_FUSION_GART_WORKING;
ginfo.value = (uintptr_t)&tmp;
r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
if (r) {
return FALSE;
}
@ -255,12 +260,12 @@ static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
#endif
memset(&ginfo, 0, sizeof(ginfo));
if (info->dri->pKernelDRMVersion->version_minor >= 5)
if (info->dri2.pKernelDRMVersion->version_minor >= 5)
ginfo.request = RADEON_INFO_ACCEL_WORKING2;
else
ginfo.request = RADEON_INFO_ACCEL_WORKING;
ginfo.value = (uintptr_t)&tmp;
r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
if (r) {
/* If kernel is too old before 2.6.32 than assume accel is working */
if (r == -EINVAL) {
@ -312,9 +317,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
info->accel_state->has_tcl = TRUE;
}
info->useEXA = TRUE;
if (info->useEXA) {
{
int errmaj = 0, errmin = 0;
info->exaReq.majorversion = EXA_VERSION_MAJOR;
info->exaReq.minorversion = EXA_VERSION_MINOR;
@ -356,7 +359,6 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
if (info->Chipset == RADEONCards[i].pci_device_id) {
RADEONCardInfo *card = &RADEONCards[i];
info->ChipFamily = card->chip_family;
info->IsMobility = card->mobility;
info->IsIGP = card->igp;
break;
}
@ -409,21 +411,6 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
return TRUE;
}
static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
return FALSE;
}
if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
return FALSE;
}
return TRUE;
}
static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@ -481,7 +468,6 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
pRADEONEnt->fd = info->dri2.drm_fd;
out:
info->drmmode.fd = info->dri2.drm_fd;
info->dri->drmFD = info->dri2.drm_fd;
return TRUE;
}
@ -504,14 +490,14 @@ static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
memset(&ginfo, 0, sizeof(ginfo));
ginfo.request = RADEON_INFO_TILING_CONFIG;
ginfo.value = (uintptr_t)&tmp;
r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
if (r)
return FALSE;
info->tile_config = tmp;
info->r7xx_bank_op = 0;
if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
if (info->dri->pKernelDRMVersion->version_minor >= 7) {
if (info->dri2.pKernelDRMVersion->version_minor >= 7) {
switch (info->tile_config & 0xf) {
case 0:
info->num_channels = 1;
@ -615,10 +601,8 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
if (!RADEONGetRec(pScrn)) return FALSE;
info = RADEONPTR(pScrn);
info->MMIO = NULL;
info->IsSecondary = FALSE;
info->IsPrimary = FALSE;
info->kms_enabled = TRUE;
info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
if (info->pEnt->location.type != BUS_PCI) goto fail;
@ -661,17 +645,14 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitChipType_KMS(pScrn))
goto fail;
if (!radeon_alloc_dri(pScrn))
return FALSE;
if (radeon_open_drm_master(pScrn) == FALSE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
goto fail;
}
info->dri2.enabled = FALSE;
info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD);
if (info->dri->pKernelDRMVersion == NULL) {
info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd);
if (info->dri2.pKernelDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RADEONDRIGetVersion failed to get the DRM version\n");
goto fail;
@ -698,7 +679,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
/* set default group bytes, overridden by kernel info below */
info->group_bytes = 256;
info->have_tiling_info = FALSE;
if (info->dri->pKernelDRMVersion->version_minor >= 6) {
if (info->dri2.pKernelDRMVersion->version_minor >= 6) {
if (r600_get_tile_config(pScrn)) {
info->allowColorTiling = xf86ReturnOptValBool(info->Options,
OPTION_COLOR_TILING, colorTilingDefault);
@ -724,7 +705,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
if (info->dri->pKernelDRMVersion->version_minor >= 8) {
if (info->dri2.pKernelDRMVersion->version_minor >= 8) {
info->allowPageFlip = xf86ReturnOptValBool(info->Options,
OPTION_PAGE_FLIP, TRUE);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@ -769,7 +750,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
{
struct drm_radeon_gem_info mminfo;
if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
{
info->vram_size = mminfo.vram_visible;
info->gart_size = mminfo.gart_size;
@ -838,6 +819,49 @@ static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
HARDWARE_CURSOR_ARGB));
}
void
RADEONBlank(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
xf86OutputPtr output;
xf86CrtcPtr crtc;
int o, c;
for (c = 0; c < xf86_config->num_crtc; c++) {
crtc = xf86_config->crtc[c];
for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
output->funcs->dpms(output, DPMSModeOff);
}
crtc->funcs->dpms(crtc, DPMSModeOff);
}
}
void
RADEONUnblank(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
xf86OutputPtr output;
xf86CrtcPtr crtc;
int o, c;
for (c = 0; c < xf86_config->num_crtc; c++) {
crtc = xf86_config->crtc[c];
if(!crtc->enabled)
continue;
crtc->funcs->dpms(crtc, DPMSModeOn);
for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
output->funcs->dpms(output, DPMSModeOn);
}
}
}
static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
{
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
@ -871,8 +895,7 @@ static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL)
"RADEONCloseScreen\n");
drmmode_uevent_fini(pScrn, &info->drmmode);
if (info->cs)
radeon_cs_flush_indirect(pScrn);
radeon_cs_flush_indirect(pScrn);
DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
@ -885,10 +908,7 @@ static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL)
if (info->accel_state->use_vbos)
radeon_vbo_free_lists(pScrn);
drmDropMaster(info->dri->drmFD);
if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
info->cursor = NULL;
drmDropMaster(info->dri2.drm_fd);
if (info->dri2.enabled)
radeon_dri2_close_screen(pScreen);
@ -933,7 +953,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
pScrn->defaultVisual)) return FALSE;
miSetPixmapDepths ();
ret = drmSetMaster(info->dri->drmFD);
ret = drmSetMaster(info->dri2.drm_fd);
if (ret) {
ErrorF("Unable to retrieve master\n");
return FALSE;
@ -942,11 +962,9 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
if (info->r600_shadow_fb == FALSE)
info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
front_ptr = info->FB;
info->surf_man = radeon_surface_manager_new(info->dri->drmFD);
info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd);
if (!info->bufmgr)
info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD);
info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd);
if (!info->bufmgr) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"failed to initialise GEM buffer manager");
@ -955,7 +973,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
if (!info->csm)
info->csm = radeon_cs_manager_gem_ctor(info->dri->drmFD);
info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd);
if (!info->csm) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"failed to initialise command submission manager");
@ -1158,7 +1176,7 @@ Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL)
"RADEONEnterVT_KMS\n");
ret = drmSetMaster(info->dri->drmFD);
ret = drmSetMaster(info->dri2.drm_fd);
if (ret)
ErrorF("Unable to retrieve master\n");
info->accel_state->XInited3D = FALSE;
@ -1169,9 +1187,6 @@ Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL)
if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
return FALSE;
if (info->adaptor)
RADEONResetVideo(pScrn);
return TRUE;
}
@ -1184,7 +1199,7 @@ void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONLeaveVT_KMS\n");
drmDropMaster(info->dri->drmFD);
drmDropMaster(info->dri2.drm_fd);
#ifdef HAVE_FREE_SHADOW
xf86RotateFreeShadow(pScrn);
@ -1341,8 +1356,6 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
/* keep area front front buffer - but don't allocate it yet */
total_size_bytes += screen_size;
info->dri->textureSize = 0;
if (info->front_bo == NULL) {
info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
base_align, RADEON_GEM_DOMAIN_VRAM, 0);
@ -1392,5 +1405,30 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
}
/* Used to disallow modes that are not supported by the hardware */
ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
Bool verbose, int flag)
{
SCRN_INFO_PTR(arg);
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
#endif
/*
* RN50 has effective maximum mode bandwidth of about 300MiB/s.
* XXX should really do this for all chips by properly computing
* memory bandwidth and an overhead factor.
*/
if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
return MODE_BANDWIDTH;
}
/* There are problems with double scan mode at high clocks
* They're likely related PLL and display buffer settings.
* Disable these modes for now.
*/
if (mode->Flags & V_DBLSCAN) {
if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768))
return MODE_CLOCK_RANGE;
}
return MODE_OK;
}

123
src/radeon_legacy_memory.c
View file

@ -18,126 +18,27 @@ radeon_legacy_allocate_memory(ScrnInfoPtr pScrn,
int align,
int domain)
{
ScreenPtr pScreen = xf86ScrnToScreen(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t offset = 0;
struct radeon_bo *video_bo;
#ifdef XF86DRM_MODE
if (info->cs) {
struct radeon_bo *video_bo;
if (*mem_struct)
radeon_legacy_free_memory(pScrn, *mem_struct);
if (*mem_struct)
radeon_legacy_free_memory(pScrn, *mem_struct);
video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0);
video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0);
*mem_struct = video_bo;
*mem_struct = video_bo;
if (!video_bo)
return 0;
if (!video_bo)
return 0;
return (uint32_t)-1;
}
#endif
#ifdef USE_EXA
if (info->useEXA) {
ExaOffscreenArea *area = *mem_struct;
if (area != NULL) {
if (area->size >= size)
return area->offset;
exaOffscreenFree(pScreen, area);
}
area = exaOffscreenAlloc(pScreen, size, align, TRUE,
NULL, NULL);
*mem_struct = area;
if (area == NULL)
return 0;
offset = area->offset;
}
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
FBLinearPtr linear = *mem_struct;
int cpp = info->CurrentLayout.bitsPerPixel / 8;
/* XAA allocates in units of pixels at the screen bpp, so adjust size
* appropriately.
*/
size = (size + cpp - 1) / cpp;
align = (align + cpp - 1) / cpp;
if (linear) {
if(linear->size >= size)
return linear->offset * cpp;
if(xf86ResizeOffscreenLinear(linear, size))
return linear->offset * cpp;
xf86FreeOffscreenLinear(linear);
}
linear = xf86AllocateOffscreenLinear(pScreen, size, align,
NULL, NULL, NULL);
*mem_struct = linear;
if (!linear) {
int max_size;
xf86QueryLargestOffscreenLinear(pScreen, &max_size, align,
PRIORITY_EXTREME);
if (max_size < size)
return 0;
xf86PurgeUnlockedOffscreenAreas(pScreen);
linear = xf86AllocateOffscreenLinear(pScreen, size, align,
NULL, NULL, NULL);
*mem_struct = linear;
if (!linear)
return 0;
}
offset = linear->offset * cpp;
}
#endif /* USE_XAA */
return offset;
return (uint32_t)-1;
}
void
radeon_legacy_free_memory(ScrnInfoPtr pScrn,
void *mem_struct)
void *mem_struct)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef XF86DRM_MODE
if (info->cs) {
struct radeon_bo *bo = mem_struct;
radeon_bo_unref(bo);
return;
}
#endif
#ifdef USE_EXA
ScreenPtr pScreen = xf86ScrnToScreen(pScrn);
if (info->useEXA) {
ExaOffscreenArea *area = mem_struct;
if (area != NULL)
exaOffscreenFree(pScreen, area);
area = NULL;
}
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
FBLinearPtr linear = mem_struct;
if (linear != NULL)
xf86FreeOffscreenLinear(linear);
linear = NULL;
}
#endif /* USE_XAA */
struct radeon_bo *bo = mem_struct;
radeon_bo_unref(bo);
return;
}

146
src/radeon_macros.h
View file

@ -51,159 +51,31 @@
#include "compiler.h"
#define RADEON_BIOS8(v) (info->VBIOS[v])
#define RADEON_BIOS16(v) (info->VBIOS[v] | \
(info->VBIOS[(v) + 1] << 8))
#define RADEON_BIOS32(v) (info->VBIOS[v] | \
(info->VBIOS[(v) + 1] << 8) | \
(info->VBIOS[(v) + 2] << 16) | \
(info->VBIOS[(v) + 3] << 24))
/* Memory mapped register access macros */
#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
#define INREG16(addr) MMIO_IN16(RADEONMMIO, addr)
#define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val)
#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)
#define ADDRREG(addr) ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr)))
#define OUTREGP(addr, val, mask) \
do { \
uint32_t tmp = INREG(addr); \
tmp &= (mask); \
tmp |= ((val) & ~(mask)); \
OUTREG(addr, tmp); \
} while (0)
#define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr)
#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val)
#define OUTPLLP(pScrn, addr, val, mask) \
do { \
uint32_t tmp_ = INPLL(pScrn, addr); \
tmp_ &= (mask); \
tmp_ |= ((val) & ~(mask)); \
OUTPLL(pScrn, addr, tmp_); \
} while (0)
#define OUTPAL_START(idx) \
do { \
if (IS_AVIVO_VARIANT) { \
OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
} else { \
OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
} \
} while (0)
#define OUTPAL_NEXT(r, g, b) \
do { \
if (IS_AVIVO_VARIANT) { \
OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 20) | ((g) << 10) | (b)); \
} else { \
OUTREG(RADEON_PALETTE_30_DATA, ((r) << 20) | ((g) << 10) | (b)); \
} \
} while (0)
#define OUTPAL(idx, r, g, b) \
do { \
OUTPAL_START((idx)); \
OUTPAL_NEXT((r), (g), (b)); \
} while (0)
#define INPAL_START(idx) \
do { \
if (IS_AVIVO_VARIANT) { \
OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
} else { \
OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
} \
} while (0)
#define INPAL_NEXT() \
do { \
if (IS_AVIVO_VARIANT) { \
INREG(AVIVO_DC_LUT_30_COLOR); \
} else { \
INREG(RADEON_PALETTE_30_DATA); \
} \
} while (0)
#define PAL_SELECT(idx) \
do { \
if (IS_AVIVO_VARIANT) { \
if (!idx) { \
OUTREG(AVIVO_DC_LUT_RW_SELECT, 0); \
} else { \
OUTREG(AVIVO_DC_LUT_RW_SELECT, 1); \
} \
} else { \
if (!idx) { \
OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
(uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL); \
} else { \
OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
RADEON_DAC2_PALETTE_ACC_CTL); \
} \
} \
} while (0)
#define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val)
#define INPCIE(pScrn, addr) RADEONINPCIE(pScrn, addr)
#define OUTPCIE(pScrn, addr, val) RADEONOUTPCIE(pScrn, addr, val)
#define INPCIE_P(pScrn, addr) R600INPCIE_PORT(pScrn, addr)
#define OUTPCIE_P(pScrn, addr, val) R600OUTPCIE_PORT(pScrn, addr, val)
#define BEGIN_ACCEL_RELOC(n, r) do { \
int _nqw = (n) + (info->cs ? (r) : 0); \
int _nqw = (n) + (r); \
BEGIN_ACCEL(_nqw); \
} while (0)
#define CHECK_OFFSET(pPix, mask, type) do { \
if (!info->cs) { \
uint32_t _pix_offset = radeonGetPixmapOffset(pPix); \
if ((_pix_offset & mask) != 0) \
RADEON_FALLBACK(("Bad %s offset 0x%x\n", type, (int)_pix_offset)); \
} \
} while(0)
#define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \
if (info->cs) { \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
OUT_ACCEL_REG((reg), (value)); \
OUT_RELOC(driver_priv->bo, (rd), (wd)); \
} else { \
uint32_t _pix_offset; \
_pix_offset = radeonGetPixmapOffset(pPix); \
OUT_ACCEL_REG((reg), _pix_offset | value); \
} \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
OUT_ACCEL_REG((reg), (value)); \
OUT_RELOC(driver_priv->bo, (rd), (wd)); \
} while(0)
#define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0)
#define EMIT_WRITE_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, 0, RADEON_GEM_DOMAIN_VRAM)
#define OUT_TEXTURE_REG(reg, offset, bo) do { \
if (info->cs) { \
OUT_ACCEL_REG((reg), (offset)); \
OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \
} else { \
OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \
OUT_ACCEL_REG((reg), (offset)); \
OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \
} while(0)
#define EMIT_COLORPITCH(reg, value, pPix) do { \
if (info->cs) { \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
OUT_ACCEL_REG((reg), value); \
OUT_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \
} else { \
OUT_ACCEL_REG((reg), value); \
} \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
OUT_ACCEL_REG((reg), value); \
OUT_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \
}while(0)
#endif

642
src/radeon_mm_i2c.c
View file

@ -1,642 +0,0 @@
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <math.h>
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
#include <X11/extensions/Xv.h>
#include "radeon_video.h"
#include "atipciids.h"
#include "xf86.h"
/* i2c stuff */
#include "xf86i2c.h"
#include "fi1236.h"
#include "msp3430.h"
#include "tda9885.h"
#include "uda1380.h"
#include "i2c_def.h"
static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv);
/* Wait for 10ms at the most for the I2C_GO register to drop. */
#define I2C_WAIT_FOR_GO() { \
int i2ctries = 0; \
RADEONWaitForIdleMMIO(pScrn); \
write_mem_barrier(); \
while (i2ctries < 10) { \
reg = INREG8(RADEON_I2C_CNTL_0+1); \
if (!(reg & (RADEON_I2C_GO >> 8))) \
break; \
if (reg & (RADEON_I2C_ABORT >> 8)) \
break; \
usleep(1000); \
i2ctries++; \
} \
}
/* Wait, and dump the status in the 'status' register. If we time out or
* receive an abort signal, halt/restart the I2C bus and leave _ABORT in the
* status register. */
#define I2C_WAIT_WITH_STATUS() { \
I2C_WAIT_FOR_GO() \
if (reg & ((RADEON_I2C_ABORT >> 8) | (RADEON_I2C_GO >> 8))) { \
RADEON_I2C_Halt(pScrn); \
status = RADEON_I2C_ABORT; \
} \
else \
status = RADEON_I2C_WaitForAck(pScrn, pPriv); \
}
/****************************************************************************
* I2C_WaitForAck (void) *
* *
* Function: polls the I2C status bits, waiting for an acknowledge or *
* an error condition. *
* Inputs: NONE *
* Outputs: I2C_DONE - the I2C transfer was completed *
* I2C_NACK - an NACK was received from the slave *
* I2C_HALT - a timeout condition has occured *
****************************************************************************/
static uint8_t RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
uint8_t retval = 0;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
long counter = 0;
usleep(1000);
while(1)
{
RADEONWaitForIdleMMIO(pScrn);
retval = INREG8(RADEON_I2C_CNTL_0);
if (retval & RADEON_I2C_HALT)
{
return (RADEON_I2C_HALT);
}
if (retval & RADEON_I2C_NACK)
{
return (RADEON_I2C_NACK);
}
if(retval & RADEON_I2C_DONE)
{
return RADEON_I2C_DONE;
}
counter++;
/* 50ms ought to be long enough. */
if(counter > 50)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Timeout condition on Radeon i2c bus\n");
return RADEON_I2C_HALT;
}
usleep(1000);
}
}
static void RADEON_I2C_Halt (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint8_t reg;
/* reset status flags */
RADEONWaitForIdleMMIO(pScrn);
reg = INREG8 (RADEON_I2C_CNTL_0 + 0) & ~(RADEON_I2C_DONE|RADEON_I2C_NACK|RADEON_I2C_HALT);
OUTREG8 (RADEON_I2C_CNTL_0 + 0, reg);
/* issue ABORT call */
RADEONWaitForIdleMMIO(pScrn);
reg = INREG8 (RADEON_I2C_CNTL_0 + 1) & 0xE7;
OUTREG8 (RADEON_I2C_CNTL_0 + 1, (reg |((RADEON_I2C_GO|RADEON_I2C_ABORT) >> 8)));
/* wait for GO bit to go low */
I2C_WAIT_FOR_GO();
}
static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
I2CByte *ReadBuffer, int nRead)
{
int loop, status;
uint32_t i2c_cntl_0, i2c_cntl_1;
uint8_t reg;
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr);
ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
status=RADEON_I2C_DONE;
RADEONWaitForIdleMMIO(pScrn);
if(nWrite>0){
/* RADEONWaitForFifo(pScrn, 4+nWrite); */
/* Clear the status bits of the I2C Controller */
OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
/* Write the address into the buffer first */
OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1));
/* Write Value into the buffer */
for (loop = 0; loop < nWrite; loop++)
{
OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]);
}
i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
nWrite | 0x100;
OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN;
OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
I2C_WAIT_WITH_STATUS();
if(status!=RADEON_I2C_DONE){
RADEON_I2C_Halt(pScrn);
return FALSE;
}
}
if(nRead > 0) {
RADEONWaitForFifo(pScrn, 4+nRead);
OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
/* Write the address into the buffer first */
OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1));
i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
nRead | 0x100;
OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE;
OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
I2C_WAIT_WITH_STATUS();
/* Write Value into the buffer */
for (loop = 0; loop < nRead; loop++)
{
RADEONWaitForFifo(pScrn, 1);
if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK))
{
ReadBuffer[loop]=0xff;
} else {
RADEONWaitForIdleMMIO(pScrn);
ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
}
}
}
if(status!=RADEON_I2C_DONE){
RADEON_I2C_Halt(pScrn);
return FALSE;
}
return TRUE;
}
static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
I2CByte *ReadBuffer, int nRead)
{
int loop, status;
uint32_t i2c_cntl_0, i2c_cntl_1;
uint8_t reg;
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr);
ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
status=RADEON_I2C_DONE;
RADEONWaitForIdleMMIO(pScrn);
if(nWrite>0){
/* RADEONWaitForFifo(pScrn, 4+nWrite); */
/* Clear the status bits of the I2C Controller */
OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
/* Write the address into the buffer first */
OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1));
/* Write Value into the buffer */
for (loop = 0; loop < nWrite; loop++)
{
OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]);
}
i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
nWrite | 0x010;
OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN;
OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
I2C_WAIT_WITH_STATUS();
if(status!=RADEON_I2C_DONE){
RADEON_I2C_Halt(pScrn);
return FALSE;
}
}
if(nRead > 0) {
RADEONWaitForFifo(pScrn, 4+nRead);
OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
/* Write the address into the buffer first */
OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1));
i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
nRead | 0x010;
OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE;
OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
I2C_WAIT_WITH_STATUS();
RADEONWaitForIdleMMIO(pScrn);
/* Write Value into the buffer */
for (loop = 0; loop < nRead; loop++)
{
if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK))
{
ReadBuffer[loop]=0xff;
} else {
ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
}
}
}
if(status!=RADEON_I2C_DONE){
RADEON_I2C_Halt(pScrn);
return FALSE;
}
return TRUE;
}
#if 0
static Bool RADEONProbeAddress(I2CBusPtr b, I2CSlaveAddr addr)
{
I2CByte a;
I2CDevRec d;
d.DevName = "Probing";
d.SlaveAddr = addr;
d.pI2CBus = b;
d.NextDev = NULL;
return I2C_WriteRead(&d, NULL, 0, &a, 1);
}
#endif
#define I2C_CLOCK_FREQ (60000.0)
const struct
{
char *name;
int type;
} RADEON_tuners[32] =
{
/* name ,index to tuner_parms table */
{"NO TUNER" , -1},
{"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
{"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
{"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216},
{"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246},
{"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216},
{"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
{"Philips FI1256 (or compatible)" , TUNER_TYPE_FI1256},
{"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
{"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216},
{"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246},
{"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216},
{"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
{"TEMIC-FN5AL" , TUNER_TYPE_TEMIC_FN5AL},
{"FQ1216ME/P" , TUNER_TYPE_FI1216},
{"FI1236W" , TUNER_TYPE_FI1236W},
{"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME},
/*{"Alps TSCxx" , -1},*/
{"Philips FM1236/F" , TUNER_TYPE_FI1236W},
{"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME},
{"UNKNOWN-19" , -1},
{"UNKNOWN-20" , -1},
{"UNKNOWN-21" , -1},
{"UNKNOWN-22" , -1},
{"UNKNOWN-23" , -1},
{"UNKNOWN-24" , -1},
{"UNKNOWN-25" , -1},
{"UNKNOWN-26" , -1},
{"UNKNOWN-27" , -1},
{"UNKNOWN-28" , -1},
{"Microtuner MT2032" , TUNER_TYPE_MT2032},
{"Microtuner MT2032" , TUNER_TYPE_MT2032},
{"UNKNOWN-31" , -1}
};
void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONWaitForFifo(pScrn, 2);
OUTREG8(RADEON_I2C_CNTL_1+2, ((RADEON_I2C_SEL | RADEON_I2C_EN)>>16));
OUTREG8(RADEON_I2C_CNTL_0+0, (RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST | RADEON_I2C_DRIVE_EN | RADEON_I2C_DRIVE_SEL));
}
void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
double nm;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPLLPtr pll = &(info->pll);
pPriv->i2c = NULL;
pPriv->fi1236 = NULL;
pPriv->msp3430 = NULL;
pPriv->tda9885 = NULL;
pPriv->uda1380 = NULL;
#if 0 /* put back on when saa7114 support is present */
pPriv->saa7114 = NULL;
#endif
/* Blacklist chipsets that lockup - these are usually older mobility chips */
switch(info->Chipset){
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M6, disabling multimedia i2c\n");
return;
case PCI_CHIP_RADEON_LW:
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M7, disabling multimedia i2c\n");
return;
/*case PCI_CHIP_RV250_If:
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon 9000 - skipping multimedia i2c initialization code.\n");
return;*/
case PCI_CHIP_RV370_5460:
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility X300, disabling multimedia i2c\n");
return;
}
/* no multimedia capabilities detected and no information was provided to substitute for it */
if(!info->MM_TABLE_valid &&
!(info->tunerType>=0))
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No video input capabilities detected and no information is provided - disabling multimedia i2c\n");
return;
}
if(pPriv->i2c!=NULL) return; /* for some reason we are asked to init it again.. Stop ! */
if(!xf86LoadSubModule(pScrn,"i2c"))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to initialize i2c bus\n");
pPriv->i2c = NULL;
return;
}
pPriv->i2c=CreateI2CBusRec();
pPriv->i2c->scrnIndex=pScrn->scrnIndex;
pPriv->i2c->BusName="Radeon multimedia bus";
pPriv->i2c->DriverPrivate.ptr=(pointer)pPriv;
switch(info->ChipFamily){
case CHIP_FAMILY_RV350:
case CHIP_FAMILY_R350:
case CHIP_FAMILY_R300:
case CHIP_FAMILY_RV250:
case CHIP_FAMILY_R200:
case CHIP_FAMILY_RV200:
pPriv->i2c->I2CWriteRead=R200_I2CWriteRead;
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using R200 i2c bus access method\n");
break;
default:
pPriv->i2c->I2CWriteRead=RADEONI2CWriteRead;
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using Radeon bus access method\n");
}
if(!I2CBusInit(pPriv->i2c))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Failed to register i2c bus\n");
}
#if 1
switch(info->ChipFamily){
case CHIP_FAMILY_RV200:
nm=(pll->reference_freq * 40000.0)/(1.0*I2C_CLOCK_FREQ);
break;
case CHIP_FAMILY_R300:
case CHIP_FAMILY_R200:
if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){
nm=(pll->reference_freq * 40000.0)/(4.0*I2C_CLOCK_FREQ);
break;
}
default:
nm=(pll->reference_freq * 10000.0)/(4.0*I2C_CLOCK_FREQ);
}
#else
nm=(pll->xclk * 40000.0)/(1.0*I2C_CLOCK_FREQ);
#endif
for(pPriv->radeon_N=1; pPriv->radeon_N<255; pPriv->radeon_N++)
if((pPriv->radeon_N * (pPriv->radeon_N-1)) > nm)break;
pPriv->radeon_M=pPriv->radeon_N-1;
pPriv->radeon_i2c_timing=2*pPriv->radeon_N;
#if 0
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref=%d M=0x%02x N=0x%02x timing=0x%02x\n", pll->reference_freq, pPriv->radeon_M, pPriv->radeon_N, pPriv->radeon_i2c_timing);
pPriv->radeon_M=0x32;
pPriv->radeon_N=0x33;
pPriv->radeon_i2c_timing=2*pPriv->radeon_N;
#endif
RADEONResetI2C(pScrn, pPriv);
#if 0 /* I don't know whether standalone boards are supported with Radeons */
/* looks like none of them have AMC connectors anyway */
if(!info->MM_TABLE_valid)RADEON_read_eeprom(pPriv);
#endif
if(!xf86LoadSubModule(pScrn,"fi1236"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize fi1236 driver\n");
}
else
{
if(pPriv->fi1236 == NULL)
{
pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_1);
}
if(pPriv->fi1236 == NULL)
{
pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_2);
}
}
if(pPriv->fi1236 != NULL)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected %s device at 0x%02x\n",
RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].name,
FI1236_ADDR(pPriv->fi1236));
if(info->MM_TABLE_valid)xf86_FI1236_set_tuner_type(pPriv->fi1236, RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type);
else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE not found (standalone board ?), forcing tuner type to NTSC\n");
xf86_FI1236_set_tuner_type(pPriv->fi1236, TUNER_TYPE_FI1236);
}
}
if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){
if(!xf86LoadSubModule(pScrn,"tda9885"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n");
}
else
{
if(pPriv->tda9885 == NULL)
{
pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1);
}
if(pPriv->tda9885 == NULL)
{
pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2);
}
if(pPriv->tda9885 != NULL)
{
RADEON_TDA9885_Init(pPriv);
}
}
}
if(info->MM_TABLE_valid && ((RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FM1216ME)
|| (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FI1236W)))
{
if(!xf86LoadSubModule(pScrn,"tda9885"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n");
}
else
{
if(pPriv->tda9885 == NULL)
{
pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1);
}
if(pPriv->tda9885 == NULL)
{
pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2);
}
if(pPriv->tda9885 != NULL)
{
RADEON_TDA9885_Init(pPriv);
pPriv->fi1236->afc_source = (void*)pPriv->tda9885;
}
}
}
if(!xf86LoadSubModule(pScrn,"uda1380"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize uda1380 driver\n");
}
else
{
if(pPriv->uda1380 == NULL)
{
pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_1);
}
if(pPriv->uda1380 == NULL)
{
pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_2);
}
if(pPriv->uda1380 != NULL)
{
xf86_uda1380_init(pPriv->uda1380);
}
}
if(!xf86LoadSubModule(pScrn,"msp3430"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize msp3430 driver\n");
}
else
{
if(pPriv->msp3430 == NULL)
{
pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_1);
}
if(pPriv->msp3430 == NULL)
{
pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_2);
}
#if 0 /* this would confuse bt829 with msp3430 */
if(pPriv->msp3430 == NULL)
{
pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_3);
}
#endif
}
if(pPriv->msp3430 != NULL)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected MSP3430 at 0x%02x\n",
MSP3430_ADDR(pPriv->msp3430));
pPriv->msp3430->standard = MSP3430_NTSC;
pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
xf86_ResetMSP3430(pPriv->msp3430);
xf86_InitMSP3430(pPriv->msp3430);
xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume));
}
#if 0 /* put this back when saa7114 driver is ready */
if(!xf86LoadSubModule(pScrn,"saa7114"))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize saa7114 driver\n");
}
else
{
if(pPriv->saa7114 == NULL)
{
pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_1);
}
if(pPriv->saa7114 == NULL)
{
pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_2);
}
}
if(pPriv->saa7114 != NULL)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected SAA7114 at 0x%02x\n",
pPriv->saa7114->d.SlaveAddr);
xf86_InitSAA7114(pPriv->saa7114);
}
#endif
}
static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv)
{
TDA9885Ptr t=pPriv->tda9885;
t->sound_trap=0;
t->auto_mute_fm=1; /* ? */
t->carrier_mode=0; /* ??? */
t->modulation=2; /* negative FM */
t->forced_mute_audio=0;
t->port1=1;
t->port2=1;
t->top_adjustment=0x10;
t->deemphasis=1;
t->audio_gain=0;
t->minimum_gain=0;
t->gating=0;
t->vif_agc=1; /* set to 1 ? - depends on design */
t->gating=0;
}

542
src/radeon_modes.c
View file

@ -1,542 +0,0 @@
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
*/
#include <string.h>
#include <stdio.h>
#include "xf86.h"
/* Driver data structures */
#include "randrstr.h"
#include "radeon_probe.h"
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_version.h"
#include "radeon_atombios.h"
#include "xf86Modes.h"
/* DDC support */
#include "xf86DDC.h"
#include <randrstr.h>
void RADEONSetPitch (ScrnInfoPtr pScrn)
{
int dummy = pScrn->virtualX;
RADEONInfoPtr info = RADEONPTR(pScrn);
int pitch_mask = 0;
int align_large;
align_large = info->allowColorTiling || IS_AVIVO_VARIANT;
/* FIXME: May need to validate line pitch here */
if (info->ChipFamily < CHIP_FAMILY_R600) {
switch (pScrn->depth / 8) {
case 1: pitch_mask = align_large ? 256 : 128;
break;
case 2: pitch_mask = align_large ? 128 : 32;
break;
case 3:
case 4: pitch_mask = align_large ? 64 : 16;
break;
}
} else
pitch_mask = 256; /* r6xx/r7xx need 256B alignment for accel */
dummy = RADEON_ALIGN(pScrn->virtualX, pitch_mask);
pScrn->displayWidth = dummy;
info->CurrentLayout.displayWidth = pScrn->displayWidth;
}
static DisplayModePtr
RADEONTVModes(xf86OutputPtr output)
{
DisplayModePtr new = NULL;
/* just a place holder */
new = xf86CVTMode(800, 600, 60.00, FALSE, FALSE);
new->type = M_T_DRIVER | M_T_PREFERRED;
return new;
}
static DisplayModePtr
RADEONATOMTVModes(xf86OutputPtr output)
{
DisplayModePtr last = NULL;
DisplayModePtr new = NULL;
DisplayModePtr first = NULL;
int i;
/* Add some common sizes */
int widths[5] = {640, 720, 800, 848, 1024};
int heights[5] = {480, 480, 600, 480, 768};
for (i = 0; i < 5; i++) {
new = xf86CVTMode(widths[i], heights[i], 60.0, FALSE, FALSE);
new->type = M_T_DRIVER;
new->next = NULL;
new->prev = last;
if (last) last->next = new;
last = new;
if (!first) first = new;
}
if (last) {
last->next = NULL; //first;
first->prev = NULL; //last;
}
return first;
}
/* This is used only when no mode is specified for FP and no ddc is
* available. We force it to native mode, if possible.
*/
static DisplayModePtr RADEONFPNativeMode(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
radeon_native_mode_ptr native_mode = &radeon_output->native_mode;
DisplayModePtr new = NULL;
char stmp[32];
if (native_mode->PanelXRes != 0 &&
native_mode->PanelYRes != 0 &&
native_mode->DotClock != 0) {
new = xnfcalloc(1, sizeof (DisplayModeRec));
sprintf(stmp, "%dx%d", native_mode->PanelXRes, native_mode->PanelYRes);
new->name = xnfalloc(strlen(stmp) + 1);
strcpy(new->name, stmp);
new->HDisplay = native_mode->PanelXRes;
new->VDisplay = native_mode->PanelYRes;
new->HTotal = new->HDisplay + native_mode->HBlank;
new->HSyncStart = new->HDisplay + native_mode->HOverPlus;
new->HSyncEnd = new->HSyncStart + native_mode->HSyncWidth;
new->VTotal = new->VDisplay + native_mode->VBlank;
new->VSyncStart = new->VDisplay + native_mode->VOverPlus;
new->VSyncEnd = new->VSyncStart + native_mode->VSyncWidth;
new->Clock = native_mode->DotClock;
new->Flags = native_mode->Flags;
if (new) {
new->type = M_T_DRIVER | M_T_PREFERRED;
new->next = NULL;
new->prev = NULL;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode: %dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
} else if (native_mode->PanelXRes != 0 &&
native_mode->PanelYRes != 0) {
new = xf86CVTMode(native_mode->PanelXRes, native_mode->PanelYRes, 60.0, TRUE, FALSE);
if (new) {
new->type = M_T_DRIVER | M_T_PREFERRED;
new->next = NULL;
new->prev = NULL;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode using CVT: %dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
}
return new;
}
#if defined(__powerpc__)
/* Apple eMacs need special modes for the internal CRT, e.g.,
* Modeline "640x480" 62.12 640 680 752 864 480 481 484 521 +HSync +Vsync
* Modeline "800x600" 76.84 800 848 936 1072 600 601 604 640 +HSync +Vsync
* Modeline "1024x768" 99.07 1024 1088 1200 1376 768 769 772 809 +HSync +Vsync
* Modeline "1152x864" 112.36 1152 1224 1352 1552 864 865 868 905 +HSync +Vsync
* Modeline "1280x960" 124.54 1280 1368 1504 1728 960 961 964 1001 +HSync +Vsync
*/
static DisplayModePtr RADEONeMacModes(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
DisplayModePtr last=NULL, new=NULL, first=NULL;
int i, *modep;
static const char *modenames[5] = {
"640x480", "800x600", "1024x768", "1152x864", "1280x960"
};
static int modes[9*5] = {
62120, 640, 680, 752, 864, 480, 481, 484, 521,
76840, 800, 848, 936, 1072, 600, 601, 604, 640,
99070, 1024, 1088, 1200, 1376, 768, 769, 772, 809,
112360, 1152, 1224, 1352, 1552, 864, 865, 868, 905,
124540, 1280, 1368, 1504, 1728, 960, 961, 964, 1001
};
modep = modes;
for (i=0; i<5; i++) {
new = xnfcalloc(1, sizeof (DisplayModeRec));
if (new) {
new->name = xnfalloc(strlen(modenames[i]) + 1);
strcpy(new->name, modenames[i]);
new->Clock = *modep++;
new->HDisplay = *modep++;
new->HSyncStart = *modep++;
new->HSyncEnd = *modep++;
new->HTotal = *modep++;
new->VDisplay = *modep++;
new->VSyncStart = *modep++;
new->VSyncEnd = *modep++;
new->VTotal = *modep++;
new->Flags = 0;
new->type = M_T_DRIVER;
if (i==2)
new->type |= M_T_PREFERRED;
new->next = NULL;
new->prev = last;
if (last) last->next = new;
last = new;
if (!first) first = new;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added eMac mode %s\n", modenames[i]);
}
}
return first;
}
#endif
/* this function is basically a hack to add the screen modes */
static void RADEONAddScreenModes(xf86OutputPtr output, DisplayModePtr *modeList)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
radeon_native_mode_ptr native_mode = &radeon_output->native_mode;
DisplayModePtr last = NULL;
DisplayModePtr new = NULL;
DisplayModePtr first = NULL;
int count = 0;
int i, width, height;
char **ppModeName = pScrn->display->modes;
first = last = *modeList;
/* We have a flat panel connected to the primary display, and we
* don't have any DDC info.
*/
for (i = 0; ppModeName[i] != NULL; i++) {
if (sscanf(ppModeName[i], "%dx%d", &width, &height) != 2) continue;
if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
/* already added the native mode */
if (width == native_mode->PanelXRes && height == native_mode->PanelYRes)
continue;
/* Note: We allow all non-standard modes as long as they do not
* exceed the native resolution of the panel. Since these modes
* need the internal RMX unit in the video chips (and there is
* only one per card), this will only apply to the primary head.
*/
if (width < 320 || width > native_mode->PanelXRes ||
height < 200 || height > native_mode->PanelYRes) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Mode %s is out of range.\n", ppModeName[i]);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Valid FP modes must be between 320x200-%dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
continue;
}
}
new = xf86CVTMode(width, height, 60.0, FALSE, FALSE);
new->type |= M_T_USERDEF;
new->next = NULL;
new->prev = last;
if (last) last->next = new;
last = new;
if (!first) first = new;
count++;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Adding Screen mode: %s\n", new->name);
}
/* Close the doubly-linked mode list, if we found any usable modes */
if (last) {
last->next = NULL; //first;
first->prev = NULL; //last;
*modeList = first;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Total number of valid Screen mode(s) added: %d\n", count);
}
/* BIOS may not have right panel size, we search through all supported
* DDC modes looking for the maximum panel size.
*/
static void
RADEONUpdatePanelSize(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
radeon_native_mode_ptr native_mode = &radeon_output->native_mode;
int j;
xf86MonPtr ddc = output->MonInfo;
DisplayModePtr p;
// update output's native mode
if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
if (radeon_encoder) {
radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv;
if (lvds)
radeon_output->native_mode = lvds->native_mode;
}
}
// crtc should handle?
if ((info->UseBiosDividers && native_mode->DotClock != 0) || (ddc == NULL))
return;
/* Go thru detailed timing table first */
for (j = 0; j < 4; j++) {
if (ddc->det_mon[j].type == 0) {
struct detailed_timings *d_timings =
&ddc->det_mon[j].section.d_timings;
int match = 0;
/* If we didn't get a panel clock or guessed one, try to match the
* mode with the panel size. We do that because we _need_ a panel
* clock, or ValidateFPModes will fail, even when UseBiosDividers
* is set.
*/
if (native_mode->DotClock == 0 &&
native_mode->PanelXRes == d_timings->h_active &&
native_mode->PanelYRes == d_timings->v_active)
match = 1;
/* If we don't have a BIOS provided panel data with fixed dividers,
* check for a larger panel size
*/
if (native_mode->PanelXRes < d_timings->h_active &&
native_mode->PanelYRes < d_timings->v_active &&
!info->UseBiosDividers)
match = 1;
if (match) {
native_mode->PanelXRes = d_timings->h_active;
native_mode->PanelYRes = d_timings->v_active;
native_mode->DotClock = d_timings->clock / 1000;
native_mode->HOverPlus = d_timings->h_sync_off;
native_mode->HSyncWidth = d_timings->h_sync_width;
native_mode->HBlank = d_timings->h_blanking;
native_mode->VOverPlus = d_timings->v_sync_off;
native_mode->VSyncWidth = d_timings->v_sync_width;
native_mode->VBlank = d_timings->v_blanking;
native_mode->Flags = (d_timings->interlaced ? V_INTERLACE : 0);
switch (d_timings->misc) {
case 0: native_mode->Flags |= V_NHSYNC | V_NVSYNC; break;
case 1: native_mode->Flags |= V_PHSYNC | V_NVSYNC; break;
case 2: native_mode->Flags |= V_NHSYNC | V_PVSYNC; break;
case 3: native_mode->Flags |= V_PHSYNC | V_PVSYNC; break;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
}
}
}
if (info->UseBiosDividers && native_mode->DotClock != 0)
return;
/* Search thru standard VESA modes from EDID */
for (j = 0; j < 8; j++) {
if ((native_mode->PanelXRes < ddc->timings2[j].hsize) &&
(native_mode->PanelYRes < ddc->timings2[j].vsize)) {
for (p = pScrn->monitor->Modes; p; p = p->next) {
if ((ddc->timings2[j].hsize == p->HDisplay) &&
(ddc->timings2[j].vsize == p->VDisplay)) {
float refresh =
(float)p->Clock * 1000.0 / p->HTotal / p->VTotal;
if (abs((float)ddc->timings2[j].refresh - refresh) < 1.0) {
/* Is this good enough? */
native_mode->PanelXRes = ddc->timings2[j].hsize;
native_mode->PanelYRes = ddc->timings2[j].vsize;
native_mode->HBlank = p->HTotal - p->HDisplay;
native_mode->HOverPlus = p->HSyncStart - p->HDisplay;
native_mode->HSyncWidth = p->HSyncEnd - p->HSyncStart;
native_mode->VBlank = p->VTotal - p->VDisplay;
native_mode->VOverPlus = p->VSyncStart - p->VDisplay;
native_mode->VSyncWidth = p->VSyncEnd - p->VSyncStart;
native_mode->DotClock = p->Clock;
native_mode->Flags = p->Flags;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
}
}
}
}
}
}
static void
radeon_add_common_modes(xf86OutputPtr output, DisplayModePtr modes)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
radeon_native_mode_ptr native_mode = &radeon_output->native_mode;
DisplayModePtr last = NULL;
DisplayModePtr new = NULL;
DisplayModePtr first = NULL;
int i;
/* Add some common sizes */
int widths[15] = {640, 800, 1024, 1152, 1280, 1280, 1280, 1280, 1280, 1440, 1400, 1680, 1600, 1920, 1920};
int heights[15] = {480, 600, 768, 768, 720, 800, 854, 960, 1024, 900, 1050, 1050, 1200, 1080, 1200};
for (i = 0; i < 15; i++) {
if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
/* already added the native mode */
if (widths[i] == native_mode->PanelXRes && heights[i] == native_mode->PanelYRes)
continue;
/* Note: We allow all non-standard modes as long as they do not
* exceed the native resolution of the panel. Since these modes
* need the internal RMX unit in the video chips (and there is
* only one per card), this will only apply to the primary head.
*/
if (widths[i] < 320 || widths[i] > native_mode->PanelXRes ||
heights[i] < 200 || heights[i] > native_mode->PanelYRes)
continue;
}
new = xf86CVTMode(widths[i], heights[i], 60.0, FALSE, FALSE);
new->type = M_T_DRIVER;
new->next = NULL;
new->prev = last;
if (last) last->next = new;
last = new;
if (!first) first = new;
}
if (last) {
last->next = NULL; //first;
first->prev = NULL; //last;
}
xf86ModesAdd(modes, first);
}
DisplayModePtr
RADEONProbeOutputModes(xf86OutputPtr output)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
DisplayModePtr modes = NULL;
AtomBiosArgRec atomBiosArg;
AtomBiosResult atomBiosResult;
if (output->status == XF86OutputStatusConnected) {
if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
if (IS_AVIVO_VARIANT)
modes = RADEONATOMTVModes(output);
else
modes = RADEONTVModes(output);
} else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) {
atomBiosResult = RHDAtomBiosFunc(pScrn, info->atomBIOS,
ATOMBIOS_GET_CV_MODES, &atomBiosArg);
if (atomBiosResult == ATOM_SUCCESS) {
modes = atomBiosArg.modes;
}
} else {
if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))
RADEONUpdatePanelSize(output);
if (output->MonInfo)
modes = xf86OutputGetEDIDModes (output);
#if defined(__powerpc__)
if ((info->MacModel == RADEON_MAC_EMAC) &&
(radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) &&
(modes == NULL))
modes = RADEONeMacModes(output);
#endif
if (modes == NULL) {
if ((radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) && info->IsAtomBios) {
atomBiosResult = RHDAtomBiosFunc(pScrn,
info->atomBIOS,
ATOMBIOS_GET_PANEL_EDID, &atomBiosArg);
if (atomBiosResult == ATOM_SUCCESS) {
output->MonInfo = xf86InterpretEDID(pScrn->scrnIndex,
atomBiosArg.EDIDBlock);
modes = xf86OutputGetEDIDModes(output);
}
}
if (modes == NULL) {
if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT))
modes = RADEONFPNativeMode(output);
/* add the screen modes */
if (modes == NULL)
RADEONAddScreenModes(output, &modes);
}
}
}
}
if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT))
radeon_add_common_modes(output, modes);
return modes;
}

3193
src/radeon_output.c
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File diff suppressed because it is too large Load diff

886
src/radeon_pm.c
View file

@ -1,886 +0,0 @@
/*
* Copyright 2009 Advanced Micro Devices, Inc.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR
* AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author: Alex Deucher <alexander.deucher@amd.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/* Driver data structures */
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_atombios.h"
#include "ati_pciids_gen.h"
/* 10 khz */
static uint32_t calc_eng_mem_clock(ScrnInfoPtr pScrn,
uint32_t req_clock,
int ref_div,
int *fb_div,
int *post_div)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPLLPtr pll = &info->pll;
if (req_clock < 15000) {
*post_div = 8;
req_clock *= 8;
} else if (req_clock < 30000) {
*post_div = 4;
req_clock *= 4;
} else if (req_clock < 60000) {
*post_div = 2;
req_clock *= 2;
} else
*post_div = 1;
req_clock *= ref_div;
req_clock += pll->reference_freq;
req_clock /= (2 * pll->reference_freq);
*fb_div = req_clock & 0xff;
req_clock = (req_clock & 0xffff) << 1;
req_clock *= pll->reference_freq;
req_clock /= ref_div;
req_clock /= *post_div;
return req_clock;
}
static void
RADEONSetEngineClock(ScrnInfoPtr pScrn, uint32_t eng_clock)
{
uint32_t tmp;
int ref_div, fb_div, post_div;
RADEONWaitForIdleMMIO(pScrn);
tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
ref_div = tmp & RADEON_M_SPLL_REF_DIV_MASK;
eng_clock = calc_eng_mem_clock(pScrn, eng_clock, ref_div, &fb_div, &post_div);
tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
tmp &= ~RADEON_DONT_USE_XTALIN;
OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
usleep(10);
tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
tmp |= RADEON_SPLL_SLEEP;
OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
usleep(2);
tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
tmp |= RADEON_SPLL_RESET;
OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
usleep(200);
tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
OUTPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV, tmp);
/* XXX: verify on different asics */
tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
tmp &= ~RADEON_SPLL_PVG_MASK;
if ((eng_clock * post_div) >= 90000)
tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
else
tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
tmp &= ~RADEON_SPLL_SLEEP;
OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
usleep(2);
tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
tmp &= ~RADEON_SPLL_RESET;
OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
usleep(200);
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
switch (post_div) {
case 1:
default:
tmp |= 1;
break;
case 2:
tmp |= 2;
break;
case 4:
tmp |= 3;
break;
case 8:
tmp |= 4;
break;
}
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
usleep(20);
tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
tmp |= RADEON_DONT_USE_XTALIN;
OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
usleep(10);
}
static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t tmp;
if (enable) {
if (!pRADEONEnt->HasCRTC2) {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) >
RADEON_CFG_ATI_REV_A13) {
tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
}
tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
RADEON_SCLK_FORCE_TDM);
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
} else if (IS_R300_VARIANT) {
if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
(info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
tmp |= RADEON_DYN_STOP_LAT_MASK;
tmp |= RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_VIP;
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp &= ~RADEON_SCLK_MORE_FORCEON;
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
R300_DVOCLK_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
R300_PIXCLK_DVO_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
tmp = INPLL(pScrn, R300_SCLK_CNTL2);
tmp &= ~(R300_SCLK_FORCE_TCL |
R300_SCLK_FORCE_GA |
R300_SCLK_FORCE_CBA);
tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
R300_SCLK_GA_MAX_DYN_STOP_LAT |
R300_SCLK_CBA_MAX_DYN_STOP_LAT);
OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
tmp |= RADEON_DYN_STOP_LAT_MASK;
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp &= ~RADEON_SCLK_MORE_FORCEON;
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
R300_DVOCLK_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
R300_PIXCLK_DVO_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_MCLK_MISC);
tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
RADEON_IO_MCLK_DYN_ENABLE);
OUTPLL(pScrn, RADEON_MCLK_MISC, tmp);
tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
tmp |= (RADEON_FORCEON_MCLKA |
RADEON_FORCEON_MCLKB);
tmp &= ~(RADEON_FORCEON_YCLKA |
RADEON_FORCEON_YCLKB |
RADEON_FORCEON_MC);
/* Some releases of vbios have set DISABLE_MC_MCLKA
and DISABLE_MC_MCLKB bits in the vbios table. Setting these
bits will cause H/W hang when reading video memory with dynamic clocking
enabled. */
if ((tmp & R300_DISABLE_MC_MCLKA) &&
(tmp & R300_DISABLE_MC_MCLKB)) {
/* If both bits are set, then check the active channels */
tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
if (info->RamWidth == 64) {
if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
tmp &= ~R300_DISABLE_MC_MCLKB;
else
tmp &= ~R300_DISABLE_MC_MCLKA;
} else {
tmp &= ~(R300_DISABLE_MC_MCLKA |
R300_DISABLE_MC_MCLKB);
}
}
OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
} else {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp &= ~(R300_SCLK_FORCE_VAP);
tmp |= RADEON_SCLK_FORCE_CP;
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
usleep(15000);
tmp = INPLL(pScrn, R300_SCLK_CNTL2);
tmp &= ~(R300_SCLK_FORCE_TCL |
R300_SCLK_FORCE_GA |
R300_SCLK_FORCE_CBA);
OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
}
} else {
tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL);
tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
RADEON_DISP_DYN_STOP_LAT_MASK |
RADEON_DYN_STOP_MODE_MASK);
tmp |= (RADEON_ENGIN_DYNCLK_MODE |
(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp);
usleep(15000);
tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
tmp |= RADEON_SCLK_DYN_START_CNTL;
OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
usleep(15000);
/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
to lockup randomly, leave them as set by BIOS.
*/
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
/*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
tmp &= ~RADEON_SCLK_FORCEON_MASK;
/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
if (((info->ChipFamily == CHIP_FAMILY_RV250) &&
((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
RADEON_CFG_ATI_REV_A13)) ||
((info->ChipFamily == CHIP_FAMILY_RV100) &&
((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
RADEON_CFG_ATI_REV_A13))) {
tmp |= RADEON_SCLK_FORCE_CP;
tmp |= RADEON_SCLK_FORCE_VIP;
}
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
if ((info->ChipFamily == CHIP_FAMILY_RV200) ||
(info->ChipFamily == CHIP_FAMILY_RV250) ||
(info->ChipFamily == CHIP_FAMILY_RV280)) {
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp &= ~RADEON_SCLK_MORE_FORCEON;
/* RV200::A11 A12 RV250::A11 A12 */
if (((info->ChipFamily == CHIP_FAMILY_RV200) ||
(info->ChipFamily == CHIP_FAMILY_RV250)) &&
((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
RADEON_CFG_ATI_REV_A13)) {
tmp |= RADEON_SCLK_MORE_FORCEON;
}
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
usleep(15000);
}
/* RV200::A11 A12, RV250::A11 A12 */
if (((info->ChipFamily == CHIP_FAMILY_RV200) ||
(info->ChipFamily == CHIP_FAMILY_RV250)) &&
((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
RADEON_CFG_ATI_REV_A13)) {
tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL);
tmp |= RADEON_TCL_BYPASS_DISABLE;
OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp);
}
usleep(15000);
/*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
usleep(15000);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
usleep(15000);
}
} else {
/* Turn everything OFF (ForceON to everything)*/
if ( !pRADEONEnt->HasCRTC2 ) {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
RADEON_SCLK_FORCE_RB);
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
} else if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
(info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp |= RADEON_SCLK_MORE_FORCEON;
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
R300_DVOCLK_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
R300_PIXCLK_DVO_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
/* for RV350/M10, no delays are required. */
tmp = INPLL(pScrn, R300_SCLK_CNTL2);
tmp |= (R300_SCLK_FORCE_TCL |
R300_SCLK_FORCE_GA |
R300_SCLK_FORCE_CBA);
OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp |= RADEON_SCLK_MORE_FORCEON;
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
tmp |= (RADEON_FORCEON_MCLKA |
RADEON_FORCEON_MCLKB |
RADEON_FORCEON_YCLKA |
RADEON_FORCEON_YCLKB |
RADEON_FORCEON_MC);
OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
R300_DVOCLK_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
R300_PIXCLK_DVO_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
tmp |= RADEON_SCLK_FORCE_SE;
if ( !pRADEONEnt->HasCRTC2 ) {
tmp |= ( RADEON_SCLK_FORCE_RB |
RADEON_SCLK_FORCE_TDM |
RADEON_SCLK_FORCE_TAM |
RADEON_SCLK_FORCE_PB |
RADEON_SCLK_FORCE_RE |
RADEON_SCLK_FORCE_VIP |
RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_TOP |
RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_DISP2 |
RADEON_SCLK_FORCE_HDP );
} else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350)) {
tmp |= ( RADEON_SCLK_FORCE_HDP |
RADEON_SCLK_FORCE_DISP1 |
RADEON_SCLK_FORCE_DISP2 |
RADEON_SCLK_FORCE_TOP |
RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP);
}
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
usleep(16000);
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350)) {
tmp = INPLL(pScrn, R300_SCLK_CNTL2);
tmp |= ( R300_SCLK_FORCE_TCL |
R300_SCLK_FORCE_GA |
R300_SCLK_FORCE_CBA);
OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
usleep(16000);
}
if (info->IsIGP) {
tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
tmp &= ~(RADEON_FORCEON_MCLKA |
RADEON_FORCEON_YCLKA);
OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
usleep(16000);
}
if ((info->ChipFamily == CHIP_FAMILY_RV200) ||
(info->ChipFamily == CHIP_FAMILY_RV250) ||
(info->ChipFamily == CHIP_FAMILY_RV280)) {
tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
tmp |= RADEON_SCLK_MORE_FORCEON;
OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
usleep(16000);
}
tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
RADEON_PIXCLK_GV_ALWAYS_ONb |
RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
usleep(16000);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
RADEON_PIXCLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
}
}
}
static void RADEONPMQuirks(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t tmp;
RADEONWaitForIdleMMIO(pScrn);
if (info->ChipFamily < CHIP_FAMILY_RV515) {
tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
if (IS_R300_VARIANT || IS_RV100_VARIANT)
tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
if ((info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280))
tmp |= RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
if ((info->ChipFamily == CHIP_FAMILY_RV350) || (info->ChipFamily == CHIP_FAMILY_RV380))
tmp |= R300_SCLK_FORCE_VAP;
if (info->ChipFamily == CHIP_FAMILY_R420)
tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
} else if (info->ChipFamily < CHIP_FAMILY_R600) {
tmp = INPLL(pScrn, AVIVO_CP_DYN_CNTL);
tmp |= AVIVO_CP_FORCEON;
OUTPLL(pScrn, AVIVO_CP_DYN_CNTL, tmp);
tmp = INPLL(pScrn, AVIVO_E2_DYN_CNTL);
tmp |= AVIVO_E2_FORCEON;
OUTPLL(pScrn, AVIVO_E2_DYN_CNTL, tmp);
tmp = INPLL(pScrn, AVIVO_IDCT_DYN_CNTL);
tmp |= AVIVO_IDCT_FORCEON;
OUTPLL(pScrn, AVIVO_IDCT_DYN_CNTL, tmp);
}
}
static void
RADEONSetPCIELanes(ScrnInfoPtr pScrn, int lanes)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t link_width_cntl, mask, target_reg;
if (info->IsIGP)
return;
/* don't change lanes on multi-gpu cards for now */
if ((info->Chipset == PCI_CHIP_RV770_9441) ||
(info->Chipset == PCI_CHIP_RV770_9443) ||
(info->Chipset == PCI_CHIP_RV770_944B) ||
(info->Chipset == PCI_CHIP_RV670_9506) ||
(info->Chipset == PCI_CHIP_RV670_9509) ||
(info->Chipset == PCI_CHIP_RV670_950F))
return;
RADEONWaitForIdleMMIO(pScrn);
switch (lanes) {
case 0:
mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
break;
case 1:
mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
break;
case 2:
mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
break;
case 4:
mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
break;
case 8:
mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
break;
case 12:
mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
break;
case 16:
default:
mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
break;
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
link_width_cntl = INPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
return;
link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
RADEON_PCIE_LC_RECONFIG_NOW |
R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE |
R600_PCIE_LC_SHORT_RECONFIG_EN |
R600_PCIE_LC_RENEGOTIATE_EN);
link_width_cntl |= mask;
#if 0
/* some northbridges can renegotiate the link rather than requiring
* a complete re-config.
* e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
*/
if (northbridge can renegotiate)
link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN;
else
#endif
link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);
if (info->ChipFamily >= CHIP_FAMILY_RV770)
target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
else
target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
/* wait for lane set to complete */
link_width_cntl = INREG(target_reg);
while (link_width_cntl == 0xffffffff)
link_width_cntl = INREG(target_reg);
} else {
link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
return;
link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
RADEON_PCIE_LC_RECONFIG_NOW |
RADEON_PCIE_LC_RECONFIG_LATER |
RADEON_PCIE_LC_SHORT_RECONFIG_EN);
link_width_cntl |= mask;
OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);
/* wait for lane set to complete */
link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
while (link_width_cntl == 0xffffffff)
link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
}
}
static void
RADEONSetClockGating(ScrnInfoPtr pScrn, Bool enable)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONWaitForIdleMMIO(pScrn);
if (info->ChipFamily >= CHIP_FAMILY_R600)
atombios_static_pwrmgt_setup(pScrn, enable);
else {
if (info->IsAtomBios) {
atombios_static_pwrmgt_setup(pScrn, enable);
atombios_clk_gating_setup(pScrn, enable);
} else if (info->IsMobility)
LegacySetClockGating(pScrn, enable);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Gating %sabled\n",
enable ? "En" : "Dis");
}
static void RADEONSetStaticPowerMode(ScrnInfoPtr pScrn, RADEONPMType type)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
int i;
for (i = 0; i < info->pm.num_modes; i++) {
if (info->pm.mode[i].type == type)
break;
}
if (i == info->pm.num_modes)
return;
if (i == info->pm.current_mode)
return;
RADEONWaitForIdleMMIO(pScrn);
if (info->IsAtomBios)
atombios_set_engine_clock(pScrn, info->pm.mode[i].sclk);
else
RADEONSetEngineClock(pScrn, info->pm.mode[i].sclk);
if (info->cardType == CARD_PCIE)
RADEONSetPCIELanes(pScrn, info->pm.mode[i].pcie_lanes);
info->pm.current_mode = i;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Power Mode Switch\n");
}
void RADEONPMInit(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
if (xf86ReturnOptValBool(info->Options, OPTION_CLOCK_GATING, FALSE)) {
info->pm.clock_gating_enabled = TRUE;
RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled);
} else
info->pm.clock_gating_enabled = FALSE;
info->pm.mode[0].type = POWER_DEFAULT;
info->pm.mode[0].sclk = (uint32_t)info->sclk * 100; /* 10 khz */
info->pm.mode[0].mclk = (uint32_t)info->mclk * 100; /* 10 khz */
info->pm.mode[0].pcie_lanes = 16; /* XXX: read back current lane config */
info->pm.current_mode = 0;
info->pm.num_modes = 1;
if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_PM, FALSE)) {
info->pm.dynamic_mode_enabled = TRUE;
info->pm.mode[1].type = POWER_LOW;
info->pm.mode[1].sclk = info->pm.mode[0].sclk / 4;
info->pm.mode[1].mclk = info->pm.mode[0].mclk / 4;
info->pm.mode[1].pcie_lanes = 1;
info->pm.mode[2].type = POWER_HIGH;
info->pm.mode[2].sclk = info->pm.mode[0].sclk;
info->pm.mode[2].mclk = info->pm.mode[0].mclk;
info->pm.mode[2].pcie_lanes = 16;
info->pm.num_modes += 2;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Enabled\n");
} else {
info->pm.dynamic_mode_enabled = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Disabled\n");
}
if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_LOW_POWER, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Force Low Power Mode Enabled\n");
info->pm.force_low_power_enabled = TRUE;
if (info->pm.dynamic_mode_enabled) {
info->pm.mode[2].type = POWER_HIGH;
info->pm.mode[2].sclk = info->pm.mode[0].sclk / 2;
info->pm.mode[2].mclk = info->pm.mode[0].mclk / 2;
info->pm.mode[2].pcie_lanes = 4;
} else {
info->pm.mode[1].type = POWER_HIGH;
info->pm.mode[1].sclk = info->pm.mode[0].sclk / 2;
info->pm.mode[1].mclk = info->pm.mode[0].mclk / 2;
info->pm.mode[1].pcie_lanes = 4;
info->pm.num_modes += 1;
}
RADEONSetStaticPowerMode(pScrn, POWER_HIGH);
} else
info->pm.force_low_power_enabled = FALSE;
RADEONPMQuirks(pScrn);
}
void RADEONPMEnterVT(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->pm.clock_gating_enabled)
RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled);
RADEONPMQuirks(pScrn);
if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled)
RADEONSetStaticPowerMode(pScrn, POWER_HIGH);
}
void RADEONPMLeaveVT(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->pm.clock_gating_enabled)
RADEONSetClockGating(pScrn, FALSE);
if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled)
RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT);
}
void RADEONPMFini(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->pm.clock_gating_enabled)
RADEONSetClockGating(pScrn, FALSE);
if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled)
RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT);
}
void RADEONPMBlockHandler(ScrnInfoPtr pScrn)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
if ((!pRADEONEnt->Controller[0]->enabled) &&
(!pRADEONEnt->Controller[1]->enabled))
RADEONSetStaticPowerMode(pScrn, POWER_LOW);
else
RADEONSetStaticPowerMode(pScrn, POWER_HIGH);
}

68
src/radeon_probe.c
View file

@ -50,40 +50,15 @@
#include "xf86Resources.h"
#endif
#ifdef XF86DRM_MODE
#include "xf86drmMode.h"
#include "dri.h"
#endif
#include "radeon_chipset_gen.h"
#include "radeon_pci_chipset_gen.h"
#include "radeon_chipinfo_gen.h"
#ifdef XSERVER_LIBPCIACCESS
#include "radeon_pci_device_match_gen.h"
static Bool radeon_ums_supported(ScrnInfoPtr pScrn, struct pci_device *pci_dev)
{
unsigned family = 0, i;
for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
if (pci_dev->device_id == RADEONCards[i].pci_device_id) {
family = RADEONCards[i].chip_family;
break;
}
}
if (family >= CHIP_FAMILY_SUMO) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
"GPU only supported with KMS, using vesa instead.\n");
return FALSE;
}
return TRUE;
}
#else
#define radeon_ums_supported(x, y) TRUE
#endif
#ifndef XSERVER_LIBPCIACCESS
@ -109,7 +84,6 @@ RADEONIdentify(int flags)
}
#ifdef XF86DRM_MODE
static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci_dev)
{
char *busIdString;
@ -134,16 +108,12 @@ static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci
"[KMS] Kernel modesetting enabled.\n");
return TRUE;
}
#else
#define radeon_kernel_mode_enabled(x, y) FALSE
#endif
static Bool
radeon_get_scrninfo(int entity_num, void *pci_dev)
{
ScrnInfoPtr pScrn = NULL;
EntityInfoPtr pEnt;
int kms = 0;
pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets,
NULL,
@ -153,12 +123,8 @@ radeon_get_scrninfo(int entity_num, void *pci_dev)
return FALSE;
if (pci_dev) {
if (radeon_kernel_mode_enabled(pScrn, pci_dev)) {
kms = 1;
} else {
if (!radeon_ums_supported(pScrn, pci_dev)) {
return FALSE;
}
if (!radeon_kernel_mode_enabled(pScrn, pci_dev)) {
return FALSE;
}
}
@ -171,28 +137,14 @@ radeon_get_scrninfo(int entity_num, void *pci_dev)
pScrn->Probe = RADEONProbe;
#endif
#ifdef XF86DRM_MODE
if (kms == 1) {
pScrn->PreInit = RADEONPreInit_KMS;
pScrn->ScreenInit = RADEONScreenInit_KMS;
pScrn->SwitchMode = RADEONSwitchMode_KMS;
pScrn->AdjustFrame = RADEONAdjustFrame_KMS;
pScrn->EnterVT = RADEONEnterVT_KMS;
pScrn->LeaveVT = RADEONLeaveVT_KMS;
pScrn->FreeScreen = RADEONFreeScreen_KMS;
pScrn->ValidMode = RADEONValidMode;
} else
#endif
{
pScrn->PreInit = RADEONPreInit;
pScrn->ScreenInit = RADEONScreenInit;
pScrn->SwitchMode = RADEONSwitchMode;
pScrn->AdjustFrame = RADEONAdjustFrame;
pScrn->EnterVT = RADEONEnterVT;
pScrn->LeaveVT = RADEONLeaveVT;
pScrn->FreeScreen = RADEONFreeScreen;
pScrn->ValidMode = RADEONValidMode;
}
pScrn->PreInit = RADEONPreInit_KMS;
pScrn->ScreenInit = RADEONScreenInit_KMS;
pScrn->SwitchMode = RADEONSwitchMode_KMS;
pScrn->AdjustFrame = RADEONAdjustFrame_KMS;
pScrn->EnterVT = RADEONEnterVT_KMS;
pScrn->LeaveVT = RADEONLeaveVT_KMS;
pScrn->FreeScreen = RADEONFreeScreen_KMS;
pScrn->ValidMode = RADEONValidMode;
pEnt = xf86GetEntityInfo(entity_num);

640
src/radeon_probe.h
View file

@ -44,18 +44,10 @@
#include "xf86Crtc.h"
#include "compat-api.h"
#ifdef USE_EXA
#include "exa.h"
#endif
#ifdef USE_XAA
#include "xaa.h"
#endif
extern DriverRec RADEON;
#define RADEON_MAX_CRTC 6
#define RADEON_MAX_BIOS_CONNECTOR 16
typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
@ -123,634 +115,14 @@ typedef struct {
int singledac;
} RADEONCardInfo;
typedef enum
{
MT_UNKNOWN = -1,
MT_NONE = 0,
MT_CRT = 1,
MT_LCD = 2,
MT_DFP = 3,
MT_CTV = 4,
MT_STV = 5,
MT_CV = 6,
MT_HDMI = 7, // this should really just be MT_DFP
MT_DP = 8
} RADEONMonitorType;
typedef enum
{
CONNECTOR_NONE,
CONNECTOR_VGA,
CONNECTOR_DVI_I,
CONNECTOR_DVI_D,
CONNECTOR_DVI_A,
CONNECTOR_STV,
CONNECTOR_CTV,
CONNECTOR_LVDS,
CONNECTOR_DIGITAL,
CONNECTOR_SCART,
CONNECTOR_HDMI_TYPE_A,
CONNECTOR_HDMI_TYPE_B,
CONNECTOR_0XC,
CONNECTOR_0XD,
CONNECTOR_DIN,
CONNECTOR_DISPLAY_PORT,
CONNECTOR_EDP,
CONNECTOR_UNSUPPORTED
} RADEONConnectorType;
typedef enum
{
DVI_AUTO,
DVI_DIGITAL,
DVI_ANALOG
} RADEONDviType;
typedef enum
{
RMX_OFF,
RMX_FULL,
RMX_CENTER,
RMX_ASPECT
} RADEONRMXType;
typedef struct {
uint32_t freq;
uint32_t value;
}RADEONTMDSPll;
/* standards */
typedef enum
{
TV_STD_NTSC = 1,
TV_STD_PAL = 2,
TV_STD_PAL_M = 4,
TV_STD_PAL_60 = 8,
TV_STD_NTSC_J = 16,
TV_STD_SCART_PAL = 32,
TV_STD_SECAM = 64,
TV_STD_PAL_CN = 128,
} TVStd;
typedef struct
{
Bool valid;
uint32_t mask_clk_reg;
uint32_t mask_data_reg;
uint32_t a_clk_reg;
uint32_t a_data_reg;
uint32_t put_clk_reg;
uint32_t put_data_reg;
uint32_t get_clk_reg;
uint32_t get_data_reg;
uint32_t mask_clk_mask;
uint32_t mask_data_mask;
uint32_t put_clk_mask;
uint32_t put_data_mask;
uint32_t get_clk_mask;
uint32_t get_data_mask;
uint32_t a_clk_mask;
uint32_t a_data_mask;
int hw_line;
Bool hw_capable;
} RADEONI2CBusRec, *RADEONI2CBusPtr;
enum radeon_pll_algo {
RADEON_PLL_OLD,
RADEON_PLL_NEW
};
typedef struct _RADEONCrtcPrivateRec {
void *crtc_rotate_mem;
void *cursor_mem;
int crtc_id;
int binding;
uint32_t cursor_offset;
/* Lookup table values to be set when the CRTC is enabled */
uint16_t lut_r[256], lut_g[256], lut_b[256];
uint32_t crtc_offset;
int can_tile;
Bool enabled;
Bool initialized;
Bool scaler_enabled;
float vsc;
float hsc;
int pll_id;
enum radeon_pll_algo pll_algo;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
uint16_t encoder_id;
int devices;
void *dev_priv;
} radeon_encoder_rec, *radeon_encoder_ptr;
typedef struct _radeon_tvout {
/* TV out */
TVStd default_tvStd;
TVStd tvStd;
int hPos;
int vPos;
int hSize;
float TVRefClk;
int SupportedTVStds;
Bool tv_on;
} radeon_tvout_rec, *radeon_tvout_ptr;
typedef struct _radeon_native_mode {
/* panel stuff */
int PanelXRes;
int PanelYRes;
int HOverPlus;
int HSyncWidth;
int HBlank;
int VOverPlus;
int VSyncWidth;
int VBlank;
int Flags;
int DotClock;
} radeon_native_mode_rec, *radeon_native_mode_ptr;
typedef struct _radeon_tvdac {
// tv dac
uint32_t ps2_tvdac_adj;
uint32_t pal_tvdac_adj;
uint32_t ntsc_tvdac_adj;
} radeon_tvdac_rec, *radeon_tvdac_ptr;
typedef struct _radeon_tmds {
// tmds
RADEONTMDSPll tmds_pll[4];
} radeon_tmds_rec, *radeon_tmds_ptr;
typedef struct _radeon_lvds {
// panel mode
radeon_native_mode_rec native_mode;
// lvds
int PanelPwrDly;
int lvds_misc;
int lvds_ss_id;
} radeon_lvds_rec, *radeon_lvds_ptr;
typedef struct _radeon_dvo {
/* dvo */
I2CBusPtr pI2CBus;
I2CDevPtr DVOChip;
RADEONI2CBusRec dvo_i2c;
int dvo_i2c_slave_addr;
Bool dvo_duallink;
} radeon_dvo_rec, *radeon_dvo_ptr;
typedef struct {
RADEONConnectorType ConnectorType;
Bool valid;
int output_id;
int devices;
int hpd_mask;
RADEONI2CBusRec ddc_i2c;
int igp_lane_info;
Bool shared_ddc;
int i2c_line_mux;
Bool load_detection;
Bool linkb;
uint16_t connector_object;
uint16_t connector_object_id;
uint8_t ucI2cId;
uint8_t hpd_id;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
uint16_t connector_id;
uint32_t devices;
uint32_t active_device;
Bool enabled;
int load_detection;
// DVI/HDMI
Bool coherent_mode;
Bool linkb;
RADEONConnectorType ConnectorType;
uint16_t connector_object_id;
RADEONDviType DVIType;
RADEONMonitorType MonType;
// DDC info
I2CBusPtr pI2CBus;
RADEONI2CBusRec ddc_i2c;
Bool shared_ddc;
Bool custom_edid;
xf86MonPtr custom_mon;
// router info
// HDP info
// panel mode
radeon_native_mode_rec native_mode;
// RMX
RADEONRMXType rmx_type;
int Flags;
//tvout - move to encoder
radeon_tvout_rec tvout;
/* dce 3.x dig block */
int igp_lane_info;
int dig_encoder;
int pixel_clock;
/* DP - aux bus*/
I2CBusPtr dp_pI2CBus;
uint8_t ucI2cId;
char dp_bus_name[20];
uint32_t dp_i2c_addr;
Bool dp_i2c_running;
/* DP - general config */
uint8_t dpcd[8];
int dp_lane_count;
int dp_clock;
uint8_t hpd_id;
int pll_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
struct avivo_pll_state {
uint32_t ref_div_src;
uint32_t ref_div;
uint32_t fb_div;
uint32_t post_div_src;
uint32_t post_div;
uint32_t ext_ppll_cntl;
uint32_t pll_cntl;
uint32_t int_ss_cntl;
};
struct avivo_crtc_state {
uint32_t pll_source;
uint32_t h_total;
uint32_t h_blank_start_end;
uint32_t h_sync_a;
uint32_t h_sync_a_cntl;
uint32_t h_sync_b;
uint32_t h_sync_b_cntl;
uint32_t v_total;
uint32_t v_blank_start_end;
uint32_t v_sync_a;
uint32_t v_sync_a_cntl;
uint32_t v_sync_b;
uint32_t v_sync_b_cntl;
uint32_t control;
uint32_t blank_control;
uint32_t interlace_control;
uint32_t stereo_control;
uint32_t cursor_control;
};
struct avivo_grph_state {
uint32_t enable;
uint32_t control;
uint32_t swap_control;
uint32_t prim_surf_addr;
uint32_t sec_surf_addr;
uint32_t pitch;
uint32_t prim_surf_addr_hi;
uint32_t sec_surf_addr_hi;
uint32_t x_offset;
uint32_t y_offset;
uint32_t x_start;
uint32_t y_start;
uint32_t x_end;
uint32_t y_end;
uint32_t desktop_height;
uint32_t viewport_start;
uint32_t viewport_size;
uint32_t mode_data_format;
};
struct dce4_main_block_state {
struct avivo_grph_state grph;
uint32_t scl[6];
uint32_t crtc[15];
uint32_t fmt[10];
uint32_t dig[20];
};
struct dce4_state
{
uint32_t vga1_cntl;
uint32_t vga2_cntl;
uint32_t vga3_cntl;
uint32_t vga4_cntl;
uint32_t vga5_cntl;
uint32_t vga6_cntl;
uint32_t vga_render_control;
struct dce4_main_block_state block[6];
uint32_t vga_pll[3][3];
uint32_t pll[2][15];
uint32_t pll_route[6];
uint32_t dac[2][26];
uint32_t uniphy[6][10];
uint32_t dig[20];
};
struct avivo_state
{
uint32_t hdp_fb_location;
uint32_t mc_memory_map;
uint32_t vga_memory_base;
uint32_t vga_fb_start;
uint32_t vga1_cntl;
uint32_t vga2_cntl;
uint32_t vga3_cntl;
uint32_t vga4_cntl;
uint32_t vga5_cntl;
uint32_t vga6_cntl;
uint32_t vga_render_control;
uint32_t crtc_master_en;
uint32_t crtc_tv_control;
uint32_t dc_lb_memory_split;
struct avivo_pll_state pll[2];
struct avivo_pll_state vga25_ppll;
struct avivo_pll_state vga28_ppll;
struct avivo_pll_state vga41_ppll;
struct avivo_crtc_state crtc[2];
struct avivo_grph_state grph[2];
/* DDIA block on RS6xx chips */
uint32_t ddia[37];
/* scalers */
uint32_t d1scl[40];
uint32_t d2scl[40];
uint32_t dxscl[6+2];
/* dac regs */
uint32_t daca[26];
uint32_t dacb[26];
/* tmdsa */
uint32_t tmdsa[31];
/* lvtma */
uint32_t lvtma[39];
/* dvoa */
uint32_t dvoa[16];
/* DCE3+ chips */
uint32_t fmt1[18];
uint32_t fmt2[18];
uint32_t dig1[19];
uint32_t dig2[19];
uint32_t hdmi1[57];
uint32_t hdmi2[57];
uint32_t aux_cntl1[14];
uint32_t aux_cntl2[14];
uint32_t aux_cntl3[14];
uint32_t aux_cntl4[14];
uint32_t aux_cntl5[14];
uint32_t aux_cntl6[14];
uint32_t phy[10];
uint32_t uniphy1[8];
uint32_t uniphy2[8];
uint32_t uniphy3[8];
uint32_t uniphy4[8];
uint32_t uniphy5[8];
uint32_t uniphy6[8];
};
/*
* Maximum length of horizontal/vertical code timing tables for state storage
*/
#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32
typedef struct {
struct avivo_state avivo;
struct dce4_state dce4;
/* Common registers */
uint32_t ovr_clr;
uint32_t ovr_wid_left_right;
uint32_t ovr_wid_top_bottom;
uint32_t ov0_scale_cntl;
uint32_t mpp_tb_config;
uint32_t mpp_gp_config;
uint32_t subpic_cntl;
uint32_t viph_control;
uint32_t i2c_cntl_1;
uint32_t gen_int_cntl;
uint32_t cap0_trig_cntl;
uint32_t cap1_trig_cntl;
uint32_t bus_cntl;
uint32_t bios_0_scratch;
uint32_t bios_1_scratch;
uint32_t bios_2_scratch;
uint32_t bios_3_scratch;
uint32_t bios_4_scratch;
uint32_t bios_5_scratch;
uint32_t bios_6_scratch;
uint32_t bios_7_scratch;
uint32_t surface_cntl;
uint32_t surfaces[8][3];
uint32_t mc_agp_location;
uint32_t mc_agp_location_hi;
uint32_t mc_fb_location;
uint32_t display_base_addr;
uint32_t display2_base_addr;
uint32_t ov0_base_addr;
/* Other registers to save for VT switches */
uint32_t dp_datatype;
uint32_t rbbm_soft_reset;
uint32_t clock_cntl_index;
uint32_t amcgpio_en_reg;
uint32_t amcgpio_mask;
/* CRTC registers */
uint32_t crtc_gen_cntl;
uint32_t crtc_ext_cntl;
uint32_t dac_cntl;
uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_offset;
uint32_t crtc_offset_cntl;
uint32_t crtc_pitch;
uint32_t disp_merge_cntl;
uint32_t grph_buffer_cntl;
uint32_t crtc_more_cntl;
uint32_t crtc_tile_x0_y0;
/* CRTC2 registers */
uint32_t crtc2_gen_cntl;
uint32_t dac_macro_cntl;
uint32_t dac2_cntl;
uint32_t disp_output_cntl;
uint32_t disp_tv_out_cntl;
uint32_t disp_hw_debug;
uint32_t disp2_merge_cntl;
uint32_t grph2_buffer_cntl;
uint32_t crtc2_h_total_disp;
uint32_t crtc2_h_sync_strt_wid;
uint32_t crtc2_v_total_disp;
uint32_t crtc2_v_sync_strt_wid;
uint32_t crtc2_offset;
uint32_t crtc2_offset_cntl;
uint32_t crtc2_pitch;
uint32_t crtc2_tile_x0_y0;
/* Flat panel registers */
uint32_t fp_crtc_h_total_disp;
uint32_t fp_crtc_v_total_disp;
uint32_t fp_gen_cntl;
uint32_t fp2_gen_cntl;
uint32_t fp_h_sync_strt_wid;
uint32_t fp_h2_sync_strt_wid;
uint32_t fp_horz_stretch;
uint32_t fp_horz_vert_active;
uint32_t fp_panel_cntl;
uint32_t fp_v_sync_strt_wid;
uint32_t fp_v2_sync_strt_wid;
uint32_t fp_vert_stretch;
uint32_t lvds_gen_cntl;
uint32_t lvds_pll_cntl;
uint32_t tmds_pll_cntl;
uint32_t tmds_transmitter_cntl;
/* Computed values for PLL */
uint32_t dot_clock_freq;
uint32_t pll_output_freq;
int feedback_div;
int reference_div;
int post_div;
/* PLL registers */
unsigned ppll_ref_div;
unsigned ppll_div_3;
uint32_t htotal_cntl;
uint32_t vclk_ecp_cntl;
/* Computed values for PLL2 */
uint32_t dot_clock_freq_2;
uint32_t pll_output_freq_2;
int feedback_div_2;
int reference_div_2;
int post_div_2;
/* PLL2 registers */
uint32_t p2pll_ref_div;
uint32_t p2pll_div_0;
uint32_t htotal_cntl2;
uint32_t pixclks_cntl;
/* Pallet */
Bool palette_valid;
Bool palette_saved[2];
uint32_t palette[2][256];
uint32_t disp2_req_cntl1;
uint32_t disp2_req_cntl2;
uint32_t dmif_mem_cntl1;
uint32_t disp1_req_cntl1;
uint32_t fp_2nd_gen_cntl;
uint32_t fp2_2_gen_cntl;
uint32_t tmds2_cntl;
uint32_t tmds2_transmitter_cntl;
/* TV out registers */
uint32_t tv_master_cntl;
uint32_t tv_htotal;
uint32_t tv_hsize;
uint32_t tv_hdisp;
uint32_t tv_hstart;
uint32_t tv_vtotal;
uint32_t tv_vdisp;
uint32_t tv_timing_cntl;
uint32_t tv_vscaler_cntl1;
uint32_t tv_vscaler_cntl2;
uint32_t tv_sync_size;
uint32_t tv_vrestart;
uint32_t tv_hrestart;
uint32_t tv_frestart;
uint32_t tv_ftotal;
uint32_t tv_clock_sel_cntl;
uint32_t tv_clkout_cntl;
uint32_t tv_data_delay_a;
uint32_t tv_data_delay_b;
uint32_t tv_dac_cntl;
uint32_t tv_pll_cntl;
uint32_t tv_pll_cntl1;
uint32_t tv_pll_fine_cntl;
uint32_t tv_modulator_cntl1;
uint32_t tv_modulator_cntl2;
uint32_t tv_frame_lock_cntl;
uint32_t tv_pre_dac_mux_cntl;
uint32_t tv_rgb_cntl;
uint32_t tv_y_saw_tooth_cntl;
uint32_t tv_y_rise_cntl;
uint32_t tv_y_fall_cntl;
uint32_t tv_uv_adr;
uint32_t tv_upsamp_and_gain_cntl;
uint32_t tv_gain_limit_settings;
uint32_t tv_linear_gain_settings;
uint32_t tv_crc_cntl;
uint32_t tv_sync_cntl;
uint32_t gpiopad_a;
uint32_t pll_test_cntl;
uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
} RADEONSaveRec, *RADEONSavePtr;
typedef struct
{
Bool HasSecondary;
Bool HasCRTC2; /* All cards except original Radeon */
/*
* The next two are used to make sure CRTC2 is restored before CRTC_EXT,
* otherwise it could lead to blank screens.
*/
Bool IsSecondaryRestored;
Bool RestorePrimary;
Bool ReversedDAC; /* TVDAC used as primary dac */
Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */
xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
ScrnInfoPtr pSecondaryScrn;
ScrnInfoPtr pPrimaryScrn;
RADEONSaveRec ModeReg; /* Current mode */
RADEONSaveRec SavedReg; /* Original (text) mode */
void *MMIO; /* Map of MMIO region */
int MMIO_cnt; /* Map of FB region refcount */
void *FB; /* Map of FB region */
int FB_cnt; /* Map of FB region refcount */
int fd; /* for sharing across zaphod heads */
unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */
int dri2_info_cnt;
@ -760,22 +132,13 @@ typedef struct
extern PciChipsets RADEONPciChipsets[];
/* radeon_driver.c */
extern Bool RADEONPreInit(ScrnInfoPtr, int);
extern Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL);
extern Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL);
#ifdef X_XF86MiscPassMessage
extern Bool RADEONHandleMessage(int, const char*, const char*,
char**);
#endif
extern void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL);
extern Bool RADEONEnterVT(VT_FUNC_ARGS_DECL);
extern void RADEONLeaveVT(VT_FUNC_ARGS_DECL);
extern void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL);
extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE, DisplayModePtr, Bool, int);
extern const OptionInfoRec *RADEONOptionsWeak(void);
#ifdef XF86DRM_MODE
extern Bool RADEONPreInit_KMS(ScrnInfoPtr, int);
extern Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL);
extern Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL);
@ -783,6 +146,7 @@ extern void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL);
extern Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL);
extern void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL);
extern void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL);
#endif
extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
Bool verbose, int flag);
#endif /* _RADEON_PROBE_H_ */

1060
src/radeon_render.c
View file

File diff suppressed because it is too large Load diff

199
src/radeon_textured_video.c
View file

@ -46,16 +46,9 @@
extern void
R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
#ifdef XF86DRM_MODE
extern void
EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
#endif
extern Bool
R600CopyToVRAM(ScrnInfoPtr pScrn,
char *src, int src_pitch,
uint32_t dst_pitch, uint32_t dst_mc_addr, uint32_t dst_width, uint32_t dst_height, int bpp,
int x, int y, int w, int h);
#define IMAGE_MAX_WIDTH 2048
#define IMAGE_MAX_HEIGHT 2048
@ -72,22 +65,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef USE_EXA
if (info->useEXA) {
if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0)
return TRUE;
else
return FALSE;
} else
#endif
{
if (info->tilingEnabled && ((pPix->devPrivate.ptr - info->FB) == 0))
return TRUE;
else
return FALSE;
}
return FALSE;
}
static __inline__ uint32_t F_TO_DW(float val)
@ -144,30 +122,9 @@ static REF_TRANSFORM trans[2] =
{1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */
};
#define ACCEL_MMIO
#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
#define OUT_RELOC(x, read, write) do {} while(0)
#define FINISH_ACCEL()
#include "radeon_textured_videofuncs.c"
#undef ACCEL_MMIO
#undef ACCEL_PREAMBLE
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
#undef OUT_ACCEL_REG_F
#undef OUT_RELOC
#undef FINISH_ACCEL
#ifdef XF86DRI
#define ACCEL_CP
#define ACCEL_PREAMBLE() \
RING_LOCALS; \
RADEONCP_REFRESH(pScrn, info)
RING_LOCALS;
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
#define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val))
@ -177,7 +134,6 @@ static REF_TRANSFORM trans[2] =
#include "radeon_textured_videofuncs.c"
#undef ACCEL_CP
#undef ACCEL_PREAMBLE
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
@ -185,8 +141,6 @@ static REF_TRANSFORM trans[2] =
#undef FINISH_ACCEL
#undef OUT_RING_F
#endif /* XF86DRI */
static void
R600CopyData(
ScrnInfoPtr pScrn,
@ -198,29 +152,18 @@ R600CopyData(
unsigned int w,
unsigned int cpp
){
RADEONInfoPtr info = RADEONPTR( pScrn );
if (cpp == 2) {
w *= 2;
cpp = 1;
}
if (info->DMAForXv) {
uint32_t dst_mc_addr = dst - (unsigned char *)info->FB + info->fbLocation;
R600CopyToVRAM(pScrn,
(char *)src, srcPitch,
dstPitch, dst_mc_addr, w, h, cpp * 8,
0, 0, w, h);
} else {
if (srcPitch == dstPitch)
memcpy(dst, src, srcPitch * h);
else {
while (h--) {
memcpy(dst, src, srcPitch);
src += srcPitch;
dst += dstPitch;
}
if (srcPitch == dstPitch)
memcpy(dst, src, srcPitch * h);
else {
while (h--) {
memcpy(dst, src, srcPitch);
src += srcPitch;
dst += dstPitch;
}
}
}
@ -251,11 +194,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
BoxRec dstBox;
int dst_width = width, dst_height = height;
int aligned_height;
#ifdef XF86DRM_MODE
int h_align = drmmode_get_height_align(pScrn, 0);
#else
int h_align = 1;
#endif
struct radeon_bo *src_bo;
int ret;
/* make the compiler happy */
s2offset = s3offset = srcPitch2 = 0;
@ -291,20 +233,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->bicubic_enabled = FALSE;
}
#ifdef XF86DRM_MODE
if (info->cs) {
if (info->ChipFamily >= CHIP_FAMILY_R600)
pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0);
else
pPriv->hw_align = 64;
} else
#endif
{
if (info->ChipFamily >= CHIP_FAMILY_R600)
pPriv->hw_align = 256;
else
pPriv->hw_align = 64;
}
if (info->ChipFamily >= CHIP_FAMILY_R600)
pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0);
else
pPriv->hw_align = 64;
aligned_height = RADEON_ALIGN(dst_height, h_align);
@ -345,12 +277,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
if (pPriv->video_offset == 0)
return BadAlloc;
if (info->cs) {
pPriv->src_bo[0] = pPriv->video_memory;
radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size,
pPriv->hw_align,
RADEON_GEM_DOMAIN_GTT);
}
pPriv->src_bo[0] = pPriv->video_memory;
radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size,
pPriv->hw_align,
RADEON_GEM_DOMAIN_GTT);
}
/* Bicubic filter loading */
@ -365,47 +295,26 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
else
pPriv->pPixmap = (PixmapPtr)pDraw;
#ifdef USE_EXA
if (info->useEXA) {
/* Force the pixmap into framebuffer so we can draw to it. */
info->exa_force_create = TRUE;
exaMoveInPixmap(pPriv->pPixmap);
info->exa_force_create = FALSE;
}
#endif
if (!info->useEXA &&
(((char *)pPriv->pPixmap->devPrivate.ptr < (char *)info->FB) ||
((char *)pPriv->pPixmap->devPrivate.ptr >= (char *)info->FB +
info->FbMapSize))) {
/* If the pixmap wasn't in framebuffer, then we have no way in XAA to
* force it there. So, we simply refuse to draw and fail.
*/
return BadAlloc;
}
/* Force the pixmap into framebuffer so we can draw to it. */
info->exa_force_create = TRUE;
exaMoveInPixmap(pPriv->pPixmap);
info->exa_force_create = FALSE;
/* copy data */
top = (y1 >> 16) & ~1;
nlines = ((y2 + 0xffff) >> 16) - top;
pPriv->src_offset = pPriv->video_offset;
if (info->cs) {
struct radeon_bo *src_bo;
int ret;
pPriv->currentBuffer ^= 1;
src_bo = pPriv->src_bo[pPriv->currentBuffer];
pPriv->currentBuffer ^= 1;
src_bo = pPriv->src_bo[pPriv->currentBuffer];
ret = radeon_bo_map(src_bo, 1);
if (ret)
return BadAlloc;
pPriv->src_addr = src_bo->ptr;
} else {
pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset);
RADEONWaitForIdleMMIO(pScrn);
}
ret = radeon_bo_map(src_bo, 1);
if (ret)
return BadAlloc;
pPriv->src_addr = src_bo->ptr;
pPriv->src_pitch = dstPitch;
pPriv->planeu_offset = dstPitch * aligned_height;
@ -489,18 +398,11 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->w = width;
pPriv->h = height;
#if defined(XF86DRM_MODE)
if (info->cs)
radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]);
#endif
#ifdef XF86DRI
radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]);
if (info->directRenderingEnabled) {
#ifdef XF86DRM_MODE
if (IS_EVERGREEN_3D)
EVERGREENDisplayTexturedVideo(pScrn, pPriv);
else
#endif
if (IS_R600_3D)
else if (IS_R600_3D)
R600DisplayTexturedVideo(pScrn, pPriv);
else if (IS_R500_3D)
R500DisplayTexturedVideoCP(pScrn, pPriv);
@ -510,17 +412,6 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
R200DisplayTexturedVideoCP(pScrn, pPriv);
else
RADEONDisplayTexturedVideoCP(pScrn, pPriv);
} else
#endif
{
if (IS_R500_3D)
R500DisplayTexturedVideoMMIO(pScrn, pPriv);
else if (IS_R300_3D)
R300DisplayTexturedVideoMMIO(pScrn, pPriv);
else if (IS_R200_3D)
R200DisplayTexturedVideoMMIO(pScrn, pPriv);
else
RADEONDisplayTexturedVideoMMIO(pScrn, pPriv);
}
return Success;
@ -765,21 +656,17 @@ Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn)
if (info->bicubic_offset == 0)
return FALSE;
if (info->cs)
info->bicubic_bo = info->bicubic_memory;
info->bicubic_bo = info->bicubic_memory;
/* Upload bicubic filter tex */
if (info->ChipFamily < CHIP_FAMILY_R600) {
uint8_t *bicubic_addr;
int ret;
if (info->cs) {
ret = radeon_bo_map(info->bicubic_bo, 1);
if (ret)
return FALSE;
ret = radeon_bo_map(info->bicubic_bo, 1);
if (ret)
return FALSE;
bicubic_addr = info->bicubic_bo->ptr;
} else
bicubic_addr = (uint8_t *)(info->FB + info->bicubic_offset);
bicubic_addr = info->bicubic_bo->ptr;
RADEONCopySwap(bicubic_addr, (uint8_t *)bicubic_tex_512, 1024,
#if X_BYTE_ORDER == X_BIG_ENDIAN
@ -788,8 +675,7 @@ Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn)
RADEON_HOST_DATA_SWAP_NONE
#endif
);
if (info->cs)
radeon_bo_unmap(info->bicubic_bo);
radeon_bo_unmap(info->bicubic_bo);
}
return TRUE;
}
@ -895,9 +781,6 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
RADEONPortPrivPtr pPriv = &pPortPriv[i];
pPriv->textured = TRUE;
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
pPriv->bicubic_state = BICUBIC_OFF;
pPriv->vsync = TRUE;
pPriv->brightness = 0;

458
src/radeon_textured_videofuncs.c
View file

@ -25,9 +25,6 @@
*
*/
#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
#error Cannot define both MMIO and CP acceleration!
#endif
#if !defined(UNIXCPP) || defined(ANSICPP)
#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
@ -35,17 +32,7 @@
#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
#endif
#ifdef ACCEL_MMIO
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
#else
#ifdef ACCEL_CP
#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
#else
#error No accel type defined!
#endif
#endif
#ifdef ACCEL_CP
#define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
@ -65,27 +52,6 @@ do { \
OUT_RING_F(_srcY); \
} while (0)
#else /* ACCEL_CP */
#define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
} while (0)
#define VTX_OUT_4(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
} while (0)
#endif /* !ACCEL_CP */
static Bool
FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
@ -100,62 +66,28 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
int pixel_shift;
int scissor_w = MIN(pPixmap->drawable.width, 2047);
int scissor_h = MIN(pPixmap->drawable.height, 2047);
int ret;
ACCEL_PREAMBLE();
#ifdef XF86DRM_MODE
if (info->cs) {
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
#else
(void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
#ifdef USE_EXA
if (info->useEXA) {
dst_pitch = exaGetPixmapPitch(pPixmap);
} else
#endif
{
dst_pitch = pPixmap->devKind;
}
#ifdef USE_EXA
if (info->useEXA) {
RADEON_SWITCH_TO_3D();
} else
#endif
{
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
/* We must wait for 3d to idle, in case source was just written as a dest. */
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
}
dst_pitch = exaGetPixmapPitch(pPixmap);
RADEON_SWITCH_TO_3D();
/* Same for R100/R200 */
switch (pPixmap->drawable.bitsPerPixel) {
@ -190,7 +122,7 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (RADEONTilingEnabled(pScrn, pPixmap))
colorpitch |= RADEON_COLOR_TILE_ENABLE;
txoffset = info->cs ? 0 : pPriv->src_offset;
txoffset = 0;
BEGIN_ACCEL_RELOC(4,2);
@ -404,16 +336,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
* the single triangle up to 2560/4021 pixels; above that we
* render as a quad.
*/
#ifdef ACCEL_CP
while (nBox) {
int draw_size = 3 * pPriv->vtx_count + 5;
int loop_boxes;
if (draw_size > radeon_cs_space_remaining(pScrn)) {
if (info->cs)
radeon_cs_flush_indirect(pScrn);
else
RADEONCPFlushIndirect(pScrn, 1);
radeon_cs_flush_indirect(pScrn);
if (!FUNC_NAME(RADEONPrepareTexturedVideo)(pScrn, pPriv))
return;
}
@ -486,63 +414,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
ADVANCE_RING();
}
#else /* ACCEL_CP */
BEGIN_ACCEL(nBox * pPriv->vtx_count * 3 + 2);
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT)));
while (nBox--) {
float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
dstw = pBox->x2 - pBox->x1;
dsth = pBox->y2 - pBox->y1;
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
pPriv->src_h) / (float)pPriv->dst_h;
srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
/*
* Just render a rect (using three coords).
*/
VTX_OUT_6((float)dstX, (float)(dstY + dsth),
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h,
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth),
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h,
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_6((float)(dstX + dstw), (float)dstY,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h);
} else {
/*
* Just render a rect (using three coords).
*/
VTX_OUT_4((float)dstX, (float)(dstY + dsth),
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth),
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_4((float)(dstX + dstw), (float)dstY,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h);
}
pBox++;
}
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
#endif /* !ACCEL_CP */
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
@ -569,61 +440,29 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
int ref = pPriv->transform_index;
float ucscale = 0.25, vcscale = 0.25;
Bool needux8 = FALSE, needvx8 = FALSE;
int ret;
ACCEL_PREAMBLE();
#ifdef XF86DRM_MODE
if (info->cs) {
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
#else
(void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
#ifdef USE_EXA
if (info->useEXA) {
dst_pitch = exaGetPixmapPitch(pPixmap);
} else
#endif
{
dst_pitch = pPixmap->devKind;
}
dst_pitch = exaGetPixmapPitch(pPixmap);
#ifdef USE_EXA
if (info->useEXA) {
RADEON_SWITCH_TO_3D();
} else
#endif
{
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
/* We must wait for 3d to idle, in case source was just written as a dest. */
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
}
RADEON_SWITCH_TO_3D();
/* Same for R100/R200 */
switch (pPixmap->drawable.bitsPerPixel) {
@ -705,7 +544,7 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vcscale = 0.125;
}
txoffset = info->cs ? 0 : pPriv->src_offset;
txoffset = 0;
if (pPriv->is_planar) {
/* need 2 texcoord sets (even though they are identical) due
@ -1046,16 +885,12 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
* render as a quad.
*/
#ifdef ACCEL_CP
while (nBox) {
int draw_size = 3 * pPriv->vtx_count + 4;
int loop_boxes;
if (draw_size > radeon_cs_space_remaining(pScrn)) {
if (info->cs)
radeon_cs_flush_indirect(pScrn);
else
RADEONCPFlushIndirect(pScrn, 1);
radeon_cs_flush_indirect(pScrn);
if (!FUNC_NAME(R200PrepareTexturedVideo)(pScrn, pPriv))
return;
}
@ -1118,60 +953,6 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
ADVANCE_RING();
}
#else /* ACCEL_CP */
BEGIN_ACCEL(nBox * 3 * pPriv->vtx_count + 2);
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT)));
while (nBox--) {
float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
dstw = pBox->x2 - pBox->x1;
dsth = pBox->y2 - pBox->y1;
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
pPriv->src_h) / (float)pPriv->dst_h;
srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
/*
* Just render a rect (using three coords).
*/
VTX_OUT_6((float)dstX, (float)(dstY + dsth),
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h,
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth),
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h,
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_6((float)(dstX + dstw), (float)dstY,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h);
} else {
/*
* Just render a rect (using three coords).
*/
VTX_OUT_4((float)dstX, (float)(dstY + dsth),
(float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth),
(float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h);
VTX_OUT_4((float)(dstX + dstw), (float)dstY,
(float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h);
}
pBox++;
}
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
#endif /* !ACCEL_CP */
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
@ -1188,61 +969,28 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
uint32_t txenable, colorpitch, bicubic_offset;
uint32_t output_fmt;
int pixel_shift;
int ret;
ACCEL_PREAMBLE();
#ifdef XF86DRM_MODE
if (info->cs) {
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
#else
(void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
#ifdef USE_EXA
if (info->useEXA) {
dst_pitch = exaGetPixmapPitch(pPixmap);
} else
#endif
{
dst_pitch = pPixmap->devKind;
}
#ifdef USE_EXA
if (info->useEXA) {
RADEON_SWITCH_TO_3D();
} else
#endif
{
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
/* We must wait for 3d to idle, in case source was just written as a dest. */
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
}
dst_pitch = exaGetPixmapPitch(pPixmap);
RADEON_SWITCH_TO_3D();
if (pPriv->bicubic_enabled)
pPriv->vtx_count = 6;
@ -1309,7 +1057,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_TX_MIN_FILTER_LINEAR |
(0 << R300_TX_ID_SHIFT));
txoffset = info->cs ? 0 : pPriv->src_offset;
txoffset = 0;
BEGIN_ACCEL_RELOC(6, 1);
OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter);
@ -1369,10 +1117,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_TX_MAG_FILTER_NEAREST |
(1 << R300_TX_ID_SHIFT));
if (info->cs)
bicubic_offset = 0;
else
bicubic_offset = pPriv->bicubic_src_offset;
bicubic_offset = 0;
BEGIN_ACCEL_RELOC(6, 1);
OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
@ -2502,18 +2247,13 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
Bool use_quad = FALSE;
#ifdef ACCEL_CP
int draw_size = 4 * pPriv->vtx_count + 4 + 2 + 3;
if (draw_size > radeon_cs_space_remaining(pScrn)) {
if (info->cs)
radeon_cs_flush_indirect(pScrn);
else
RADEONCPFlushIndirect(pScrn, 1);
radeon_cs_flush_indirect(pScrn);
if (!FUNC_NAME(R300PrepareTexturedVideo)(pScrn, pPriv))
return;
}
#endif
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@ -2548,7 +2288,6 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
((dstY + dsth + 1440 - 1) << R300_SCISSOR_Y_SHIFT)));
FINISH_ACCEL();
#ifdef ACCEL_CP
if (use_quad) {
BEGIN_RING(4 * pPriv->vtx_count + 4);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
@ -2564,21 +2303,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
if (use_quad)
BEGIN_ACCEL(2 + pPriv->vtx_count * 4);
else
BEGIN_ACCEL(2 + pPriv->vtx_count * 3);
if (use_quad)
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
(4 << RADEON_VF_NUM_VERTICES_SHIFT)));
else
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
#endif
if (pPriv->bicubic_enabled) {
/*
* This code is only executed on >= R300, so we don't
@ -2642,11 +2367,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flushing is pipelined, free/finish is not */
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
#ifdef ACCEL_CP
ADVANCE_RING();
#else
FINISH_ACCEL();
#endif /* !ACCEL_CP */
pBox++;
}
@ -2672,61 +2393,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
uint32_t txenable, colorpitch, bicubic_offset;
uint32_t output_fmt;
int pixel_shift, out_size = 6;
int ret;
ACCEL_PREAMBLE();
#ifdef XF86DRM_MODE
if (info->cs) {
int ret;
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_reset_bos(info->cs);
radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
driver_priv = exaGetPixmapDriverPrivate(pPixmap);
radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
ret = radeon_cs_space_check(info->cs);
if (ret) {
ErrorF("Not enough RAM to hw accel xv operation\n");
return FALSE;
}
#else
(void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
#ifdef USE_EXA
if (info->useEXA) {
dst_pitch = exaGetPixmapPitch(pPixmap);
} else
#endif
{
dst_pitch = pPixmap->devKind;
}
#ifdef USE_EXA
if (info->useEXA) {
RADEON_SWITCH_TO_3D();
} else
#endif
{
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
/* We must wait for 3d to idle, in case source was just written as a dest. */
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
if (!info->accel_state->XInited3D)
RADEONInit3DEngine(pScrn);
}
dst_pitch = exaGetPixmapPitch(pPixmap);
RADEON_SWITCH_TO_3D();
if (pPriv->bicubic_enabled)
pPriv->vtx_count = 6;
@ -2818,7 +2506,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
out_size++;
}
txoffset = info->cs ? 0 : pPriv->src_offset;
txoffset = 0;
BEGIN_ACCEL_RELOC(out_size, 1);
OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter);
@ -2877,10 +2565,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_TX_MAG_FILTER_NEAREST |
(1 << R300_TX_ID_SHIFT));
if (info->cs)
bicubic_offset = 0;
else
bicubic_offset = pPriv->bicubic_src_offset;
bicubic_offset = 0;
BEGIN_ACCEL_RELOC(6, 1);
OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
@ -4132,18 +3817,13 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
while (nBox--) {
float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
#ifdef ACCEL_CP
int draw_size = 3 * pPriv->vtx_count + 4 + 2 + 3;
if (draw_size > radeon_cs_space_remaining(pScrn)) {
if (info->cs)
radeon_cs_flush_indirect(pScrn);
else
RADEONCPFlushIndirect(pScrn, 1);
radeon_cs_flush_indirect(pScrn);
if (!FUNC_NAME(R500PrepareTexturedVideo)(pScrn, pPriv))
return;
}
#endif
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@ -4167,19 +3847,13 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
((dstY + dsth - 1) << R300_SCISSOR_Y_SHIFT)));
FINISH_ACCEL();
#ifdef ACCEL_CP
BEGIN_RING(3 * pPriv->vtx_count + 4);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
3 * pPriv->vtx_count));
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
#else /* ACCEL_CP */
BEGIN_ACCEL(2 + pPriv->vtx_count * 3);
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
(3 << RADEON_VF_NUM_VERTICES_SHIFT)));
#endif
if (pPriv->bicubic_enabled) {
VTX_OUT_6((float)dstX, (float)dstY,
(float)srcX / pPriv->w, (float)srcY / pPriv->h,
@ -4210,11 +3884,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* flushing is pipelined, free/finish is not */
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
#ifdef ACCEL_CP
ADVANCE_RING();
#else
FINISH_ACCEL();
#endif /* !ACCEL_CP */
pBox++;
}

1283
src/radeon_tv.c
View file

File diff suppressed because it is too large Load diff

62
src/radeon_tv.h
View file

@ -1,62 +0,0 @@
/*
* Integrated TV out support based on the GATOS code by
* Federico Ulivi <fulivi@lycos.com>
*/
/*
* Limits of h/v positions (hPos & vPos)
*/
#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
/*
* Unit for hPos (in TV clock periods)
*/
#define H_POS_UNIT 10
/*
* Indexes in h. code timing table for horizontal line position adjustment
*/
#define H_TABLE_POS1 6
#define H_TABLE_POS2 8
/*
* Limits of hor. size (hSize)
*/
#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
/* tv standard constants */
#define NTSC_TV_CLOCK_T 233
#define NTSC_TV_VFTOTAL 1
#define NTSC_TV_LINES_PER_FRAME 525
#define NTSC_TV_ZERO_H_SIZE 479166
#define NTSC_TV_H_SIZE_UNIT 9478
#define PAL_TV_CLOCK_T 188
#define PAL_TV_VFTOTAL 3
#define PAL_TV_LINES_PER_FRAME 625
#define PAL_TV_ZERO_H_SIZE 473200
#define PAL_TV_H_SIZE_UNIT 9360
/* tv pll setting for 27 mhz ref clk */
#define NTSC_TV_PLL_M_27 22
#define NTSC_TV_PLL_N_27 175
#define NTSC_TV_PLL_P_27 5
#define PAL_TV_PLL_M_27 113
#define PAL_TV_PLL_N_27 668
#define PAL_TV_PLL_P_27 3
/* tv pll setting for 14 mhz ref clk */
#define NTSC_TV_PLL_M_14 33
#define NTSC_TV_PLL_N_14 693
#define NTSC_TV_PLL_P_14 7
#define PAL_TV_PLL_M_14 19
#define PAL_TV_PLL_N_14 353
#define PAL_TV_PLL_P_14 5
#define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe
#define FRAC_MASK 0x3fff

3
src/radeon_vbo.c
View file

@ -37,8 +37,6 @@
/* KMS vertex buffer support - for R600 only but could be used on previous gpus */
#ifdef XF86DRM_MODE
static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn);
void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
@ -210,4 +208,3 @@ again_alloc:
return bo;
}
#endif

10
src/radeon_vbo.h
View file

@ -24,9 +24,6 @@ radeon_vbo_space(ScrnInfoPtr pScrn,
struct radeon_vbo_object *vbo,
int vert_size)
{
#if defined(XF86DRM_MODE)
RADEONInfoPtr info = RADEONPTR(pScrn);
#endif
void *vb;
/* we've ran out of space in the vertex buffer - need to get a
@ -34,12 +31,7 @@ radeon_vbo_space(ScrnInfoPtr pScrn,
radeon_vbo_check(pScrn, vbo, vert_size);
vbo->vb_op_vert_size = vert_size;
#if defined(XF86DRM_MODE)
if (info->cs)
vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset);
else
#endif
vb = (pointer)((char *)vbo->vb_ptr + vbo->vb_offset);
vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset);
return vb;
}

3532
src/radeon_video.c
View file

File diff suppressed because it is too large Load diff

71
src/radeon_video.h
View file

@ -2,15 +2,8 @@
#define __RADEON_VIDEO_H__
#include "xf86i2c.h"
#include "fi1236.h"
#include "msp3430.h"
#include "tda9885.h"
#include "uda1380.h"
#include "i2c_def.h"
#include "generic_bus.h"
#include "theatre.h"
#include "xf86Crtc.h"
#include "bicubic_table.h"
@ -27,64 +20,12 @@ typedef struct {
int saturation;
int hue;
int contrast;
int red_intensity;
int green_intensity;
int blue_intensity;
/* overlay composition mode */
int alpha_mode; /* 0 = key mode, 1 = global mode */
int ov_alpha;
int gr_alpha;
/* i2c bus and devices */
I2CBusPtr i2c;
uint32_t radeon_i2c_timing;
uint32_t radeon_M;
uint32_t radeon_N;
uint32_t i2c_status;
uint32_t i2c_cntl;
FI1236Ptr fi1236;
uint8_t tuner_type;
MSP3430Ptr msp3430;
TDA9885Ptr tda9885;
UDA1380Ptr uda1380;
/* VIP bus and devices */
GENERIC_BUS_Ptr VIP;
TheatrePtr theatre;
Bool video_stream_active;
int encoding;
uint32_t frequency;
int volume;
Bool mute;
int sap_channel;
int v;
uint32_t adjustment; /* general purpose variable */
#define METHOD_BOB 0
#define METHOD_SINGLE 1
#define METHOD_WEAVE 2
#define METHOD_ADAPTIVE 3
int overlay_deinterlacing_method;
int capture_vbi_data;
int dec_brightness;
int dec_saturation;
int dec_hue;
int dec_contrast;
Bool doubleBuffer;
unsigned char currentBuffer;
RegionRec clip;
uint32_t colorKey;
uint32_t videoStatus;
Time offTime;
Time freeTime;
Bool autopaint_colorkey;
xf86CrtcPtr desired_crtc;
int size;
@ -103,8 +44,6 @@ typedef struct {
#define BICUBIC_ON 1
#define BICUBIC_AUTO 2
Atom device_id, location_id, instance_id;
/* textured video */
Bool textured;
DrawablePtr pDraw;
@ -145,14 +84,6 @@ typedef struct tagREF_TRANSFORM
#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0)
#define RTFHue(a) (((a)*3.1416)/1000.0)
void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
void RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONStopVideo(ScrnInfoPtr, pointer, Bool);
void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short,

362
src/radeon_vip.c
View file

@ -1,362 +0,0 @@
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
#include <X11/extensions/Xv.h>
#include "radeon_video.h"
#include "xf86.h"
#include "atipciids.h"
#include "generic_bus.h"
#include "theatre_reg.h"
#define VIP_NAME "RADEON VIP BUS"
#define VIP_TYPE "ATI VIP BUS"
/* Status defines */
#define VIP_BUSY 0
#define VIP_IDLE 1
#define VIP_RESET 2
static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2)
{
long count;
switch(ioctl){
case GB_IOCTL_GET_NAME:
count=strlen(VIP_NAME)+1;
if(count>arg1)return FALSE;
memcpy(arg2,VIP_NAME,count);
return TRUE;
case GB_IOCTL_GET_TYPE:
count=strlen(VIP_TYPE)+1;
if(count>arg1)return FALSE;
memcpy(arg2,VIP_TYPE,count);
return TRUE;
default:
return FALSE;
}
}
static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t timeout;
RADEONWaitForIdleMMIO(pScrn);
timeout = INREG(RADEON_VIPH_TIMEOUT_STAT);
if(timeout & RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */
{
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK);
RADEONWaitForIdleMMIO(pScrn);
return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
}
RADEONWaitForIdleMMIO(pScrn);
return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
}
static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t timeout;
RADEONWaitForIdleMMIO(pScrn);
timeout = INREG(VIPH_TIMEOUT_STAT);
if((timeout & 0x0000000f) & channel) /* lockup ?? */
{
xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "RADEON_fifo_idle\n");
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
RADEONWaitForIdleMMIO(pScrn);
return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
}
RADEONWaitForIdleMMIO(pScrn);
return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
}
/* address format:
((device & 0x3)<<14) | (fifo << 12) | (addr)
*/
#define VIP_WAIT_FOR_IDLE() { \
int i2ctries = 0; \
while (i2ctries < 10) { \
status = RADEONVIP_idle(b); \
if (status==VIP_BUSY) \
{ \
usleep(1000); \
i2ctries++; \
} else break; \
} \
}
static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status,tmp;
if((count!=1) && (count!=2) && (count!=4))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000);
write_mem_barrier();
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
disable RADEON_VIPH_REGR_DIS to enable VIP cycle.
The LSB of RADEON_VIPH_TIMEOUT_STAT are set to 0
because 1 would have acknowledged various VIP
interrupts unexpectedly
*/
RADEONWaitForIdleMMIO(pScrn);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
write_mem_barrier();
/*
the value returned here is garbage. The read merely initiates
a register cycle
*/
RADEONWaitForIdleMMIO(pScrn);
INREG(RADEON_VIPH_REG_DATA);
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
set RADEON_VIPH_REGR_DIS so that the read won't take too long.
*/
RADEONWaitForIdleMMIO(pScrn);
tmp=INREG(RADEON_VIPH_TIMEOUT_STAT);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
RADEONWaitForIdleMMIO(pScrn);
switch(count){
case 1:
*buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff);
break;
case 2:
*(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff);
break;
case 4:
*(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff);
break;
}
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
so that reading RADEON_VIPH_REG_DATA would not trigger unnecessary vip cycles.
*/
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
return TRUE;
}
static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status,tmp;
if(count!=1)
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, address | 0x3000);
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
disable VIPH_REGR_DIS to enable VIP cycle.
The LSB of VIPH_TIMEOUT_STAT are set to 0
because 1 would have acknowledged various VIP
interrupts unexpectedly
*/
RADEONWaitForIdleMMIO(pScrn);
OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
write_mem_barrier();
/*
the value returned here is garbage. The read merely initiates
a register cycle
*/
RADEONWaitForIdleMMIO(pScrn);
INREG(VIPH_REG_DATA);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
set VIPH_REGR_DIS so that the read won't take too long.
*/
RADEONWaitForIdleMMIO(pScrn);
tmp=INREG(VIPH_TIMEOUT_STAT);
OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
RADEONWaitForIdleMMIO(pScrn);
switch(count){
case 1:
*buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff);
break;
case 2:
*(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff);
break;
case 4:
*(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff);
break;
}
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
*/
OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
return TRUE;
}
static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
if((count!=4))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
RADEONWaitForFifo(pScrn, 2);
switch(count){
case 4:
OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer);
break;
}
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
return TRUE;
}
static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
uint32_t i;
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status){
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
for (i = 0; i < count; i+=4)
{
OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i));
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n");
return FALSE;
}
}
return TRUE;
}
void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONWaitForIdleMMIO(pScrn);
switch(info->ChipFamily){
case CHIP_FAMILY_RV250:
case CHIP_FAMILY_RV350:
case CHIP_FAMILY_R350:
case CHIP_FAMILY_R300:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0009); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
case CHIP_FAMILY_RV380:
OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
default:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x151);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
}
}
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
pPriv->VIP=calloc(1,sizeof(GENERIC_BUS_Rec));
pPriv->VIP->pScrn=pScrn;
pPriv->VIP->DriverPrivate.ptr=pPriv;
pPriv->VIP->ioctl=RADEONVIP_ioctl;
pPriv->VIP->read=RADEONVIP_read;
pPriv->VIP->write=RADEONVIP_write;
pPriv->VIP->fifo_read=RADEONVIP_fifo_read;
pPriv->VIP->fifo_write=RADEONVIP_fifo_write;
RADEONVIP_reset(pScrn, pPriv);
}

2211
src/theatre.c
View file

File diff suppressed because it is too large Load diff

71
src/theatre.h
View file

@ -1,71 +0,0 @@
#ifndef __THEATRE_H__
#define __THEATRE_H__
#define MODE_UNINITIALIZED 1
#define MODE_INITIALIZATION_IN_PROGRESS 2
#define MODE_INITIALIZED_FOR_TV_IN 3
typedef struct {
GENERIC_BUS_Ptr VIP;
int theatre_num;
uint32_t theatre_id;
int mode;
char* microc_path;
char* microc_type;
uint16_t video_decoder_type;
uint32_t wStandard;
uint32_t wConnector;
int iHue;
int iSaturation;
uint32_t wSaturation_U;
uint32_t wSaturation_V;
int iBrightness;
int dbBrightnessRatio;
uint32_t wSharpness;
int iContrast;
int dbContrast;
uint32_t wInterlaced;
uint32_t wTunerConnector;
uint32_t wComp0Connector;
uint32_t wSVideo0Connector;
uint32_t dwHorzScalingRatio;
uint32_t dwVertScalingRatio;
} TheatreRec, * TheatrePtr;
/* DO NOT FORGET to setup constants before calling InitTheatre */
#define xf86_InitTheatre InitTheatre
_X_EXPORT void InitTheatre(TheatrePtr t);
#define xf86_RT_SetTint RT_SetTint
_X_EXPORT void RT_SetTint (TheatrePtr t, int hue);
#define xf86_RT_SetSaturation RT_SetSaturation
_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation);
#define xf86_RT_SetBrightness RT_SetBrightness
_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness);
#define xf86_RT_SetSharpness RT_SetSharpness
_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness);
#define xf86_RT_SetContrast RT_SetContrast
_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast);
#define xf86_RT_SetInterlace RT_SetInterlace
_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace);
#define xf86_RT_SetStandard RT_SetStandard
_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard);
#define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize
_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On);
#define xf86_RT_SetConnector RT_SetConnector
_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag);
#define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout
_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t);
#define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout
_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t);
#define xf86_DumpRageTheatreRegs DumpRageTheatreRegs
_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t);
#define xf86_DumpRageTheatreRegsByName DumpRageTheatreRegsByName
_X_EXPORT void DumpRageTheatreRegsByName(TheatrePtr t);
#define xf86_ShutdownTheatre ShutdownTheatre
_X_EXPORT void ShutdownTheatre(TheatrePtr t);
#endif

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/*************************************************************************************
* Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
* software and associated documentation files (the "Software"), to deal in the Software
* without restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the author shall not be used in advertising or
* otherwise to promote the sale, use or other dealings in this Software without prior written
* authorization from the author.
*
* $Log$
* Revision 1.5 2005/12/08 17:54:40 kem
* Allow hard-coded paths to be configurable.
*
* Revision 1.4 2005/11/07 19:28:40 bogdand
* Replaced the variadic macros(gcc) by macros according to C99 standard
*
* Revision 1.3 2005/08/28 18:00:23 bogdand
* Modified the licens type from GPL to a X/MIT one
*
* Revision 1.2 2005/07/01 22:43:11 daniels
* Change all misc.h and os.h references to <X11/foo.h>.
*
*
************************************************************************************/
#ifndef __THEATRE200_H__
#define __THEATRE200_H__
#include "theatre.h"
#ifdef MICROC_DIR
#define DEFAULT_MICROC_PATH MICROC_DIR"/rt2_pmem.bin"
#else
#define DEFAULT_MICROC_PATH "/usr/X11R6/lib/modules/multimedia/rt2_pmem.bin"
#endif
#define DEFAULT_MICROC_TYPE "BINARY"
/* #define ENABLE_DEBUG 1 */
#ifdef ENABLE_DEBUG
#define ERROR_0(str) xf86DrvMsg(screen, X_ERROR, str)
#define DEBUG_0(str) xf86DrvMsg(screen, X_INFO, str)
#define ERROR(str,param1) xf86DrvMsg(screen, X_ERROR, str, param1)
#define DEBUG(str,param1) xf86DrvMsg(screen, X_INFO, str, param1)
#define ERROR_2(str,param1,param2) xf86DrvMsg(screen, X_ERROR, str, param1, param2)
#define DEBUG_2(str,param1,param2) xf86DrvMsg(screen, X_INFO, str, param1, param2)
#define ERROR_3(str,param1,param2,param3) xf86DrvMsg(screen, X_ERROR, str, param1, param2, param3)
#define DEBUG_3(str,param1,param2,param3) xf86DrvMsg(screen, X_INFO, str, param1, param2, param3)
#else
#define ERROR_0(str) (void)screen
#define DEBUG_0(str) (void)screen
#define ERROR(str,param1) (void)screen
#define DEBUG(str,param1) (void)screen
#define ERROR_2(str,param1,param2) (void)screen
#define DEBUG_2(str,param1,param2) (void)screen
#define ERROR_3(str,param1,param2,param3) (void)screen
#define DEBUG_3(str,param1,param2,param3) (void)screen
#endif
#define DSP_OK 0x21
#define DSP_INVALID_PARAMETER 0x22
#define DSP_MISSING_PARAMETER 0x23
#define DSP_UNKNOWN_COMMAND 0x24
#define DSP_UNSUCCESS 0x25
#define DSP_BUSY 0x26
#define DSP_RESET_REQUIRED 0x27
#define DSP_UNKNOWN_RESULT 0x28
#define DSP_CRC_ERROR 0x29
#define DSP_AUDIO_GAIN_ADJ_FAIL 0x2a
#define DSP_AUDIO_GAIN_CHK_ERROR 0x2b
#define DSP_WARNING 0x2c
#define DSP_POWERDOWN_MODE 0x2d
#define RT200_NTSC_M 0x01
#define RT200_NTSC_433 0x03
#define RT200_NTSC_J 0x04
#define RT200_PAL_B 0x05
#define RT200_PAL_D 0x06
#define RT200_PAL_G 0x07
#define RT200_PAL_H 0x08
#define RT200_PAL_I 0x09
#define RT200_PAL_N 0x0a
#define RT200_PAL_Ncomb 0x0b
#define RT200_PAL_M 0x0c
#define RT200_PAL_60 0x0d
#define RT200_SECAM 0x0e
#define RT200_SECAM_B 0x0f
#define RT200_SECAM_D 0x10
#define RT200_SECAM_G 0x11
#define RT200_SECAM_H 0x12
#define RT200_SECAM_K 0x13
#define RT200_SECAM_K1 0x14
#define RT200_SECAM_L 0x15
#define RT200_SECAM_L1 0x16
#define RT200_480i 0x17
#define RT200_480p 0x18
#define RT200_576i 0x19
#define RT200_720p 0x1a
#define RT200_1080i 0x1b
struct rt200_microc_head
{
unsigned int device_id;
unsigned int vendor_id;
unsigned int revision_id;
unsigned int num_seg;
};
struct rt200_microc_seg
{
unsigned int num_bytes;
unsigned int download_dst;
unsigned int crc_val;
unsigned char* data;
struct rt200_microc_seg* next;
};
struct rt200_microc_data
{
struct rt200_microc_head microc_head;
struct rt200_microc_seg* microc_seg_list;
};
#endif

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src/theatre200_module.c
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(theatre200Setup);
static XF86ModuleVersionInfo theatre200VersRec =
{
"theatre200",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{0,0,0,0}
};
_X_EXPORT XF86ModuleData theatre200ModuleData = {
&theatre200VersRec,
theatre200Setup,
NULL
};
static pointer
theatre200Setup(pointer module, pointer opts, int *errmaj, int *errmin) {
return (pointer)1;
}

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src/theatre_detect.c
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/*************************************************************************************
*
* Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
* software and associated documentation files (the "Software"), to deal in the Software
* without restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the author shall not be used in advertising or
* otherwise to promote the sale, use or other dealings in this Software without prior written
* authorization from the author.
*
* $Log$
* Revision 1.4 2005/08/28 18:00:23 bogdand
* Modified the licens type from GPL to a X/MIT one
*
* Revision 1.3 2005/07/11 02:29:45 ajax
* Prep for modular builds by adding guarded #include "config.h" everywhere.
*
* Revision 1.2 2005/07/01 22:43:11 daniels
* Change all misc.h and os.h references to <X11/foo.h>.
*
*
************************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include "xf86.h"
#include "generic_bus.h"
#include "theatre.h"
#include "theatre_reg.h"
#include "theatre_detect.h"
static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data)
{
if(t->theatre_num<0)return FALSE;
return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data);
}
/* Unused code - reference */
#if 0
static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data)
{
if(t->theatre_num<0)return FALSE;
return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data);
}
#define RT_regw(reg,data) theatre_write(t,(reg),(data))
#endif
#define RT_regr(reg,data) theatre_read(t,(reg),(data))
#define VIP_TYPE "ATI VIP BUS"
_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
{
TheatrePtr t;
int i;
uint32_t val;
char s[20];
b->ioctl(b,GB_IOCTL_GET_TYPE,20,s);
if(strcmp(VIP_TYPE, s)){
xf86DrvMsg(b->pScrn->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n",
VIP_TYPE, s);
return NULL;
}
t = calloc(1,sizeof(TheatreRec));
t->VIP = b;
t->theatre_num = -1;
t->mode=MODE_UNINITIALIZED;
b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val);
for(i=0;i<4;i++)
{
if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val))
{
if(val)xf86DrvMsg(b->pScrn->scrnIndex, X_INFO,
"Device %d on VIP bus ids as 0x%08x\n", i,
(unsigned)val);
if(t->theatre_num>=0)continue; /* already found one instance */
switch(val){
case RT100_ATI_ID:
t->theatre_num=i;
t->theatre_id=RT100_ATI_ID;
break;
case RT200_ATI_ID:
t->theatre_num=i;
t->theatre_id=RT200_ATI_ID;
break;
}
} else {
xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i);
}
}
if(t->theatre_num>=0)xf86DrvMsg(b->pScrn->scrnIndex, X_INFO,
"Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",
t->theatre_num, (unsigned)t->theatre_id);
if(t->theatre_num < 0)
{
free(t);
return NULL;
}
RT_regr(VIP_VIP_REVISION_ID, &val);
xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n",
(unsigned)val);
#if 0
DumpRageTheatreRegsByName(t);
#endif
return t;
}

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src/theatre_detect.h
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@ -1,46 +0,0 @@
/*************************************************************************************
* Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
* software and associated documentation files (the "Software"), to deal in the Software
* without restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the author shall not be used in advertising or
* otherwise to promote the sale, use or other dealings in this Software without prior written
* authorization from the author.
*
* $Log$
* Revision 1.3 2005/08/28 18:00:23 bogdand
* Modified the licens type from GPL to a X/MIT one
*
* Revision 1.2 2005/07/01 22:43:11 daniels
* Change all misc.h and os.h references to <X11/foo.h>.
*
*
************************************************************************************/
#ifndef __THEATRE_DETECT_H__
#define __THEATRE_DETECT_H__
/*
* Created by Bogdan D. bogdand@users.sourceforge.net
*/
#define xf86_DetectTheatre DetectTheatre
_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b);
#endif

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src/theatre_detect_module.c
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/*
* Created by Bogdan D. bogdand@users.sourceforge.net
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(theatre_detectSetup);
static XF86ModuleVersionInfo theatre_detectVersRec =
{
"theatre_detect",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{0,0,0,0}
};
_X_EXPORT XF86ModuleData theatre_detectModuleData = {
&theatre_detectVersRec,
theatre_detectSetup,
NULL
};
static pointer
theatre_detectSetup(pointer module, pointer opts, int *errmaj, int *errmin) {
return (pointer)1;
}

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src/theatre_module.c
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#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(theatreSetup);
static XF86ModuleVersionInfo theatreVersRec =
{
"theatre",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{0,0,0,0}
};
_X_EXPORT XF86ModuleData theatreModuleData = {
&theatreVersRec,
theatreSetup,
NULL
};
static pointer
theatreSetup(pointer module, pointer opts, int *errmaj, int *errmin) {
return (pointer)1;
}

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src/theatre_reg.h
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#ifndef __THEATRE_REGS_H__
#define __THEATRE_REGS_H__
#define VIPH_CH0_DATA 0x0c00
#define VIPH_CH1_DATA 0x0c04
#define VIPH_CH2_DATA 0x0c08
#define VIPH_CH3_DATA 0x0c0c
#define VIPH_CH0_ADDR 0x0c10
#define VIPH_CH1_ADDR 0x0c14
#define VIPH_CH2_ADDR 0x0c18
#define VIPH_CH3_ADDR 0x0c1c
#define VIPH_CH0_SBCNT 0x0c20
#define VIPH_CH1_SBCNT 0x0c24
#define VIPH_CH2_SBCNT 0x0c28
#define VIPH_CH3_SBCNT 0x0c2c
#define VIPH_CH0_ABCNT 0x0c30
#define VIPH_CH1_ABCNT 0x0c34
#define VIPH_CH2_ABCNT 0x0c38
#define VIPH_CH3_ABCNT 0x0c3c
#define VIPH_CONTROL 0x0c40
#define VIPH_DV_LAT 0x0c44
#define VIPH_BM_CHUNK 0x0c48
#define VIPH_DV_INT 0x0c4c
#define VIPH_TIMEOUT_STAT 0x0c50
#define VIPH_REG_DATA 0x0084
#define VIPH_REG_ADDR 0x0080
/* Address Space Rage Theatre Registers (VIP Access) */
#define VIP_VIP_VENDOR_DEVICE_ID 0x0000
#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004
#define VIP_VIP_COMMAND_STATUS 0x0008
#define VIP_VIP_REVISION_ID 0x000c
#define VIP_HW_DEBUG 0x0010
#define VIP_SW_SCRATCH 0x0014
#define VIP_I2C_CNTL_0 0x0020
#define VIP_I2C_CNTL_1 0x0024
#define VIP_I2C_DATA 0x0028
#define VIP_INT_CNTL 0x002c
/* RT200 */
#define VIP_INT_CNTL__FB_INT0 0x02000000
#define VIP_INT_CNTL__FB_INT0_CLR 0x02000000
#define VIP_GPIO_INOUT 0x0030
#define VIP_GPIO_CNTL 0x0034
#define VIP_CLKOUT_GPIO_CNTL 0x0038
#define VIP_RIPINTF_PORT_CNTL 0x003c
/* RT200 */
#define VIP_GPIO_INOUT 0x0030
#define VIP_GPIO_CNTL 0x0034
#define VIP_HOSTINTF_PORT_CNTL 0x003c
#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008
#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080
#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100
#define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000
#define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000
#define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000
#define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000
#define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000
#define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000
#define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000
/* RT200 */
#define VIP_DSP_PLL_CNTL 0x0bc
/* RT200 */
#define VIP_TC_SOURCE 0x300
#define VIP_TC_DESTINATION 0x304
#define VIP_TC_COMMAND 0x308
/* RT200 */
#define VIP_TC_STATUS 0x030c
#define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff
#define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000
#define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000
#define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000
#define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000
#define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000
#define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000
#define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000
#define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000
#define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000
#define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000
/* RT200 */
#define VIP_TC_DOWNLOAD 0x0310
#define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff
#define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000
/* RT200 */
#define VIP_FB_INT 0x0314
#define VIP_FB_INT__INT_7 0x00000080
#define VIP_FB_SCRATCH0 0x0318
#define VIP_FB_SCRATCH1 0x031c
#define VIP_ADC_CNTL 0x0400
#define VIP_ADC_DEBUG 0x0404
#define VIP_STANDARD_SELECT 0x0408
#define VIP_THERMO2BIN_STATUS 0x040c
#define VIP_COMB_CNTL0 0x0440
#define VIP_COMB_CNTL1 0x0444
#define VIP_COMB_CNTL2 0x0448
#define VIP_COMB_LINE_LENGTH 0x044c
#define VIP_NOISE_CNTL0 0x0450
#define VIP_HS_PLINE 0x0480
#define VIP_HS_DTOINC 0x0484
#define VIP_HS_PLLGAIN 0x0488
#define VIP_HS_MINMAXWIDTH 0x048c
#define VIP_HS_GENLOCKDELAY 0x0490
#define VIP_HS_WINDOW_LIMIT 0x0494
#define VIP_HS_WINDOW_OC_SPEED 0x0498
#define VIP_HS_PULSE_WIDTH 0x049c
#define VIP_HS_PLL_ERROR 0x04a0
#define VIP_HS_PLL_FS_PATH 0x04a4
#define VIP_SG_BLACK_GATE 0x04c0
#define VIP_SG_SYNCTIP_GATE 0x04c4
#define VIP_SG_UVGATE_GATE 0x04c8
#define VIP_LP_AGC_CLAMP_CNTL0 0x0500
#define VIP_LP_AGC_CLAMP_CNTL1 0x0504
#define VIP_LP_BRIGHTNESS 0x0508
#define VIP_LP_CONTRAST 0x050c
#define VIP_LP_SLICE_LIMIT 0x0510
#define VIP_LP_WPA_CNTL0 0x0514
#define VIP_LP_WPA_CNTL1 0x0518
#define VIP_LP_BLACK_LEVEL 0x051c
#define VIP_LP_SLICE_LEVEL 0x0520
#define VIP_LP_SYNCTIP_LEVEL 0x0524
#define VIP_LP_VERT_LOCKOUT 0x0528
#define VIP_VS_DETECTOR_CNTL 0x0540
#define VIP_VS_BLANKING_CNTL 0x0544
#define VIP_VS_FIELD_ID_CNTL 0x0548
#define VIP_VS_COUNTER_CNTL 0x054c
#define VIP_VS_FRAME_TOTAL 0x0550
#define VIP_VS_LINE_COUNT 0x0554
#define VIP_CP_PLL_CNTL0 0x0580
#define VIP_CP_PLL_CNTL1 0x0584
#define VIP_CP_HUE_CNTL 0x0588
#define VIP_CP_BURST_GAIN 0x058c
#define VIP_CP_AGC_CNTL 0x0590
#define VIP_CP_ACTIVE_GAIN 0x0594
#define VIP_CP_PLL_STATUS0 0x0598
#define VIP_CP_PLL_STATUS1 0x059c
#define VIP_CP_PLL_STATUS2 0x05a0
#define VIP_CP_PLL_STATUS3 0x05a4
#define VIP_CP_PLL_STATUS4 0x05a8
#define VIP_CP_PLL_STATUS5 0x05ac
#define VIP_CP_PLL_STATUS6 0x05b0
#define VIP_CP_PLL_STATUS7 0x05b4
#define VIP_CP_DEBUG_FORCE 0x05b8
#define VIP_CP_VERT_LOCKOUT 0x05bc
#define VIP_H_ACTIVE_WINDOW 0x05c0
#define VIP_V_ACTIVE_WINDOW 0x05c4
#define VIP_H_VBI_WINDOW 0x05c8
#define VIP_V_VBI_WINDOW 0x05cc
#define VIP_VBI_CONTROL 0x05d0
#define VIP_DECODER_DEBUG_CNTL 0x05d4
#define VIP_SINGLE_STEP_DATA 0x05d8
#define VIP_MASTER_CNTL 0x0040
#define VIP_RGB_CNTL 0x0048
#define VIP_CLKOUT_CNTL 0x004c
#define VIP_SYNC_CNTL 0x0050
#define VIP_I2C_CNTL 0x0054
#define VIP_HTOTAL 0x0080
#define VIP_HDISP 0x0084
#define VIP_HSIZE 0x0088
#define VIP_HSTART 0x008c
#define VIP_HCOUNT 0x0090
#define VIP_VTOTAL 0x0094
#define VIP_VDISP 0x0098
#define VIP_VCOUNT 0x009c
#define VIP_VFTOTAL 0x00a0
#define VIP_DFCOUNT 0x00a4
#define VIP_DFRESTART 0x00a8
#define VIP_DHRESTART 0x00ac
#define VIP_DVRESTART 0x00b0
#define VIP_SYNC_SIZE 0x00b4
#define VIP_TV_PLL_FINE_CNTL 0x00b8
#define VIP_CRT_PLL_FINE_CNTL 0x00bc
#define VIP_TV_PLL_CNTL 0x00c0
#define VIP_CRT_PLL_CNTL 0x00c4
#define VIP_PLL_CNTL0 0x00c8
#define VIP_PLL_TEST_CNTL 0x00cc
#define VIP_CLOCK_SEL_CNTL 0x00d0
#define VIP_VIN_PLL_CNTL 0x00d4
#define VIP_VIN_PLL_FINE_CNTL 0x00d8
#define VIP_AUD_PLL_CNTL 0x00e0
#define VIP_AUD_PLL_FINE_CNTL 0x00e4
#define VIP_AUD_CLK_DIVIDERS 0x00e8
#define VIP_AUD_DTO_INCREMENTS 0x00ec
#define VIP_L54_PLL_CNTL 0x00f0
#define VIP_L54_PLL_FINE_CNTL 0x00f4
#define VIP_L54_DTO_INCREMENTS 0x00f8
#define VIP_PLL_CNTL1 0x00fc
#define VIP_FRAME_LOCK_CNTL 0x0100
#define VIP_SYNC_LOCK_CNTL 0x0104
#define VIP_TVO_SYNC_PAT_ACCUM 0x0108
#define VIP_TVO_SYNC_THRESHOLD 0x010c
#define VIP_TVO_SYNC_PAT_EXPECT 0x0110
#define VIP_DELAY_ONE_MAP_A 0x0114
#define VIP_DELAY_ONE_MAP_B 0x0118
#define VIP_DELAY_ZERO_MAP_A 0x011c
#define VIP_DELAY_ZERO_MAP_B 0x0120
#define VIP_TVO_DATA_DELAY_A 0x0140
#define VIP_TVO_DATA_DELAY_B 0x0144
#define VIP_HOST_READ_DATA 0x0180
#define VIP_HOST_WRITE_DATA 0x0184
#define VIP_HOST_RD_WT_CNTL 0x0188
#define VIP_VSCALER_CNTL1 0x01c0
#define VIP_TIMING_CNTL 0x01c4
#define VIP_VSCALER_CNTL2 0x01c8
#define VIP_Y_FALL_CNTL 0x01cc
#define VIP_Y_RISE_CNTL 0x01d0
#define VIP_Y_SAW_TOOTH_CNTL 0x01d4
#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0
#define VIP_GAIN_LIMIT_SETTINGS 0x01e4
#define VIP_LINEAR_GAIN_SETTINGS 0x01e8
#define VIP_MODULATOR_CNTL1 0x0200
#define VIP_MODULATOR_CNTL2 0x0204
#define VIP_MV_MODE_CNTL 0x0208
#define VIP_MV_STRIPE_CNTL 0x020c
#define VIP_MV_LEVEL_CNTL1 0x0210
#define VIP_MV_LEVEL_CNTL2 0x0214
#define VIP_PRE_DAC_MUX_CNTL 0x0240
#define VIP_TV_DAC_CNTL 0x0280
#define VIP_CRC_CNTL 0x02c0
#define VIP_VIDEO_PORT_SIG 0x02c4
#define VIP_VBI_CC_CNTL 0x02c8
#define VIP_VBI_EDS_CNTL 0x02cc
#define VIP_VBI_20BIT_CNTL 0x02d0
#define VIP_VBI_DTO_CNTL 0x02d4
#define VIP_VBI_LEVEL_CNTL 0x02d8
#define VIP_UV_ADR 0x0300
#define VIP_MV_STATUS 0x0330
#define VIP_UPSAMP_COEFF0_0 0x0340
#define VIP_UPSAMP_COEFF0_1 0x0344
#define VIP_UPSAMP_COEFF0_2 0x0348
#define VIP_UPSAMP_COEFF1_0 0x034c
#define VIP_UPSAMP_COEFF1_1 0x0350
#define VIP_UPSAMP_COEFF1_2 0x0354
#define VIP_UPSAMP_COEFF2_0 0x0358
#define VIP_UPSAMP_COEFF2_1 0x035c
#define VIP_UPSAMP_COEFF2_2 0x0360
#define VIP_UPSAMP_COEFF3_0 0x0364
#define VIP_UPSAMP_COEFF3_1 0x0368
#define VIP_UPSAMP_COEFF3_2 0x036c
#define VIP_UPSAMP_COEFF4_0 0x0370
#define VIP_UPSAMP_COEFF4_1 0x0374
#define VIP_UPSAMP_COEFF4_2 0x0378
#define VIP_TV_DTO_INCREMENTS 0x0390
#define VIP_CRT_DTO_INCREMENTS 0x0394
#define VIP_VSYNC_DIFF_CNTL 0x03a0
#define VIP_VSYNC_DIFF_LIMITS 0x03a4
#define VIP_VSYNC_DIFF_RD_DATA 0x03a8
#define VIP_SCALER_IN_WINDOW 0x0618
#define VIP_SCALER_OUT_WINDOW 0x061c
#define VIP_H_SCALER_CONTROL 0x0600
#define VIP_V_SCALER_CONTROL 0x0604
#define VIP_V_DEINTERLACE_CONTROL 0x0608
#define VIP_VBI_SCALER_CONTROL 0x060c
#define VIP_DVS_PORT_CTRL 0x0610
#define VIP_DVS_PORT_READBACK 0x0614
#define VIP_FIFOA_CONFIG 0x0800
#define VIP_FIFOB_CONFIG 0x0804
#define VIP_FIFOC_CONFIG 0x0808
#define VIP_SPDIF_PORT_CNTL 0x080c
#define VIP_SPDIF_CHANNEL_STAT 0x0810
#define VIP_SPDIF_AC3_PREAMBLE 0x0814
#define VIP_I2S_TRANSMIT_CNTL 0x0818
#define VIP_I2S_RECEIVE_CNTL 0x081c
#define VIP_SPDIF_TX_CNT_REG 0x0820
#define VIP_IIS_TX_CNT_REG 0x0824
/* Status defines */
#define VIP_BUSY 0
#define VIP_IDLE 1
#define VIP_RESET 2
#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT 0x00000001
#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK 0x00000001
#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT 0x00000002
#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK 0x00000002
#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT 0x00000004
#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK 0x00000004
#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT 0x00000008
#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK 0x00000008
#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
#define RT100_ATI_ID 0x4D541002
#define RT200_ATI_ID 0x4d4a1002
/* Register/Field values: */
#define RT_COMP0 0x0
#define RT_COMP1 0x1
#define RT_COMP2 0x2
#define RT_YF_COMP3 0x3
#define RT_YR_COMP3 0x4
#define RT_YCF_COMP4 0x5
#define RT_YCR_COMP4 0x6
/* Video standard defines */
#define RT_NTSC 0x0
#define RT_PAL 0x1
#define RT_SECAM 0x2
#define extNONE 0x0000
#define extNTSC 0x0100
#define extRsvd 0x0200
#define extPAL 0x0300
#define extPAL_M 0x0400
#define extPAL_N 0x0500
#define extSECAM 0x0600
#define extPAL_NCOMB 0x0700
#define extNTSC_J 0x0800
#define extNTSC_443 0x0900
#define extPAL_BGHI 0x0A00
#define extPAL_60 0x0B00
/* these are used in MSP3430 */
#define extPAL_DK1 0x0C00
#define extPAL_AUTO 0x0D00
/* these are used in RT200. Some are defined above */
#define extPAL_B 0x0E00
#define extPAL_D 0x0F00
#define extPAL_G 0x1000
#define extPAL_H 0x1100
#define extPAL_I 0x1200
#define extSECAM_B 0x1300
#define extSECAM_D 0x1400
#define extSECAM_G 0x1500
#define extSECAM_H 0x1600
#define extSECAM_K 0x1700
#define extSECAM_K1 0x1800
#define extSECAM_L 0x1900
#define extSECAM_L1 0x1A00
#define RT_FREF_2700 6
#define RT_FREF_2950 5
#define RT_COMPOSITE 0x0
#define RT_SVIDEO 0x1
#define RT_NORM_SHARPNESS 0x03
#define RT_HIGH_SHARPNESS 0x0F
#define RT_HUE_PAL_DEF 0x00
#define RT_DECINTERLACED 0x1
#define RT_DECNONINTERLACED 0x0
#define NTSC_LINES 525
#define PAL_SECAM_LINES 625
#define RT_ASYNC_ENABLE 0x0
#define RT_ASYNC_DISABLE 0x1
#define RT_ASYNC_RESET 0x1
#define RT_VINRST_ACTIVE 0x0
#define RT_VINRST_RESET 0x1
#define RT_L54RST_RESET 0x1
#define RT_REF_CLK 0x0
#define RT_PLL_VIN_CLK 0x1
#define RT_VIN_ASYNC_RST 0x20
#define RT_DVS_ASYNC_RST 0x80
#define RT_ADC_ENABLE 0x0
#define RT_ADC_DISABLE 0x1
#define RT_DVSDIR_IN 0x0
#define RT_DVSDIR_OUT 0x1
#define RT_DVSCLK_HIGH 0x0
#define RT_DVSCLK_LOW 0x1
#define RT_DVSCLK_SEL_8FS 0x0
#define RT_DVSCLK_SEL_27MHZ 0x1
#define RT_DVS_CONTSTREAM 0x1
#define RT_DVS_NONCONTSTREAM 0x0
#define RT_DVSDAT_HIGH 0x0
#define RT_DVSDAT_LOW 0x1
#define RT_ADC_CNTL_DEFAULT 0x03252338
/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 /* was 0x09438090 */
#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000
#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090
#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090
#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/
#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090
#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090
#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090
#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090
#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090
/* End of filter settings. */
/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010
#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081
#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010
#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1
#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091
#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081
#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010
#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1
#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010
#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1
/* End of filter settings. */
/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010
#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF
#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */
#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102
#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */
#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102
#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102
#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102
#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102
#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102
/* End of filter settings. */
/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */
#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A
#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A
#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B
#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B
#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A
#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A
#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391
#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391
#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389
#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389
/* End of filter settings. */
/* LP_AGC_CLAMP_CNTL0 */
#define RT_NTSCM_SYNCTIP_REF0 0x00000037
#define RT_NTSCM_SYNCTIP_REF1 0x00000029
#define RT_NTSCM_CLAMP_REF 0x0000003B
#define RT_NTSCM_PEAKWHITE 0x000000FF
#define RT_NTSCM_VBI_PEAKWHITE 0x000000D2 /* was 0xc2 - docs say d2 */
#define RT_NTSCM_WPA_THRESHOLD 0x00000406
#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3
#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B
#define RT_NTSCM_LP_LOCKOUT_START 0x00000206
#define RT_NTSCM_LP_LOCKOUT_END 0x00000021
#define RT_NTSCM_CH_DTO_INC 0x00400000
#define RT_NTSCM_CH_PLL_SGAIN 0x00000001
#define RT_NTSCM_CH_PLL_FGAIN 0x00000002
#define RT_NTSCM_CR_BURST_GAIN 0x0000007A
#define RT_NTSCM_CB_BURST_GAIN 0x000000AC
#define RT_NTSCM_CH_HEIGHT 0x000000CD
#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0
#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002
#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000
#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000
#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A
#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC
#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207
#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E
#define RT_NTSCJ_SYNCTIP_REF0 0x00000004
#define RT_NTSCJ_SYNCTIP_REF1 0x00000012
#define RT_NTSCJ_CLAMP_REF 0x0000003B
#define RT_NTSCJ_PEAKWHITE 0x000000CB
#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2
#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0
#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4
#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C
#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206
#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021
#define RT_NTSCJ_CR_BURST_GAIN 0x00000071
#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F
#define RT_NTSCJ_CH_HEIGHT 0x000000CD
#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0
#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002
#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000
#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000
#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071
#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F
#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207
#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E
#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
#define RT_PAL_CLAMP_REF 0x0000003B
#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */
#define RT_PAL_WPA_TRIGGER_LO 0x00000096
#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2
#define RT_PAL_LP_LOCKOUT_START 0x00000263
#define RT_PAL_LP_LOCKOUT_END 0x0000002C
#define RT_PAL_CH_DTO_INC 0x00400000
#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */
#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */
#define RT_PAL_CR_BURST_GAIN 0x0000007A
#define RT_PAL_CB_BURST_GAIN 0x000000AB
#define RT_PAL_CH_HEIGHT 0x0000009C
#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */
#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */
#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */
#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000
#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */
#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */
#define RT_PAL_VERT_LOCKOUT_START 0x00000269
#define RT_PAL_VERT_LOCKOUT_END 0x00000012
#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
#define RT_SECAM_CLAMP_REF 0x0000003B
#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/
#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */
#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2
#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */
#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */
#define RT_SECAM_CH_DTO_INC 0x003E7A28
#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 - Volodya */
#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */
#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
#define RT_SECAM_CH_HEIGHT 0x00000066
#define RT_SECAM_CH_KILL_LEVEL 0x00000060
#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003
#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000
#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000
#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */
#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */
#define RT_SECAM_VERT_LOCKOUT_START 0x00000269
#define RT_SECAM_VERT_LOCKOUT_END 0x00000012
#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/
#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000a
#define RT_NTSCM_FIELD_IDLOCATION 0x00000105
#define RT_PAL_FIELD_IDLOCATION 0x00000137
#define RT_NTSCM_H_ACTIVE_START 0x00000070
#define RT_NTSCM_H_ACTIVE_END 0x00000363
#define RT_PAL_H_ACTIVE_START 0x0000009A
#define RT_PAL_H_ACTIVE_END 0x00000439
#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1)
#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1)
#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */
#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */
/* VBI */
#define RT_NTSCM_H_VBI_WIND_START 0x32 /* instead of 0x00000049 - V.D. */
#define RT_NTSCM_H_VBI_WIND_END 0x367 /* instead of 0x00000366 - V.D. */
#define RT_PAL_H_VBI_WIND_START 0x00000084
#define RT_PAL_H_VBI_WIND_END 0x0000041F
#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def
#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def
#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */
#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */
#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */
#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */
#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */
#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA
#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353
#define RT_NTSCM_VSYNC_INT_HOLD 0x17
#define RT_PALSEM_VSYNC_INT_HOLD 0x1C
#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */
#define RT_FIELD_FLIP_EN 0x4
#define RT_V_FIELD_FLIP_INVERTED 0x2000
#define RT_NTSCM_H_IN_START 0x70
#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */
#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */
#define RT_NTSC_H_ACTIVE_SIZE 744
#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */
#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */
#define RT_NTSCM_V_IN_START (0x23)
#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */
#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */
#define RT_NTSCM_V_ACTIVE_SIZE 480
#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */
#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */
#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D
#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D
#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F
#define RT_PALM_WIN_CLOSE_LIMIT 0x4D
#define RT_PALN_WIN_CLOSE_LIMIT 0x5F
#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */
#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
#define RT_NTSCM_HS_PLL_SGAIN 0x5
#define RT_NTSCM_HS_PLL_FGAIN 0x7
#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4
#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0
#define TV 0x1
#define LINEIN 0x2
#define MUTE 0x3
#define DEC_COMPOSITE 0
#define DEC_SVIDEO 1
#define DEC_TUNER 2
#define DEC_NTSC 0
#define DEC_PAL 1
#define DEC_SECAM 2
#define DEC_NTSC_J 8
#define DEC_SMOOTH 0
#define DEC_SHARP 1
/* RT Register Field Defaults: */
#define fld_tmpReg1_def (uint32_t) 0x00000000
#define fld_tmpReg2_def (uint32_t) 0x00000001
#define fld_tmpReg3_def (uint32_t) 0x00000002
#define fld_LP_CONTRAST_def (uint32_t) 0x0000006e
#define fld_LP_BRIGHTNESS_def (uint32_t) 0x00003ff0
#define fld_CP_HUE_CNTL_def (uint32_t) 0x00000000
#define fld_LUMA_FILTER_def (uint32_t) 0x00000001
#define fld_H_SCALE_RATIO_def (uint32_t) 0x00010000
#define fld_H_SHARPNESS_def (uint32_t) 0x00000000
#define fld_V_SCALE_RATIO_def (uint32_t) 0x00000800
#define fld_V_DEINTERLACE_ON_def (uint32_t) 0x00000001
#define fld_V_BYPSS_def (uint32_t) 0x00000000
#define fld_V_DITHER_ON_def (uint32_t) 0x00000001
#define fld_EVENF_OFFSET_def (uint32_t) 0x00000000
#define fld_ODDF_OFFSET_def (uint32_t) 0x00000000
#define fld_INTERLACE_DETECTED_def (uint32_t) 0x00000000
#define fld_VS_LINE_COUNT_def (uint32_t) 0x00000000
#define fld_VS_DETECTED_LINES_def (uint32_t) 0x00000000
#define fld_VS_ITU656_VB_def (uint32_t) 0x00000000
#define fld_VBI_CC_DATA_def (uint32_t) 0x00000000
#define fld_VBI_CC_WT_def (uint32_t) 0x00000000
#define fld_VBI_CC_WT_ACK_def (uint32_t) 0x00000000
#define fld_VBI_CC_HOLD_def (uint32_t) 0x00000000
#define fld_VBI_DECODE_EN_def (uint32_t) 0x00000000
#define fld_VBI_CC_DTO_P_def (uint32_t) 0x00001802
#define fld_VBI_20BIT_DTO_P_def (uint32_t) 0x0000155c
#define fld_VBI_CC_LEVEL_def (uint32_t) 0x0000003f
#define fld_VBI_20BIT_LEVEL_def (uint32_t) 0x00000059
#define fld_VBI_CLK_RUNIN_GAIN_def (uint32_t) 0x0000010f
#define fld_H_VBI_WIND_START_def (uint32_t) 0x00000041
#define fld_H_VBI_WIND_END_def (uint32_t) 0x00000366
#define fld_V_VBI_WIND_START_def (uint32_t) 0x0B /* instead of 0x0D - V.D. */
#define fld_V_VBI_WIND_END_def (uint32_t) 0x24
#define fld_VBI_20BIT_DATA0_def (uint32_t) 0x00000000
#define fld_VBI_20BIT_DATA1_def (uint32_t) 0x00000000
#define fld_VBI_20BIT_WT_def (uint32_t) 0x00000000
#define fld_VBI_20BIT_WT_ACK_def (uint32_t) 0x00000000
#define fld_VBI_20BIT_HOLD_def (uint32_t) 0x00000000
#define fld_VBI_CAPTURE_ENABLE_def (uint32_t) 0x00000000
#define fld_VBI_EDS_DATA_def (uint32_t) 0x00000000
#define fld_VBI_EDS_WT_def (uint32_t) 0x00000000
#define fld_VBI_EDS_WT_ACK_def (uint32_t) 0x00000000
#define fld_VBI_EDS_HOLD_def (uint32_t) 0x00000000
#define fld_VBI_SCALING_RATIO_def (uint32_t) 0x00010000
#define fld_VBI_ALIGNER_ENABLE_def (uint32_t) 0x00000000
#define fld_H_ACTIVE_START_def (uint32_t) 0x00000070
#define fld_H_ACTIVE_END_def (uint32_t) 0x000002f0
#define fld_V_ACTIVE_START_def (uint32_t) ((22-4)*2+1)
#define fld_V_ACTIVE_END_def (uint32_t) ((22+240-4)*2+2)
#define fld_CH_HEIGHT_def (uint32_t) 0x000000CD
#define fld_CH_KILL_LEVEL_def (uint32_t) 0x000000C0
#define fld_CH_AGC_ERROR_LIM_def (uint32_t) 0x00000002
#define fld_CH_AGC_FILTER_EN_def (uint32_t) 0x00000000
#define fld_CH_AGC_LOOP_SPEED_def (uint32_t) 0x00000000
#define fld_HUE_ADJ_def (uint32_t) 0x00000000
#define fld_STANDARD_SEL_def (uint32_t) 0x00000000
#define fld_STANDARD_YC_def (uint32_t) 0x00000000
#define fld_ADC_PDWN_def (uint32_t) 0x00000001
#define fld_INPUT_SELECT_def (uint32_t) 0x00000000
#define fld_ADC_PREFLO_def (uint32_t) 0x00000003
#define fld_H_SYNC_PULSE_WIDTH_def (uint32_t) 0x00000000
#define fld_HS_GENLOCKED_def (uint32_t) 0x00000000
#define fld_HS_SYNC_IN_WIN_def (uint32_t) 0x00000000
#define fld_VIN_ASYNC_RST_def (uint32_t) 0x00000001
#define fld_DVS_ASYNC_RST_def (uint32_t) 0x00000001
/* Vendor IDs: */
#define fld_VIP_VENDOR_ID_def (uint32_t) 0x00001002
#define fld_VIP_DEVICE_ID_def (uint32_t) 0x00004d54
#define fld_VIP_REVISION_ID_def (uint32_t) 0x00000001
/* AGC Delay Register */
#define fld_BLACK_INT_START_def (uint32_t) 0x00000031
#define fld_BLACK_INT_LENGTH_def (uint32_t) 0x0000000f
#define fld_UV_INT_START_def (uint32_t) 0x0000003b
#define fld_U_INT_LENGTH_def (uint32_t) 0x0000000f
#define fld_V_INT_LENGTH_def (uint32_t) 0x0000000f
#define fld_CRDR_ACTIVE_GAIN_def (uint32_t) 0x0000007a
#define fld_CBDB_ACTIVE_GAIN_def (uint32_t) 0x000000ac
#define fld_DVS_DIRECTION_def (uint32_t) 0x00000000
#define fld_DVS_VBI_UINT8_SWAP_def (uint32_t) 0x00000000
#define fld_DVS_CLK_SELECT_def (uint32_t) 0x00000000
#define fld_CONTINUOUS_STREAM_def (uint32_t) 0x00000000
#define fld_DVSOUT_CLK_DRV_def (uint32_t) 0x00000001
#define fld_DVSOUT_DATA_DRV_def (uint32_t) 0x00000001
#define fld_COMB_CNTL0_def (uint32_t) 0x09438090
#define fld_COMB_CNTL1_def (uint32_t) 0x00000010
#define fld_COMB_CNTL2_def (uint32_t) 0x16161010
#define fld_COMB_LENGTH_def (uint32_t) 0x0718038A
#define fld_SYNCTIP_REF0_def (uint32_t) 0x00000037
#define fld_SYNCTIP_REF1_def (uint32_t) 0x00000029
#define fld_CLAMP_REF_def (uint32_t) 0x0000003B
#define fld_AGC_PEAKWHITE_def (uint32_t) 0x000000FF
#define fld_VBI_PEAKWHITE_def (uint32_t) 0x000000D2
#define fld_WPA_THRESHOLD_def (uint32_t) 0x000003B0
#define fld_WPA_TRIGGER_LO_def (uint32_t) 0x000000B4
#define fld_WPA_TRIGGER_HIGH_def (uint32_t) 0x0000021C
#define fld_LOCKOUT_START_def (uint32_t) 0x00000206
#define fld_LOCKOUT_END_def (uint32_t) 0x00000021
#define fld_CH_DTO_INC_def (uint32_t) 0x00400000
#define fld_PLL_SGAIN_def (uint32_t) 0x00000001
#define fld_PLL_FGAIN_def (uint32_t) 0x00000002
#define fld_CR_BURST_GAIN_def (uint32_t) 0x0000007a
#define fld_CB_BURST_GAIN_def (uint32_t) 0x000000ac
#define fld_VERT_LOCKOUT_START_def (uint32_t) 0x00000207
#define fld_VERT_LOCKOUT_END_def (uint32_t) 0x0000000E
#define fld_H_IN_WIND_START_def (uint32_t) 0x00000070
#define fld_V_IN_WIND_START_def (uint32_t) 0x00000027
#define fld_H_OUT_WIND_WIDTH_def (uint32_t) 0x000002f4
#define fld_V_OUT_WIND_WIDTH_def (uint32_t) 0x000000f0
#define fld_HS_LINE_TOTAL_def (uint32_t) 0x0000038E
#define fld_MIN_PULSE_WIDTH_def (uint32_t) 0x0000002F
#define fld_MAX_PULSE_WIDTH_def (uint32_t) 0x00000046
#define fld_WIN_CLOSE_LIMIT_def (uint32_t) 0x0000004D
#define fld_WIN_OPEN_LIMIT_def (uint32_t) 0x000001B7
#define fld_VSYNC_INT_TRIGGER_def (uint32_t) 0x000002AA
#define fld_VSYNC_INT_HOLD_def (uint32_t) 0x0000001D
#define fld_VIN_M0_def (uint32_t) 0x00000039
#define fld_VIN_N0_def (uint32_t) 0x0000014c
#define fld_MNFLIP_EN_def (uint32_t) 0x00000000
#define fld_VIN_P_def (uint32_t) 0x00000006
#define fld_REG_CLK_SEL_def (uint32_t) 0x00000000
#define fld_VIN_M1_def (uint32_t) 0x00000000
#define fld_VIN_N1_def (uint32_t) 0x00000000
#define fld_VIN_DRIVER_SEL_def (uint32_t) 0x00000000
#define fld_VIN_MNFLIP_REQ_def (uint32_t) 0x00000000
#define fld_VIN_MNFLIP_DONE_def (uint32_t) 0x00000000
#define fld_TV_LOCK_TO_VIN_def (uint32_t) 0x00000000
#define fld_TV_P_FOR_WINCLK_def (uint32_t) 0x00000004
#define fld_VINRST_def (uint32_t) 0x00000001
#define fld_VIN_CLK_SEL_def (uint32_t) 0x00000000
#define fld_VS_FIELD_BLANK_START_def (uint32_t) 0x00000206
#define fld_VS_FIELD_BLANK_END_def (uint32_t) 0x0000000A
/*#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000105 */
#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000001
#define fld_VS_FRAME_TOTAL_def (uint32_t) 0x00000217
#define fld_SYNC_TIP_START_def (uint32_t) 0x00000372
#define fld_SYNC_TIP_LENGTH_def (uint32_t) 0x0000000F
#define fld_GAIN_FORCE_DATA_def (uint32_t) 0x00000000
#define fld_GAIN_FORCE_EN_def (uint32_t) 0x00000000
#define fld_I_CLAMP_SEL_def (uint32_t) 0x00000003
#define fld_I_AGC_SEL_def (uint32_t) 0x00000001
#define fld_EXT_CLAMP_CAP_def (uint32_t) 0x00000001
#define fld_EXT_AGC_CAP_def (uint32_t) 0x00000001
#define fld_DECI_DITHER_EN_def (uint32_t) 0x00000001
#define fld_ADC_PREFHI_def (uint32_t) 0x00000000
#define fld_ADC_CH_GAIN_SEL_def (uint32_t) 0x00000001
#define fld_HS_PLL_SGAIN_def (uint32_t) 0x00000003
#define fld_NREn_def (uint32_t) 0x00000000
#define fld_NRGainCntl_def (uint32_t) 0x00000000
#define fld_NRBWTresh_def (uint32_t) 0x00000000
#define fld_NRGCTresh_def (uint32_t) 0x00000000
#define fld_NRCoefDespeclMode_def (uint32_t) 0x00000000
#define fld_GPIO_5_OE_def (uint32_t) 0x00000000
#define fld_GPIO_6_OE_def (uint32_t) 0x00000000
#define fld_GPIO_5_OUT_def (uint32_t) 0x00000000
#define fld_GPIO_6_OUT_def (uint32_t) 0x00000000
/* End of field default values. */
#endif